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  1. The M24C08 is an 8-Kbit I. 2. C-compatible EEPROM (electrically erasable programmable memory) organized as 1 K × 8 bits. The M24C08-W can be accessed with a supply voltage from 2.5 V to 5.5 V, the M24C08-R can be accessed with a supply voltage from 1.8 V to 5.5 V, and the M24C08-F can be accessed either with a supply voltage from 1.7

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  2. Order today, ships today. M24C08-RDS6TG – EEPROM Memory IC 8Kbit I2C 400 kHz 900 ns 8-MSOP from STMicroelectronics. Pricing and Availability on millions of electronic components from Digi-Key Electronics.

    • IC EEPROM 8KBIT I2C 400KHZ 8MSOP
    • STMicroelectronics
    • M24C08-RDS6TG-ND-Tape & Reel (TR)
    • M24C08-RDS6TG
  3. 16Kbit, 8Kbit, 4Kbit, 2Kbit and 1Kbit Serial I2C Bus EEPROM, M24C08-RDS3TG/G Datasheet, M24C08-RDS3TG/G circuit, M24C08-RDS3TG/G data sheet : STMICROELECTRONICS, alldatasheet, Datasheet, Datasheet search site for Electronic Components and Semiconductors, integrated circuits, diodes, triacs and other semiconductors.

  4. M24C08-RDS6TG STMicroelectronics EEPROM 1.8-5.5V 8K (1Kx8) datasheet, inventory & pricing. Skip to Main Content. 080 42650011. Contact Mouser (Bangalore) 080 42650011

    • STMicroelectronics
    • EEPROM
    • SMD/SMT
  5. Features, Applications: Two-Wire I²C Serial Interface Supports 400kHz Protocol Single Supply Voltage: to 5.5V for to 5.5V for M24Cxx-R Write Control Input BYTE and PAGE WRITE (up to 16 Bytes) RANDOM and SEQUENTIAL READ Modes Self-Timed Programming Cycle Automatic Address Incrementing Enhanced ESD/Latch-Up Protection More than 1 Million Erase/Write Cycles More than 40-Year Data Retention ...

  6. M24C08-RDS3TG/G 16kbit, 8kbit, 4kbit, 2kbit and 1kbit Serial I2C Bus Eeprom . Two Wire I2C Serial Interface Supports 400kHz Protocol Single Supply Voltage: to 5.5V for to 5.5V for to 5.5V for M24Cxx-R Write Control Input BYTE and PAGE WRITE (up to 16 Bytes) RANDOM and SEQUENTIAL READ Modes Self-Timed Programming Cycle

  7. 19/29M24C16, M24C08, M24C04, M24C02, M24C01Table 17. AC Characteristics (M24Cxx-R)Note: 1. For a reSTART condition, or following a Write cycle.2. Sampled only, not 100% tested.3. To avoid spurious START and STOP conditions, a minimum delay is placed between SCL=1 and the falling or rising edge of SDA.4. 100kHz clock frequency is offered on the standard device. 400kHz clock frequency is offered ...