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6 days ago · EP20K160EBC356-3 Altera FPGA - Field Programmable Gate Array CPLD - APEX 20K 640 Macro 271 IOs datasheet, inventory, & pricing.
- Altera
- FPGA-Field Programmable Gate Array
- 6400 LE
- APEX 20K EP20K160E
EP20K160E Product details The Altera enhanced configuration device is a single-device, high-speed, advanced configuration solution for very high-density FPGAs. The core of an enhanced configuration device is divided into two major blocks, a configuration controller and a flash memory.
3.3-V, and 5.0-V devices (see Table 3) – Programmable clamp to V CCIO – Individual tri-state output enable control for each pin – Programmable output slew-rate control to reduce switching noise – Support for advanced I/O standards, including low-voltage differential signaling (LVDS), LVPECL, PCI-X, AGP, CTT, stub-
EP20K160E I/O Pins ver. 1.3 I/O & VREF Bank Pad Number Orientation Pin/Pad Function 144-Pin TQFP (1) 208-Pin PQFP (1) 240-Pin PQFP (1) 356-Pin BGA 484-Pin FineLine BGA 6 144 I/O 67 98 111 AF23 Y7 6 145 I/O – 97 110 AD20 U8 6 146 I/O 66 96 109 AE21 V8 6 147 I/O – – – AF22 W8 6 148 I/O 65 94 107 AF21 Y9 6 149 I/O – – 106 AE20 T9
Part #: EP20K160E. Description: 1. Enhanced Configuration Devices (EPC4, EPC8, and EPC16) Data Sheet. File Size: 456.96 Kbytes. Manufacturer: Altera Corporation.
2Altera CorporationAPEX 20K Programmable Logic Device Family Data SheetNote to Tables 1 and 2:(1)The embedded IEEE Std. 1149.1 Joint Test Action Group (JTAG) boundary-scan circuitry contributes up to57,000 additional gates.AdditionalFeatures Datasheet search, datasheets, Datasheet search site for Electronic Components and Semiconductors, integrated circuits, diodes, triacs and other ...
84Altera CorporationAPEX 20K Programmable Logic Device Family Data SheetTable 52. EP20K30E Minimum Pulse Width Timing ParametersSymbol-1-2-3UnitMin Datasheet search, datasheets, Datasheet search site for Electronic Components and Semiconductors, integrated circuits, diodes, triacs and other semiconductors.
