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TI’s CD54HC194 is a High Speed CMOS Logic 4-Bit Bidirectional Universal Shift Register. Find parameters, ordering and quality information.
Data sheet acquired from Harris Semiconductor. SCHS164G. September 1997 - Revised May 2006. CD54HC194, CD74HC194, CD74HCT194. High-Speed CMOS Logic 4-Bit Bidirectional Universal Shift Register. [ /Title (CD74 HC194, CD74H CT194) /Sub-ject (High-Speed CMOS Logic 4-Bit. Features. Four Operating Modes. Shift Right, Shift Left, Hold and Reset.
CD54HC194 (CERDIP) CD74HC194 (PDIP, SOIC, SOP, TSSOP) CD74HCT194 (PDIP) TOP VIEW Description The ’HC194 and CD74HCT194 are 4-bit shift registers with Asynchronous Master Reset (MR). In the parallel mode (S0 and S1 are high), data is loaded into the associated flip-flop and appears at the output after the positive transition of the clock ...
CD54HC194 (CERDIP) CD74HC194 (PDIP, SOIC, SOP, TSSOP) CD74HCT194 (PDIP) TOP VIEW Description The ’HC194 and CD74HCT194 are 4-bit shift registers with Asynchronous Master Reset (MR). In the parallel mode (S0 and S1 are high), data is loaded into the associated flip-flop and appears at the output after the positive transition of the clock ...
Description: Counter Shift Registers High Speed CMOS Logic 4-Bit Bidirectional Universal Shift Register 16-CDIP -55 to 125. Lifecycle: Restricted Availability: This part number is not currently available from Mouser. Product may be in limited distribution or a factory special order. Datasheet: CD54HC194F3A Datasheet. ECAD Model:
- Serial/Parallel to Parallel
- 4 bit
- Texas Instruments
- Counter Shift Registers
Description. The ’HC194 and CD74HCT194 are 4-bit shift registers with. Asynchronous Master Reset ( MR). In the parallel mode (S0. and S1 are high), data is loaded into the associated flip-flop. and appears at the output after the positive tr ansition of the.
CD54HC194 (CERDIP) CD74HC194 (PDIP, SOIC, SOP, TSSOP) CD74HCT194 (PDIP) TOP VIEW Description The ’HC194 and CD74HCT194 are 4-bit shift registers with Asynchronous Master Reset (MR). In the parallel mode (S0 and S1 are high), data is loaded into the associated flip-flop and appears at the output after the positive transition of the clock ...
