Lutton Court, Bernard Terrace, Edinburgh EH8 9NX, UK

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email:sales@wolfson.co.uk

www: http://www.wolfson.co.uk

Wolfson Microelectronics

WM8144-12

Production Data

February 1998 Rev. 4.1

Integrated 12-bit Data Acquisition System for

Imaging Applications

Description

WM8144-12 integrates the analogue signal conditioning
required by CCD sensors with a 12-bit ADC and optional
pixel-by-pixel image compensation. WM8144-12 requires
minimal external circuitry and provides a cost effective
sensor-to-digital domain system solution.

Each analogue conditioning channel provides reset level
clamp, CDS, fine offset level shifting and gain
amplification. The three channels are multiplexed into the
ADC. Output from the ADC can either be direct or passed
through a digital post-processing function. The post-
processing provides compensation for variations in offset
and shading on a pixel-by-pixel basis.

The flexible output architecture allows twelve-bit data to
be accessed either on a twelve-bit bus or via a time-
multiplexed eight-bit bus. The WM8144-12 can be
configured for pixel-by-pixel or line-by-line multiplexing
operation. Reset level clamp and/or CDS features can be
optionally bypassed. Device configuration is either by a
simple serial or eight-bit parallel interface.

Features

Block Diagram

Reset level clamp

Correlated Double Sampling (CDS)

Fine offset level shifting

Programmable Gain Amplification

12-Bit ADC with maximum 4 MSPS

Digital post-processing for pixel-by-pixel
image compensation

Simple clocking scheme

Control by serial or parallel interface

Time-multiplexed eight-bit data output mode

48 pin TQFP package

Pin compatible with WM8144-10

Applications

Document scanners

CCD sensor interfaces

Contact image sensor (CIS) interfaces

Production Data data sheets contain final
specifications current on publication date.
Supply of products conforms to Wolfson
Microelectronics standard terms and condi-
tions.

VSMP

MCLK

RLC

12 BIT
ADC

IMAGE
COMPENSATION
PROCESSING

EXTERNAL
DATA STORE
INTERFACE

12/8
MUX

CONFIGURABLE
SERIAL/PARALLEL
CONTROL INTERFACE

MUX

U
X

MID

OP[11:0]

ORNG

CDATA(7:0)

CC[2:0]

SDI / DNA

PNS

SCK / RNW

SEN / STB

OEB

RLC

VDD

GND

VDD1

VDD2

GND

TIMING CONTROL

NRESET

S/H

RINP

CDS

S/H

GINP

S/H

BINP

S/H

WM8144-12

8-BIT + SIGN
DAC

OFFSET

PGA

5-BIT REG

MID

8-BIT + SIGN
DAC

PGA

5-BIT REG

MID

8-BIT + SIGN
DAC

PGA

5-BIT REG

MID

WM8144-12

Wolfson Microelectronics

Ordering Information

Package Outline

Absolute Maximum Ratings

Analogue Supply Voltage. . . AGND - 0.3 V, AGND +7 V
Digital Supply Voltage. . . . DGND - 0.3 V, DGND +7 V
Digital Inputs . . . . . . . . .DGND - 0.3 V, DVDD + 0.3 V
Digital Outputs. . . . . . . .DGND - 0.3 V, DVDD + 0.3 V
Reference inputs . . . . . . AGND - 0.3 V, AVDD + 0.3 V
RINP, GINP, BINP . . . . . . AGND - 0.3 V, AVDD + 0.3 V

Operating temperature range, T

. . . . . . 0oC to +70oC

Storage Temperature . . . . . . . . . . -50oC to +150oC
Lead Temperature (soldering, 10 sec) . . . . . . +260oC

Note:

Absolute Maximum Ratings are stress ratings only. Permanent damage to the device may be caused by

continuously operating at or beyond these limits. Device functional operating range limits and guaranteed
performance specifications are given under Electrical Characteristics at the test conditions specified.

ESD Sensitive Device. The WM8144-12 is manufactured on a CMOS process. It is therefore generically

susceptible to damage from excessive static voltages. Proper ESD precautions must be taken during handling
and storage of this device.

As per JEDEC specifications A112-A and A113-A this product requires specific storage conditions prior to

surface mount assembly. It has been classified as having a Moisture Sensitivity level of 2 and as such will be
supplied in vacuum sealed moisture barrier bags.

Recommended Operating Conditions

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

Supply Voltage

4.75

5.25

Operating Temperature Range

Input Common Mode Range

CMR

0.5

4.5

DEVICE

TEMP RANGE

PACKAGE

WM8144-12CFT/V 0

C - 70

48 Pin TQFP

2 4

2 3

1 6

1 7

1 8

1 9

2 0

2 1

2 2

1 3

1 4

1 5

3 7

4 7

4 6

4 5

4 4

4 3

4 2

4 1

4 0

3 9

3 8

4 8

P N S

A G N D

G I N P

V R L C

V M I D

B I N P

R I N P

V R U

V R T

V R B

V R L

A V D D

OP4

OP0

OP1

DVDD2

OP2

OP3

CC2

CC1

CC0

ORNG

NRESET

O P 5

O P 1 0

O P 9

O P 8

O P 7

O P 6

C D A T A 3

C D A T A 2

C D A T A 1

C D A T A 0

D G N D

O P 1 1

CDATA4

DVDD1

VSMP

MCLK

CDATA7

CDATA6

CDATA5

OEB

SEN/STB

SDI/DNA

SCK/RNW

RLC

W M 8 1 4 4 - 1 2

WM8144-12

Wolfson Microelectronics

Electrical Characteristics

= 4.75V to 5.25V, GND = 0 V, ........T

= 0oC to +70oC, MLCK = 8MHz unless otherwise stated.

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

Supply Current - Active

110.0

150

Supply Current - Standby

10.0

Digital Inputs

High Level Input Voltage

0.8*DVDD

Low Level Input Voltage

0.2*DVDD

High Level Input Current

1.0

Low Level Input Current

1.0

Input Capacitance

10.0

Digital Outputs

High Level Output Voltage

= 1.0mA

DVDD-0.75

Voltage output range

= 1.0mA

DGND+0.75

High Impedance Output Current

1.0

Input Multiplexer

Channel to Channel Gain Matching

0.5

Input Video Set-up Time

tVSU

Input Video Hold Time

tVH

Reset Video Set-up Time

tRSU CDS Mode only

Reset Video Hold Time

tRH

CDS Mode only

Reference String

Reference Voltage - Top

= 5.00 V, V

= 0.00V

3.465

3.5

3.535

Reference Voltage - Bottom

= 5.00 V, V

= 0.00V

1.465

1.5

1.535

DAC Reference Voltage

MID

= 5.00 V, V

= 0.00V

2.475

2.5

2.525

R.L.C. Switch Impedence

200

Ohms

Reset Level Clamp Options

RLC

= 5.00 V, V

= 0.00V

1.425

1.5

1.575

Voltage set by user

2.375

2.5

2.625

configuration - Table 7

3.325

3.5

3.675

Impedance V

to V

490

700

910 Ohms

Impedance V

to V

1190

1700

2210 Ohms

8-bit DACs

Resolution

Bits

Zero Code Voltage

DAC

-10

DAC

+10

Full Scale Voltage Error

Differential Non Linearity

DNL

0.1

1 LSB

Integral Non Linearity

INL

0.4

1 LSB

WM8144-12

Wolfson Microelectronics

Electrical Characteristics (Contd.)

= 4.75V to 5.25V, GND = 0 V, ........T

= 0oC to +70oC, MCLK = 8MHz unless otherwise stated.

Note 1: Guaranteed monotonic up to PGA Gain code 1Fh

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

Resolution

= 5V

Bits

Maximum Sampling Rate

= 5V

MSPS

Full Scale Transition Error Voltage at
VINP

DAC Code = 000H, V

=5V,

measured relative to VRT

+/-50

+/-200

Zero Scale Transition Error Voltage
at VINP

DAC Code = 000H, V

=5V,

measured relative to VRB

+/-50

+/-200

Differential Non Linearity

DNL

= 5V

+1.5 LSB

Number of missing codes

4 Code

PGA Gain

Red Channel Max. Gain, Note 1

VDD=5V

Times

Green Channel Max. Gain, Note 1

Mode=1

Times

Blue Channel Max. Gain, Note 1

Times

12-Bit ADC including CDS, PGA and offset functions

WM8144-12

Wolfson Microelectronics

Electrical Characteristics (Contd.)

= 4.75V to 5.25V, GND = 0 V, ........T

= 0oC to +70oC, MCLK = 8MHz unless otherwise stated.

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

Switching Characteristics

MCLK Period

tPER

125

MCLK High

tCKH

37.5

MCLK Low

tCKL

37.5

Data Set-up time

tDSU

VSMP, RLC Data Hold Time

tDH

CDATA Data Hold Time

tDH

Output Propagation Delay

tPD

= 1.0mA

Output Enable TIme

tPZE I

= 1.0mA

Output Disable Time

tPEZ

Serial Interface

SCK Period

tSPER

125

SCK High

tSCKH

37.5

SCK Low

tSCKL

37.5

SDI Set up time

tSSU

SDI Hold Time

tSH

Set up time - SCK to SEN

tSCE

Set up time - SEN to SCK

tSEC

SEN Pulse Width

tSEW

Parallel Interface

RNW Low to OP[11:4] Tristate

tOPZ

Address Setup Time to STB Low

tASU

DNA Low Setup Time to STB Low

tADLS

Strobe Low Time

tSTB

Address Hold Time from STB High

tAH

DNA Low Hold Time from STB High

tADLH

Data Set-up Time to STB Low

tDSU

DNA High Setup Time to STB Low

tADHS

Data Hold Time from STB High

tDH

DNA High Hold Time from STB High tADHH

RNW High to OP[11:4] Output

tOPD

WM8144-12

Wolfson Microelectronics

Pin Descriptions

Pin No.

Name

Type

Description

RINP

Analogue IP

Red Channel input video

GINP

Analogue IP

Green Channel input video

BINP

Analogue IP

Blue Channel input video

CDATA[7]

Digital IO

Image compensation data read/write at twice ADC conversion rate

CDATA[6]

Digital IO

CDATA[5]

Digital IO

CDATA[4]

Digital IO

CDATA[3]

Digital IO

CDATA[2]

Digital IO

CDATA[1]

Digital IO

CDATA[0]

Digital IO

MCLK

Digital IP

Master clock. This clock is applied at either six, four or two times the input
pixel rate depending on the operational mode. MCLK is divided internally
to define the ADC samples rate and to provide the clock source for digital
logic.

VSMP

Digital IP

Video sample synchronisation pulse. This signal is applied synchronously
with MLCK to specify the point in time that the input is sampled. The timing
of internal multiplexing between the R, G and B channels is derived from
this signal

RLC

Digital IP

Selects whether reset level clamp is applied on a pixel-by-pixel basis. If
RLC is required on each pixel then this pin can be tied high

RLC

Analogue OP

Selectable analogue output voltage for RLC

Analogue IP

ADC reference voltages. The ADC reference range is applied between

Analogue IP

(full scale) and V

(zero level). V

and V

can be used to

Analogue IP

derive optimum reference voltages from an external 5V reference

Analogue IP

MID

Analogue OP

Buffered mid-point of ADC reference string.

OP[11]

Digital IO

Tri-state digital 10-bit bi-directional bus. There are four modes:

OP[10]

Digital IO

Tri-state: when OEB = 1

OP[9]

Digital IO

Output twelve-bit: twelve bit data is output from bus

OP[8]

Digital IO

Output 8-bit multiplexed: data output on OP[11:4] at 2 * ADC conversion
rate

OP[7]

Digital IO

Input 8-bit: control data is input on bits OP[11:4]

OP[6]

Digital IO

OP[5]

Digital IO

OP[4]

Digital IO

OP[3]

Digital IO

OP[2]

Digital IO

OP[1]

Digital IO

OP[0]

Digital IO

WM8144-12

Wolfson Microelectronics

Pin Descriptions (contd.)

Pin No.

Name

Type

Description

CC[2]

Digital OP

Colour code outputs. These outputs indicate from which channel the

CC[1]

Digital OP

current output sample was taken (R = 00X, G = 01X, B = 10X).

CC[0]

Digital OP

Two codes are provided per channel.

ORNG

Digital OP

Out-of-range signal, active high. This signal indicates that the current
output pixel has exceeded the maximum or minimum achievable
somewhere within the pixel processing.

OEB

Digital IP

Output tri-state control, all outputs enabled when OEB=0

Digital OP

Data valid output, active low.

NRESET

Digital IP

Reset input, active low. This signal forces a reset of all internal registers.

PNS

Digital IP

Control interface parallel (high) or serial (low, default)

SDI/DNA

Digital IP

Serial Interface: serial interface input data signal

Parallel interface: high = data, low = address

SCK/RNW

Digital IP

Serial Interface: serial interface clock signal

Parallel interface: high = OP[11:4] is output, low = OP[11:4] is input bus

SEN/STB

Digital IP

Serial Interface: enable, active high

Parallel interface: strobe, active low

DVDD1

Digital supply

Positive Digital Supply (5V)

DVDD2

Digital supply

Positive Digital Supply (5V)

DGND

Digital supply

Digital ground (0V)

AVDD

Analogue supply Positive Analogue supply (5V)

AGND

Analogue supply Analogue Ground (0V)

WM8144-12

Wolfson Microelectronics

Gain DNL

-5

-4

-3

-2

-1

Gain

Red

Green

Blue

MCLK = 8MHz. Input 2.5V +/- 100mV. Other 2 are at 2.5V. Colour. Vdd =

-1

-0.8

-0.6

-0.4

-0.2

0.2

0.4

0.6

0.8

512

1024

1536

2048

2560

3072

3584

4096

ADC Code

LSB's

-5

-4

-3

-2

-1

512

1024

1536

2048

2560

3072

3584

4096

ADC Code

LSB's

Typical Performance

= 5V, GND = 0 V, ........T

= 25oC.

ADC 12 Bit DNL

PGA Gain

Gain

Red

Green

Blue

MCLK = 8MHz. Input set to 2.5V +/- 100mV. Other 2 are at 2.5V Colour.

ADC 12 Bit INL

PGA DNL @ MCLK = 8MHz

PGA Gain Code vs. Actual Gain
@ MCLK = 8MHz

Actual Gain

PGA Gain Code

ADC Code

LSB's

ADC Code

LSB's

DNL

PGA Gain Code

WM8144-12

Wolfson Microelectronics

The WM8144-12 is configured to output 12-bit data by
writing to Setup Register 4: Bit 4 'Mode12'. By default
the device is configured to output 10-bit data.

S/H, Offset DAC's and PGA
Each analogue input (RINP, GINP, BINP) of the WM8144-
12 consists of a sample and hold, a programmable gain
amplifier, and a DC offset correction block. The operation
of the red input stage is summarised in Figure 1.

S/H

Gain=G

VMID

VADC

VMID

Voffset

RINP

Figure 1

The sample/hold block can operate in two modes of op-
eration, CDS (Correlated Double Sampling) or Single Ended.
In CDS operation the video signal processed is the differ-
ence between the voltage applied at the RINP input when
RS occurs, and the voltage at the RINP input when VS
occurs. This is summarised in Figure 2.

Vrs

Vvs

Figure 2

When using CDS the actual DC value of the input signal is
not important, as long as the signal extremes are main-
tained within 0.5 volts of the chip power supplies. This is
because the signal processed is the difference between
the two sample voltages, with the common DC voltage
being rejected.
In single ended operation, the VS and RS control signals
occur simultaneously, and the voltage applied to the re-
set switch is fixed at V

MID

. This means that the voltage

processed is the difference between the voltage applied
to RINP when VS/RS occurs, and V

MID

. When using Sin-

gle ended operation the DC content of the video signal is
not rejected.
The Programmable Gain Amplifier block multiplies the re-
sulting input voltage by a value between 0.5 and 8.25
which can be programmed independently for each of the
three input channels via the serial (or parallel) interface.
PGA gain is dependent on the 5-bit binary code pro-
grammed in the PGA registers. A typical plot of PGA
Code versus Actual Gain is shown on Page 8.

The DC value of the gained signal can then be trimmed by
the 8 bit plus sign DAC. The voltage output by this DAC is
shown as Voffset in Figure 1. The range of the DAC is
(V

MID

/2).

The output from the offset DAC stage is referenced to
the V

MID

voltage. This allows the input to the ADC to

maximise the dynamic range, and is shown diagrammati-
cally in Figure 1 by the final VMID addition.
For the input stage the final analogue voltage applied to
the ADC can be expressed as:

(

)

(

)

VADC

G Vvs

Vrs

1 2 * Sign *

DAC_ CODE

255

VMID

Where: V

ADC

is the voltage applied to the ADC

G is the programmed gain
Vvs is the voltage of the video sample
Vrs is the voltage of the reset sample
Sign is the Offset DAC sign bit
DAC_CODE is the offset DAC value
V

MID

is the WM8144-12 generated V

MID

voltage

The ADC has a lower reference of V

(typically 1.5 V)

and an upper reference of V

(typically 3.5 V). When

an ADC input voltage is applied to the ADC equal to VRB
the resulting code is 000(hex). When an ADC input volt-
age is applied to the ADC equal to V

the resulting code

is FFF(hex).

Reset Level Clamp
Both CDS and Single ended operation can be used with
Reset Level Clamping. A typical input configuration is
shown in Figure 3.

S/H

Gain=G

VMID

VRLC

RINP

Cin

WM8144

Figure 3

Theory of Operation

WM8144-12

Wolfson Microelectronics

Theory of Operation (contd.)

The position of the clamp relative to the video sample is
programmable by CDSREF1-0 (see Table 7). By default,
the reset sample occurs on the fourth MCLK rising edge
after VSMP. The relative timing between the reset sam-
ple ( and CL) and video sample can be altered as shown
in Figure 4.

Figure 4: Reset Sample and Clamp Timing

When the clamp pulse is active the voltage on the
WM8144-12 side of Cin, i.e. RINP, will be forced to be
equal to the VRLC clamp voltage (see Figure 5). The
VRLC clamp voltage is programmable to three different
levels via the serial interface (1.5V, 2.5V or 3.5V). The
voltage to which the clamp voltage should be programmed
is dependent on the type of sampling selected and the
polarity of the input video signal. For CDS operation it is
important to match the clamp voltage to the amplitude and
polarity of the video signal. This will allow the best use of
the wide input common-mode range offered by the
WM8144-12. If the input video is positive going it is advis-
able to clamp to Vcl (Lower clamp voltage). If the video is
negative going it is advisable to clamp to Vcu (Upper
clamp voltage). Regardless of where the video is clamped
the offset DAC is programmed to move the ADC output
corresponding to the reset level to an appropriate value
to maximise the ADC dynamic range. For Single Ended
operation it is recommended that the clamp voltage is set
to Vcm (Middle clamp voltage).

Clamp Pulse

Video Input

Figure 5

A reset level clamp is activated if the RLC pin is high on
an MCLK rising edge (Figure 6). By default this initiates
an internal clamp pulse three MCLK pulses later (Figure
4: CL). The relationship between CL and RS is fixed.
Therefore altering the RS position also alters the CL po-
sition (Figure 4). Table 7 shows the three possible
voltages to which the reset level can be clamped.

Figure 6: RLC Timing

RINP, GINP and BINP Input Impedence
The input impedence of the WM8144-12 analogue inputs
is dependent on the sampling frequency of the input sig-
nal and the configuration of the internal gain amplifiers.

The input impedence = 1/(Capacitance * frequency)

where the Capacitance value changes from 0.3pF for
minimum gain to 9.6pF for maximum gain. Table 1 illus-
trates the minimum and maximum input impedence at dif-
ferent frequencies.

Table 1: Effects of Frequency on Input Impedence

Sampling

Frequency

(MHz)

Impedence with

minimum gain

)

Impedence with

maximum gain

)

0.5

6.6

208

3.3

104

1.6

0.8

WM8144-12

Wolfson Microelectronics

For a white pixel:

= V

- 1.6

For the white pixel, using the same offset DAC value, the
ADC input can be expressed as:

When the VMID is 2.5V, the ADC input voltage becomes
1.7 volts which will result in a code of 409(dec). This is
near the ideal full-scale of 000(dec).

Therefore the output codes from the ADC are between
3686(dec) and 409(dec), which implies that the ADC
input has been set up to maximise the dynamic range
available. If a digital representation of the ADC output
with a black level near 000(dec) and a white level near
4095(dec) is required then the INVOP control bit should

now be set to ONE.

Theory of Operation (Contd)

= 1*(V

- V

) + (1 - 2*0) * * + V

ADC

MID

= 0 + * V

+ V

ADC

MID

= * V

ADC

MID

164 V

MID

337

255

255 2

= 1*(V

- 1.6 - V

) + (1 - 2*0) * * + V

ADC

MID

= -1.6 + * V

+ V

ADC

MID

= * V

- 1.6

ADC

MID

164 V

MID

337

255

255 2

Example of Gain and Offset Operation
Input Video polarity

negative

Input sampling

CDS

Input voltage amplitude (V

- V

)

1.6V

Programmable gain

Clamping

Yes, V

= 3.5V

After the input capacitor the input to the WM8144-12 can
be represented as:

Vrs

Vvs

Figure 7

For a black pixel:

= V

Assuming that the offset DAC is set to 00dec:

(

)

(

)

VADC = 1* Vcl - Vcl

VADC

0 + 0 + VMID

VADC = VMID

1 2 0

255

VMID

An input voltage of V

MID

corresponds to a code of

2048(dec) from the ADC.

To maximise the dynamic range of the ADC input it is
necessary to program the offset DAC code to move the
ADC code corresponding to the black level towards code
4096(dec).

Hence set the offset DAC to 164(dec) with the sign bit
not set.

When the VMID is 2.5v, the ADC input voltage becomes
3.3 volts which will result in an ADC code of 3686(dec).
This is near the ideal full-scale of 4095(dec).

WM8144-12

Wolfson Microelectronics

PIXEL OFFSET

ADDER

LIMIT

MUX

DEFAULT

MUX

PIXEL GAIN

ADJUST

LIMIT

DATA VALID

GENERATION

DATA

PARTITIONING

DEMUX

AND MUX

DATA

LATCH

OUT OF RANGE

GENERATION

4,5 or 6

12,11 or 10

ADC

ORNG INPUT TO
12/8 MUX BLOCK

OP[11:0] INPUT TO
12/8 MUX BLOCK

DV OUTPUT

ADCOP

CDATA

DEFAULT

Figure 12

Digital Signal Processing
By default, the output from the ADC passes through the
digital compensation block without being altered and is
output directly on the OP[11:0] pins. If required, the pixel
data from the ADC can be processed further by the
digital compensation block (Figure 8). This section de-
scribes the sub-blocks of the digital compensation block.

CDATA Demultiplexor
The input to this block is coefficient data presented to the
CDATA[7:0] pins at twice the pixel rate. i.e. two eight-bit
words are input for each pixel of video data.

Data Partitioning
The sixteen bits of data per pixel from the CDATA
Demultiplexor is partitioned into pixel offset, pixel gain
and pixel valid bits (Table 3). Table 4 details the resulting
range and resolution options.

Pixel Offset Adder
This uses the offset coefficients that are either supplied
externally via the CDATA interface or from the internal
default registers. The object of this block is to correct for
the small offsets which can occur from the CCD on a
pixel-by-pixel basis. The output from the Pixel Offset
Adder is limited to be between 0 and 4095(dec).

Pixel Gain Adjust
This block corrects for the pixel-by-pixel shading curve
non-uniformity and photo response non-uniformity within
the CCD sensor. This block has a gain range of 0 to 2.
The output word from the Pixel Gain Adjust is limited to
between 0 and 4095(dec).

Effect of digital compensation on ADC output
The combined effect of the digital compensation sec-
tions on the ADC output is summarised by the formula:

OP[11:0] = (ADCOP + POC) * PSCF

where:
All values are decimal
OP[11:0] is the 12 bit result output from the WM8144-12
ADCOP is a 12 bit unsigned number from the ADC
POC is a 2's compliment number divided byNUMBER OF
POC BITS ALLOCATED incrementing in steps of four (e.g.
-32,-28,-24.....24,28)
PSCF is an unsigned number divided by NUMBER OF PSC
BITS ALLOCATED/2

For this example assume PSC is allocated 12 bits and
POC is allocated 4 bits (refer to table
3:DVMODE,PWP0,PWP1 = 0). Table 2 shows some ex-
amples of the effect of the digital backend on the ADC
output.

ADCOP

POC

PSC

OP[11:0]

ORNG

Range

0:4095

-32:28

0:4095

0:1

Default

2048 (x1)

Ex 1

2048

Ex 2

2048

-32

2048

2016

Ex 3

2048

2056

Ex 4

4091

2048

4095

Ex 5

4091

512

1023

Ex 6

2048

2560

Ex 7

2048

512

Ex 8

2049

4095

Ex 9

2048

4095

Table 2: Examples of digital backend calculation

Theory of Operation (contd.)

Figure 8

WM8144-12

Wolfson Microelectronics

Table 3: Bit Allocation Assignment

CDATA WORD 1

CDATA WORD 2

D
V

M
O

D
E

G11 G10 G9

G10 G9

Table 4: Bit Range and Resolution Options

Theory of Operation (contd.)

Data Valid Generation
The DV pin can be controlled to determine whether a DV
pulse will be generated for a particular pixel. For exam-
ple, if red pixels only are required the following DV pulse
can be generated.

OP[11:0]

Figure 9

Data Latch
Under control of the LATCHOP bit the output data bus
can be prevented from clamping until the next Data Valid
pulse. Hence the above output would become:

OP[11:0]

Figure 10

DVMODE PWP1 PWP0 No. of

offset

bits

offset range

No. of gain

bits

gain

range

gain

resolution

(LSB

steps)

DV bits

-32 : 28

0:2

-64 : 56

0:2

-128 : 112

0:2

-32 : 28

0:2

-64 : 56

0:2

Output data interface
Typically, data is output from the device as a twelve-bit
wide word on OP[11:0] - assuming the MODE12 bit is
set. Optionally, data can be output in an eight-bit word
format. Figure 11 shows this function. Data is presented

on pins OP[11:4] at twice pixel rate.

A = d11,d10,d9,d8,d7,d6,d5,d4
B = d3,d2,d1,d0,X,X,X,ORNG

Figure 11: Eight-bit Multiplexed Bus
Output

MCLK

OP[11:4]

CC[1]

CC[0]

CC[2]

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Operating Modes

Video Sampling Options
WM8144-12 can interface to CCD sensors using four
basic modes of operation ( summarised in Table 5). Mode
configurations are controlled by a combination of control
bits and timing applied to MCLK and VMSP pins. The de-
fault operational mode is mode 1: colour with CDS ena-
bled.

Colour mode definition (mode 1)
Figure 12 summarises the timing relationships within the
Colour mode. MCLK is applied at twice the required ADC
conversion rate. Synchronisation of sampling and chan-
nel multiplexing to the incoming video signal is performed
by the VSMP pulse (active high). The three input chan-
nels (R,G,B) are sampled in parallel on the rising edge of
MCLK following a VSMP pulse. The sampled data is mul-
tiplexed into a single data stream at three times the VSMP
rate and passes through the internal pipeline and emerges
on the OP[11:0] bus 20.5 MCLK periods later.
If the digital post-processing stage is activated, compen-
sation data will be clocked into the device at twice the
ADC conversion rate (e.g. two reads per red pixel ). The
first of the two bytes will be required on the CDATA bus
15.5 MCLK periods after the corresponding VSMP pulse.
CC[2:0] can be used to control the three lower address
lines of an external RAM. Both Correlated Double Sam-
pling (CDS) and Single Ended modes of operation are
available.

Monochrome mode definitions
One input channel is continuously sampled on the rising
edge of MCLK following a VSMP pulse. The user can
specify which input channel (R,G,B) to be sampled by
writing to WM8144-12 internal control registers. There
are three separate monochrome modes with different
maximum sample rates and CDS availability.

Details of Monochrome mode timing (mode 2)
Figure 13 summarises the timing relationships. The timing
in this mode is identical to mode 1 except for the CC[2:0]
outputs. One input channel is sampled three times ( due
to the multiplexer being held in one position) and passes
through the device as three separate samples. Two of
the samples can be ignored at the output. The CC[2:1]
output pins reflect the input channel selected (R,G or B).

Details of Fast Monochrome mode timing
(mode 3)
Figure 14 summarises the timing relationships. This mode
allows the maximum sample rate to be increased to 2.66
MSPS. This is achieved by altering the MCLK:VSMP ratio

to 3:1. In this mode, the timing of RS and CL must be
fixed (refer to Table 5).
The sampled video data will pass through the internal
pipeline and emerge on the OP[11:0] bus 29.5 MCLK
periods later.
If the digital post-processing stage is activated com-
pensation data will be clocked into the device at twice
the internal pixel rate (e.g. two reads per red pixel ).
The first of the two bytes will be required on the CDATA
bus 22.5 MCLK periods after the corresponding VSMP
pulse.
Details of Max. Speed Monochrome mode
(mode 4)
Figure 15 summarises the timing relationships. This
mode allows the maximum sample rate to be increased
to 4 MSPS. This is achieved by altering the MCLK:VSMP
ratio to 2:1. The latency through the device is identical
to modes 1 and 2. CDS is not available in this mode.

WM8144-12

Wolfson Microelectronics

able 5: WM8144-12 Mode Summary

Theory of Operation (contd.)

Mode

Description

CDS

available

Max.

Sample

Rate

Sensor Interface

Description

Timing Requirements

Register Contents

with CDS*

Register Contents

without CDS*

Colour

Yes

1.33

MSPS

The three input
channels (R,G,B) are
sampled in parallel at
max. 2MSPS. The
sampled data is
multiplexed into a
single data stream
before the internal
ADC giving an
internal serial data
rate of max. 4MSPS.

MCLK max. 8MHz.
MCLK:VSMP ratio is 6:1.

Setup Reg 1: 1B(H)

Setup Reg 1: 19(H)

Monochrome

Yes

1.33

MSPS

One input channel is
continuously
sampled. The internal
multiplexer is held in
one position under
control of the user.

Identical to Mode 1

Setup Reg 1: 1F(H)
Setup Reg 3: bits
b[7-6] define which
channel to be
sampled

Setup Reg 1: 1D(H)
Setup Reg 3: bits b[7-
6] define which
channel to be
sampled

Fast
Monochrome

Yes

2.66

MSPS

Identical to Mode 2

MCLK max. 8MHz.
MCLK:VSMP ratio is 3:1.

Identical to Mode 2
plus Setup Reg 3: bits
b[5-4] must be set to
00(H)

Identical to Mode 2

Max Speed
Monochrome

4 MSPS Identical to Mode 2

MCLK max. 8MHz.
MCLK:VSMP ratio is 2:1.

Not Applicable

Setup Reg 1: 5D(H)
Setup Reg 3: bits b[7-
6] define which
channel to be
sampled

* Only indicates relevant register bits

WM8144-12

Wolfson Microelectronics

Device timing for mode 2

Figure 13: Default Timing in CDS Monochrome Mode

Operating Modes (contd.)

CDA

A[7:0]

ADC sample

Input video

r1,g1,b1

r2,g2,b2

r3,g3,b3

r4,g4,b4

r5,g5,b5

VSMP

MCLK

20.5 MCLK periods

r1:1

r1:2

2345

OP[1

1:0]*

CC[1]*

CC[0]

ORNG

CC[2]*

INPUT SIGNALS

INTERNAL SIGNALS

OUTPUT SIGNALS

* This example shows function when Red channel selected. CC[1] and CC[2] indicate the selected channel (R,G or B)

15.5 MCLK periods

0000000000000

CC[2:1]

ADC input

XXXX

XXX

'X' indicates don't care

WM8144-12

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Figure 16: Serial Interface Timing

Figure 17: Parallel Interface Timing

Configuration of the WM8144-12

The WM8144-12 can be configured through a serial
interface or a parallel interface. Selection of the
interface type is by the PNS pin which must be tied
high (parallel) or low (serial).

Serial Interface
The serial interface consists of three pins (refer to
figure 16 ). A six-bit address is clocked in MSB first
followed by an eight-bit data word, also MSB first.
Each bit is latched on the rising edge of SCK, which
can operate at up to 8MHz. Once the data has been
shifted into the device, a pulse is applied to SEN to
transfer the data to the appropriate internal register.

Parallel Interface
The parallel interface uses bits [11:4] of the OP bus as
well as the STB, DNA and RNW pins (refer to figure
17). Pin RNW must be low during a write operation.
The DNA pin defines whether the data byte is address
(low) or data (high). The data bus OP[11:4] is latched in
during the low period of STB. This interface is
compatible with the Extended Parallel Port interface.

Internal Register Definition
Table 6 summarises the internal register content. The
first 4 addresses in the table are used to program setup
registers and to provide a software reset feature ( 00H
is reserved ). The remaining 7 entries in the table define

Table 6: Register Map Contents

the address location of internal data registers. In each
case, a further three sub-addresses are defined for the
red, green and blue register. Selection between the red,
green and blue registers is performed by address bits a1
and a0, as defined in the table. Setting both a1 and a0
equal to 1 forces all three registers to be updated to the
same data value. Blank entries can be taken as 'don't care'
values.

OP[11:4]

Address

Data

RNW

STB

DNA

Address

Description

Def'lt

Bit

<a5:a0>

(Hex)

000000 Reserved
000001 Setup Register 1

DVMODE

VSMP4M

DEFDV

DEFPO

DEFPG

MONO

CDS

ENADC

000010 Setup Register 2

CDATOUT

BYPASS

LATCHOP

INVOP

MUXOP

000011 Setup Register 3

CHAN[1]

CHAN[0]

CDSREF[1] CDSREF[0]

PWP[1]

PWP[0]

RLC[1]

RLC[0]

000100 Software Reset

000101 Setup Register 4

MODE12

DACRNG

1000xx DAC values

DAC[7]

DAC[6]

DAC[5]

DAC[4]

DAC[3]

DAC[2]

DAC[1]

DAC[0]

1001xx DAC signs

DSIGN

1010xx PGA Gains

PGA[4]

PGA[3]

PGA[2]

PGA[1]

PGA[0]

1011xx Pixel Offsets

OFF[5]

OFF[4]

OFF[3]

OFF[2]

OFF[1]

OFF[0]

1100xx Pixel Gain MSB

GAIN[11]

GAIN[10]

GAIN[9]

GAIN[8]

GAIN[7]

GAIN[6]

GAIN[5]

GAIN[4]

1101xx Pixel Gain LSB

GAIN[3]

GAIN[2]

GAIN[1]

GAIN[0]

1110xx Data Valid

Address LSB decode

Red Register

Green Register

Blue Register

Red, Green and Blue

WM8144-12

Wolfson Microelectronics

Configuration of the WM8144-12 (Contd.)

Table 7: Control Bit Descriptions

Register

Bit

Bit(s)

Default Description

Setup

ENADC

ADC standby control: 0 = standby, 1 = active

CDS

Select Correlated double sampling mode: 0 = normal sampling, 1 =
CDS mode

MONO

Mono/Colour select: 0 = colour, 1 = monochrome operation

DEFPG

Select Default Pixel Gain: 0 = external pixel gain, 1 = internal

DEFPO

Select Default Pixel Offsets: 0 = external pixel offsets, 1 = internal

DEFDV

Select default internal Data Valid: 0 = external DV, 1 = internal

VSMP4M

Required when in mode 4: 0 = other mode, 1 = mode 4

DVMODE

External Data Valid control (refer to Bit Allocation Assignment table)

Setup

MUXOP

Eight bit output mode: 0 = twelve-bit, 1 = 8-bit multiplexed

1
2

INVOP

Inverts ADC output: 0 = non-inverting, 1 = inverting

LATCHOP

OP bus updated on DV pulse; OP bus updated each sample, 1 = update
only on DV pulse

BYPASS

Bypass digital post-processing; 0 = no bypass, 1 = bypass

CDATOUT

Data on OP pins available on CDAT pins; 0 = no, 1 = yes

6
7

Setup

1-0

RLC1-0

Reset Level Clamp voltage

00 = 1.5V
01 = 2.5V
10 = 3.5V
11 = Reserved

3-2

PWP1-0

Parallel Word Partitioning
See Bit Allocation Assignment (Table 3)

5-4

CDSREF1-0

CDS Mode Reset Timing Adjust
00 = Advance 1 MCLK Period
01 = Normal
10 = Retard 1 MCLK Period
11 = Retard 2 MCLK Period

7-6

CHAN1-0

Monochrome mode channel select
00 = Red Channel
01 = Green Channel
10 = Blue Channel
11 = Reserved

Setup
Register 4

DACRNG

Alters range of offset DAC output
0 = DAC output range equal to Vmid/2 (1.25V)
1= DAC output range equal to 1.5 *Vmid/2 (1.875V)

MODE12

Enable 12-bit ADC output: 0 = ten-bit, 1 = twelve-bit

WM8144-12

Wolfson Microelectronics

Figure 22: Detailed Video Input Timing - Mode 4

Figure 23: Detailed Digital Timing - Mode 4

Detailed timing Diagrams (Contd.)

Figure 20: Detailed Video Input Timing - Mode 3

Figure 21: Detailed Digital Timing - Mode 3

Detailed timing Diagrams (Contd.)

CKH

CKL

DSU

PER

MCLK

VSMP, RLC

OP[11:0]

DSU

CDATA[7:0]

WORD 1

WORD 2

CC[0]

CKH

CKL

DSU

PER

MCLK

VSMP, RLC

OP[11:0]

DSU

CDATA[7:0]

WM8144-12

Wolfson Microelectronics

External component recommendations

A G N D

1 0 1 1 1 2

3 6 3 5 3 4 3 3 3 2 3 1 3 0 2 9 2 8 2 7 2 6 2 5

3 7

3 8

3 9

4 0

4 1

4 2

4 3

4 4

4 5

4 6

4 7

4 8

2 4

2 3

2 2

2 1

2 0

1 9

1 8

1 7

1 6

1 5

1 4

1 3

OEB

SEN/STB

SDI/DNA

SCK/RNW

RLC

DVDD1

VSMP

MCLK

CDATA7

CDATA6

CDATA5

CDATA4

C D A T A 3

C D A T A 2

C D A T A 1

C D A T A 0

D G N D

O P 1 1

O P 1 0

O P 9

O P 8

O P 7

O P 6

O P 5

P N S

R I N P

G I N P

B I N P

V M I D

V R L C

A G N D

A V D D

V R L

V R U

V R B

V R T

C 1

1 0

C 2

0.1

C 3

0.1

D G N D

A G N D

A V D D

C 7

3 3

C 6

0.1

C 5

2 2

C 8

0.1

W M 8 1 4 4 - 1 2

A G N D

C 1 1

C 1 0

0.1

C 9

C 1 2

0 . 1

NRESET

ORNG

CC0

CC1

CC2

OP0

OP1

DVDD2

OP2

OP3

OP4

C 1 3

C 1 4
0.1

D V D D

C 1 5

C 1 6

0.1

D G N D

Part Number WM8144-12