W83759A

ADVANCED VL-IDE DISK CONTROLLER

Publication Release Date: May 1995

- 1 -

Revision A1

GENERAL DESCRIPTION

The W83759A is an advanced version of Winbond's popular VL-IDE interface chip, the W83759. The
W83759A retains all of the features and compatibility of the W83759 (the chip meets the ANSI ATA
4.0 specification for IDE hard disk operation and the VESA VL-Bus 2.0 specification for PC local bus
devices) while incorporating new features to meet Enhanced IDE, SFF-8011, ATA-2, and Fast-ATA
specifications.

Supports Disk Capacity of Greater than 528 MB

The W83759A's driver can handle remapping from BIOS CHS mode to HDD LBA mode. This scheme
enables users to break the 528 MB per drive barrier, allowing full use of BIOS INT13 CHS information
in drives with a capacity of up to 8.4 GB.

High Speed Host Transfer Rate

The W83759A supports Enhanced IDE PIO mode 3 and Fast ATA PIO mode 3 and 4 timing; jumper
settings or driver programming can be used to select the PIO mode and a 33 or 50 MHz VL-Bus
clock. Different programming timing can be selected for different drives in the same system. The
burst transfer rate is shown in the following table.

ATA PIO

MODE

IDE COMMAND CYCLE

TIME (nS)

BURST TRANSFER

RATE (MB/sec)

IORDY THROTTLE

CONTROL

600

3.33

Option

383

5.22

Option

240

8.33

Option

180

11.1

Required

120

16.6

Required

Dual IDE Channels

Like the W83759, the W83759A supports a secondary IDE address (170h-177h/376h) and IRQ15 for
applications with four hard disk drives. Additionally, the primary and secondary channels can be
independently enabled or disabled by jumper settings or software programming.

Non-disk IDE Peripherals

Because the command cycle can be programmed individually for each drive and dual IDE channels
are supported, non-disk IDE peripherals (such as an ATAPI CD-ROM or tape drive) can be attached
to the secondary IDE without affecting the transfer rate of the ATA disk drive. Sales of ATAPI IDE
CD-ROMs are expected to grow rapidly as these devices become a standard part of many users'
desktop PC setup.

W83759A

- 2 -

Enhanced IDE/Fast ATA Dual Channel Structure

Primary Channel

40-pins

Disk

< 8.4 GB

Secondary Channel

40-pins

CD ROM

Tape

ATAPI

PD0

PD1

SD0

SD1

The W83759A provides all of the next-generation ATA-IDE requirements, including support for high
capacity disk drives, high speed host transfers, multiple IDE peripherals, and non-disk IDE
peripherals. It makes high-performance, low-cost, easy-to-use IDE machines possible.

The W83759A is pin-to-pin backward compatible with the W83759. In addition to the advanced
features described above, the W83759A supports automatic power-down, standby, and suspend APM
power management states for green PC applications. This new chip is packaged in a 100-pin QFP.

The table below compares the W83759 and W83759A:

W83759

W83759A

Dual Channel IDE

Yes

8.4 G Max. Cap.

Software Driving

PIO Mode 3, 4 Control

Yes*

DMA Mode Control

Yes*

IOCHRDY Control

Yes*

IDE Timing Control

Jumper

Jumper or Driver*

Prefetch Control

Yes*

Power Saving Control

Yes*

ATAPI Protocol

Software Driving

* All control is drive-by-drive (per drive selectability)

W83759A

Publication Release Date: May 1995

- 3 -

Revision A1

FEATURES

Pin-to-pin backward compatible with W83759 VL-IDE Interface chip

VESA VL-Bus Rev 2.0 compatible, connects directly to local bus and four IDE drives

Direct interface to various ANSI ATA/ATA-2/FAST ATA/IDE-2/Enhanced IDE drives

Supports 32 and 16-bit data transfer

Fully software programmable for command active/recovery time and address setup, data hold
time

Built-in VL-Bus to 16-bit IO data buffer for special applications

Fully supports Enhanced IDE features, including Fast PIO, Mode 3/4, IORDY flow control,
prefetch control

Supports dual channels to allow up to four drives or non-disk devices (ATAPI CD-ROM and tape
drives)

Pipeline pre-fetched reads and posted writes for concurrent disk and host operations

Independent access timing for all drives (primary/secondary and master/slave)

All Enhanced IDE new features may be disabled/enabled via driver or power-on setting by per
drive selectability

ATA/Mode 0-4 PIO speed may be set as default timing of each drive via power-on jumper setting

Supports slave DMA mode protocol (reserved)

Supports auto power-down, standby, suspend APM power management state for green PCs

Primary and secondary channel can be independently enabled/disabled by software or jumper
setting

Supports drivers for DOS, Windows, OS/2, UNIX, and Netware

Packaged in 100-pin QFP

W83759A

- 4 -

PIN CONFIGURATION

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80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51

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9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30

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AEN

XIOW

XIOR

SA1

SA0

HD0

HD1

HD2

HD3

Vcc

GND

HD4

HD5

HD6

HD7

HD8

HD9

HD10

HD11

HD12

IDD6

IDD5

IDD4

IDD3

IDD2

IDD1

IDD0

GND

LCLK

GND

Vcc

LDEV

LRDY

RDYRTN

LADS

HWR

HMIO

IORDY/HDC

SYSRST

ADV

W83759A

Publication Release Date: May 1995

- 5 -

Revision A1

PIN DESCRIPTION

SYMBOL

PIN

TYPE

DESCRIPTION

VL-Bus Interface

ADV

100

I-PU

Advanced mode indicator.
When high, chip is in W83759A mode. When low, chip is in
W83759 mode.

LCLK

VL-Bus clock.

SYSRST

System reset.
When active, the power-on setting pin acts as input.

LADS

Address data strobe.
An active low input signal indicates that there is a valid address
and command on the bus.

IORDY

HDC

In W83759A mode: Enhanced IDE IORDY flow control input. Used
to throttle disk's PIO data transfers to improve PIO mode.
In W83759 mode: Host data or code status. Used to distinguish
between IO and interrupt or halt cycles.

HMIO

I-PU

Host memory or I/O status.
Used to distinguish between memory and I/O cycles.

HWR

Host write or read status.
Used to distinguish between write and read cycles.

BE2

BE0

Byte enable bits 2 and 0 from the host CPU address bus.
These active low inputs specify which bytes will be valid for host

read and write data transfers. When

BE2

is low, the host performs

a 32-bit hard disk data transfer cycle when

LDEV

is active.

LDEV

Local device.
An active low output signal which indicates that the current host
CPU command cycle is a valid W83759A I/O address (1F0h or
170h).

LRDY

Tri-O

Local ready.
An active low output that indicates when a CPU transfer has been

completed. During a cycle

LRDY

will first be enabled and driven

high. When the cycle is completed,

LRDY

will immediately be

pulled low and will remain active for one T-state. Then it will drive
high for one T-state before finally being disabled to end the
sequence.

This signal is shared with all other VL-Bus targets and driven by
W83759A only during cycles W83759A has claimed as its own.

W83759A

- 6 -

Pin Description, continued

SYMBOL

PIN

TYPE

DESCRIPTION

RDYRTN

Ready return.
An active low signal that indicates the end of the current host
CPU transfer.

Usually

RDYRTN

is tied directly to the

RDY

signal of the host

CPU.

HA[9:2]

10-3

Host address bits 9 through 2 from the host address bus.

HD[31:0]

I/O

Host data.
This is the 32-bit bidirectional data bus that connects to the host
CPU. HD[7:0] define the lowest data byte, while D[31:24] define

the most significant byte by the

[ ]

BE 2:0 signals. The HD bus is

normally in a high-impedance state and is driven by the
W83759A only during data register (1F0h or 170h) read cycles

and VGA (

VGAOEH

= 0 or

VGAOEL

= 0) read cycles.

Drive Interface

PRDYEN

IDE0CS0

I/O

-PU

When

SYSRST

is active, this is an input that latches on the

rising edge of

SYSRST

PRDYEN: A high input enables the IORDY flow control function of
the primary channel (IDE0) and a low input disables the IDE0's
flow control function.

IDE0CS0

: When

SYSRST

is inactive, this pin is an active low

output used to select the command block registers in the IDE0
drive (1F0h

1F7h).

SRDYEN

IDE0CS1

I/O

-PU

When

SYSRST

is active, this is an input that latches on the

rising edge of

SYSRST

SRDYEN: A high input enables the IORDY flow control function of
the secondary channel (IDE1) and a low disables the IDE1's flow
control function.

IDE0CS1

: When

SYSRST

is inactive, this pin is an active low

output used to select the alternate status register of the control
block registers in the IDE0 drive (3F6).

W83759A

Publication Release Date: May 1995

- 7 -

Revision A1

Pin Description, continued

SYMBOL

PIN

TYPE

DESCRIPTION

ENIDE

IDE1CS0

I/O

-PU

When

SYSRST

is active, this is an input that latches on the rising

edge of

SYSRST

ENIDE: In W83759 mode (ADV = low), this power-on-setting pin
controls if the chip enable or disable. In W83759A mode (ADV =
high), this pin controls if the IDE0 channel enable or disable. A high
input enables and a low input disables the IDE0 channel.

IDE1CS0

: When

SYSRST

is inactive, this pin is an active low

output and is used to select the command block registers in the
IDE1 drive (170h

177h).

TEST

IDE1CS1

I/O

-PU

When

SYSRST

is active, this is an input that latches on the rising

edge of

SYSRST

TEST: In W83759 mode, this power-on-setting pin controls whether
both dual channels are enabled or only the primary channel is
enabled. A high input enables IDE0 and IDE1 simultaneously and a
low input enables IDE0 only. In W83759A mode, this pin controls
whether the IDE1 channel enable or disable controls the IDE0
channel as ENIDE.

IDE1CS1

: When

SYSRST

is inactive, this pin is an active low

output used to select the alternate status register of the control
block registers in the IDE1 drive (376).

EMD1

IDEIOR

I/O

-PU

When

SYSRST

is active, this is an input that latches on the rising

edge of

SYSRST

EMD1: This power-on-setting pin combines with EMD0 to set the

initial enhanced timing mode of hard disk access cycles when the
enhanced mode is selected via the POSS3 configuration register.

IDEIOR

: Drive I/O read. An active low output that enables data to

be read from the drive. The duration and repetition rate of IDEIOR
cycles are determined by the type of IDE drive, as specified by

MD1 and MD0, in W83759 mode or by

EMD1

and EMD0 in

W83759A enhanced mode.

W83759A

- 8 -

Pin Description, continued

SYMBOL

PIN

TYPE

DESCRIPTION

EMD0

IDEIOW

I/O

-PU

When

SYSRST

is active, this is an input that latches on the rising

edge of

SYSRST

EMD0 : This power-on-setting pin combines with EMD1 to set the
initial enhanced timing mode of hard disk access cycles when the
enhanced mode is selected via the POSS3 configuration register.

ATA PIO mode

Access Time

240 nS

180 nS

120 nS

EMD1

EMD0

IDEIOW

: Drive I/O write. An active low output that enables data to

be written to the drive. The duration and repetition rate of IDEIOW
cycles are determined by the type of IDE drive, as specified by
IDEIOR .

MD1

/IDEA2,

MD0

/IDEA1

I/O

-PD

When

SYSRST

is active, these pins function as inputs and latch

on the rising edge of

SYSRST

MD1, MD0: ATA mode of IDE Drive. MD0 and MD1 are used to
select the hard disk access time.

ATA PIO mode

Access Time

600 nS

500 nS

400 nS

240 nS

EMD1

EMD0

IDEA2, IDEA1: IDE drive address bits 2 and 1. Drive address bits 2
and 1 are outputs to the IDE connector for register selection in the
drive.

W83759A

Publication Release Date: May 1995

- 9 -

Revision A1

Pin Description, continued

SYMBOL

PIN

TYPE

DESCRIPTION

SP1

/IDEA0

I/O

-PD

When

SYSRST

is active, this pin is an input that latches on the

rising edge of

SYSRST

SP1: VL-Bus speed select. A high input configures the W83759A
to run at from 33 MHz to 50 MHz; a low input configures the
W83759A to run at under 33 MHz.

IDEA0: IDE drive address bit 0. Drive address bit 0 is output to
the IDE connector for register selection in the drive.

IDD[15:0]

I/O

-PU

When

SYSRST

is active, these pins function as inputs and latch

on the rising edge of

SYSRST

As power-on setting pins, IDD[15:8] are latched to the POSS3
register and IDD[7:0] are latched to the POSS2 register.

As the drive data bus, bits 15 through 0 are the 16-bit bidirectional
data bus that connects to the IDE drive.

IDD[7:0] define the lowest data byte. The IDD bus is normally in a
pull-high state and is driven with valid data by the W83759A only

during IDE or VGA (

VGAOEH

= 0 or

VGAOEL

= 0) write cycles.

ISA-Bus Interface

SA[1:0]

47, 46

ISA address bits 1 and 0.
Used to select the hard disk I/O registers.

SD[7:0]

58-51

I/O

These signals provide data bus bits 0 through 7 for the CPU and
IDE I/O devices. SD0 is the least significant bit and SD7 is the
most significant bit.

XIOR

instructs the hard disk I/O device to drive its data onto the

SD data bus.

XIOW

instructs the hard disk I/O device to read the data on the

SD data bus.

AEN

When this line is active (high), the DMA controller has control of
the address bus. A low is the address enable.

W83759A

- 10 -

Pin Description, continued

SYMBOL

PIN

TYPE

DESCRIPTION

Special Bus Control Interface

SUSP ,

DACK ,

VGAOEH

I-PU

This pin is a multi-function input pin.

SUSP : In suspend enable mode, indicates that the W83759A

will enter the suspend state when low and resume operation when
high.

DACK : In DMA transfer enable mode, used to indicate when the
DMA transfer cycle occurs.

VGAOEH : In VGA buffer enable mode, this active low input

controls the input enable for the data transceivers that connect
the ID[15:0] pins to the HD[31:16] pins.

DMASL ,

VGAOEL

/ISDENH

I/O

-PU

When

SYSRST

is active, this pin is an input that latches on the

rising edge of

SYSRST

DMASL : This power-on setting pin combines with SUSPEN
(IDD11 power-on setting pin) to determine which mode the
W83759A is in.

DMASL

SUSPEN

Mode

VGA buffer enable

Suspend enable

DMA transfer enable

VGAOEL: In VGA buffer enable mode, this active low input

controls the input enable for the data transceivers that connect
the ID[15:0] pins to the HD[15:0] pins.

ISDENH : In DMA transfer enable mode, this output pin controls
the activity of the high byte buffer between IDD[15:8] and
SD[15:8].

Vcc

41, 65,
91

+5V power supply

GND

15, 40,
66, 88,
90

Ground reference

W83759A

Publication Release Date: May 1995

- 11 -

Revision A1

CONFIGURATION REGISTERS

Several configuration registers are implemented in the W83759A. These registers are accessible in
single-chip mode through the index/data port. The index/data port address is 1B4h/1B8h or
134h/138h, depending on whether pin IDD0 is high or low at power-on.

When the W83759A is in multi-chip mode (IDD1 is low at power-on setting), an ID code should be
written to 1B0h/130h (IDIN port). The W83759A will then enter the programming sequence if the ID
code matches the chip ID (determined by IDD2, IDD3 at power-on setting) or leave the programming
sequence if the ID code does not match. After the chip has entered the programming sequence, the
chip ID can be read by reading 1BCh/13Ch (IDOUT port).

IDD0_P is HIGH

IDD0_P is LOW

IDIN port (W/O)

1B0h*

130h**

Index port (R/W)

1B4h

134h

data port (R/W)

1B8h

138h

IDOUT port (R/O)

1BCh

13Ch

* The alias base addresses of 1B0h are XB0h and YB0h, where "X" means 0, 4, 8, C and "Y" means 1, 5, 9, D.

** The alias base addresses of 130h are X30h and Y30h, where "X" means 0, 4, 8, C and "Y" means 1, 5, 9, D.

Index map of configuration registers:

INDEX

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Default

Value

80h(R/O)
POSS1

ADV

SP1

MD1

MD0

PRDYEN

SRDYEN

IDEN1

IDEN0

8Fh

81h(R/W)
POSP1

ADV_P

SP1_P

MD1_P

MD0_P

PRDYEN_P

SRDYEN_P

IDEN1_P

IDEN0_P

8Fh

82h(R/O)
POSS2

PD0LEN

PD1LEN

SD0LEN

SD1LEN

DSL1

DSL0

CRLK#

CRSL

FFh

83h(R/W)
POSP2

PD0LE_P

PD1LEN_P

SD0LEN_P

SD1LEN_P

DSL1_P

DSL0_P

CRLK#_P

CRSL_P

FFh

84h(R/O)
POSS3

PD0EM#

PD1EM#

SD0EM#

SD1EM#

SUSPEN

STBY#

APD

SWAP#

FFh

85h(R/W)
POSP3

PD0EM#_P

PD1EM#_P

SD0EM#_P

SD1EM#_P

SUSPEN_P

STBY#_P

APD_P

SWAP#_P

FFh

86h(R/W)
ALTCTL

DMASL#_

Reserved

EMD1

EMD0

PEMD1_P

PEMD0_P

SEMD1_P

SEMD0_P

80h

87h(R/O)
REVID

DMASL#

Reserved

PDRV

SDRV

Rev 3

Rev 2

Rev 1

Rev 0

8Ah

88h(R/W)
PD0TIM0

PD0ACT3

PD0ACT2

PD0ACT1

PD0ACT0

PD0RCV3

PD0RCV2

PD0RCV1

PD0RCV0

00h

89h(R/W)
PD0TIM1

PD0AST1

PD0AST0

PD0DHT1

PD0DHT0

PD0PRE#

PD0DMA#

PD0RDY#

PD0ADV

00h

8Ah(R/W)
PD1TIM0

PD1ACT3

PD1ACT2

PD1ACT1

PD1ACT0

PD1RCV3

PD1RCV2

PD1RCV1

PD1RCV0

00h

8Bh(R/W)
PD1TIM1

PD1AST1

PD1AST0

PD1DHT1

PD1DHT0

PD1PRE#

PD1DMA#

PD1RDY#

PD1ADV

00h

8Ch(R/W)
SD0TIM0

SD0ACT3

SD0ACT2

SD0ACT1

SD0ACT0

SD0RCV3

SD0RCV2

SD0RCV1

SD0RCV0

00h

8Dh(R/W)
SD0TIM1

SD0AST1

SD0AST0

SD0DHT1

SD0DHT0

SD0PRE#

SD0DMA#

SD0RDY#

SD0ADV

00h

8Eh(R/W)
SD1TIM0

SD1ACT3

SD1ACT2

SD1ACT1

SD1ACT0

SD1RCV3

SD1RCV2

SD1RCV1

SD1RCV0

00h

8Fh(R/W)
SD1TIM1

SD1AST1

SD1AST0

SD1DHT1

SD1DHT0

SD1PRE#

SD1DMA#

SD1RDY#

SD1ADV

00h

W83759A

- 12 -

CRX80h (POSS1)

Read Only

Power-on Setting Status 1

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

ADV

SP1

MD1

MD0

PRDYEN

SRDYEN

IDEN1

IDEN0

Bit 7

ADV

Power-on setting value of ADV pin
Initial application mode

0
1

No advanced mode application

Advanced mode application

Bit 6

SP1

Power-on setting value of IDEA0 pin
Select VESA bus operating CLK

0
1

VLCLK 33 MHz

VLCLK > 33 MHz

Bit 5, 4 MD1, MD0

Power-on setting value of IDEA2, IDEA1 pin
Default HDD host transfer mode

MD1 MD0

0 0 Mode 0 (cycle time = 600 nS)

0 1 Mode 0+ (cycle time = 500 nS)

1 0 Mode 1 (cycle time = 400 nS)

1 1 Mode 2 (cycle time = 240 nS)

Bit 3

PRDYEN

Power-on setting value of IDE0CS0 pin
Initial state of primary channel IOCHRDY flow control

0 Disable IOCHRDY flow control

1 Enable IOCHRDY flow control

Bit 2

SRDYEN

Power-on setting value of IDE0CS1 pin
Initial state of secondary channel IOCHRDY flow control

0 Disable IOCHRDY flow control

1 Enable IOCHRDY flow control

Bit 1, 0

IDEN1, IDEN0

Power-on setting value of IDE1CS1, IDE1CS0 pins
Initial state of IDE ENable control

when ADV_P
= 0

IDEN1 IDEN0 Primary IDE Secondary IDE

X 0 disabled disabled

0 1 enabled disabled

1 1 enabled enabled

W83759A

Publication Release Date: May 1995

- 13 -

Revision A1

Continued

when ADV_P
= 1

IDEN1 IDEN0 Primary IDE Secondary IDE

0 0 disabled disabled
1 0 disabled enabled
0 1 enabled disabled
1 1 enabled enabled

CRX81h (POSP1)

Read / Write

Power-on Setting Programming 1

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

ADV_P

SP1_P

MD1_P

MD0_P

PRDYEN_P

SRDYEN_P

IDEN1_P

IDEN0_P

After power-on, the content of the POSP1 register is equal to that of the POSS1 register. The host
can program POSP1 to modify the power-on settings.

Bit 7

ADV_P

Programming application mode

0 No advanced mode application

1 Advanced mode application

Bit 6

SP1_P

Select VESA bus operating CLK

0 VLCLK 33 MHz

1 VLCLK > 33 MHz

Bit 5, 4

MD1_P,

MD0_P

Select default HDD host transfer mode

MD1_P MD0_P

0 0 Mode 0 (cycle time = 600 nS)

0 1 Mode 0+ (cycle time = 500 nS)

1 0 Mode 1 (cycle time = 400 nS)

1 1 Mode 2 (cycle time = 240 nS)

Bit 3

PRDYEN_P

Primary channel IOCHRDY flow control

0 Disable IOCHRDY flow control

1 Enable IOCHRDY flow control

Bit 2

SRDYEN_P

Secondary channel IOCHRDY flow control

0 Disable IOCHRDY flow control

1 Enable IOCHRDY flow control

Bit 1, 0

IDEN1_P,

IDEN0_P

IDE ENable control

W83759A

- 14 -

Continued

when ADV_P
= 0

IDEN1_P IDEN0_P Primary IDE Secondary IDE

X 0 disabled disabled

0 1 enabled disabled

1 1 enabled enabled

when ADV_P
= 1

IDEN1_P IDEN0_P Primary IDE Secondary IDE

0 0 disabled disabled

1 0 disabled enabled

0 1 enabled disabled

1 1 enabled enabled

CRX82h (POSS2)

Read Only

Power-on Setting Status 2

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

PD0LEN

PD1LEN

SD0LEN

SD1LEN

DSL1

DSL0

CRLK

CRSL

Bit 7

PD0LEN

Power-on setting value of IDD7 pin
Initial Primary Drive 0 (PD0) local device control

0 Disable local device

1 Enable local device

Bit 6

PD1LEN

Power-on setting value of IDD6 pin
Initial Primary Drive 1 (PD1) local device control

0 Disable local device

1 Enable local device

Bit 5

SD0LEN

Power-on setting value of IDD5 pin
Initial Secondary Drive 0 (SD0) local device control

0 Disable local device

1 Enable local device

Bit 4

SD1LEN

Power-on setting value of IDD4 pin
Initial Secondary Drive 1 (SD1) local device control

0 Disable local device

1 Enable local device

W83759A

Publication Release Date: May 1995

- 15 -

Revision A1

Continued

Bit 3, 2

DSL1, 0

Power-on setting value of IDD3, IDD2 pin
Initial Device ID selection (used in multi-chip mode or
CR protection scheme)

DSL1 DSL0 Device ID

0 0 60h
0 1 61h
1 0 62h
1 1 63h

Bit 1

CRLK

Power-on setting value of IDD1 pin
Initial Configuration Register locked control

0 CR is auto-locked (used in multi-chip mode)

1 CR is not auto-locked (used in single-chip mode)

Bit 0

CRSL

Power-on setting value of IDD0 pin
Initial Configuration Register selection

0 CR port address: 130h, 134h, 138h, 13Ch

1 CR portaddress: 1B0h, 1B4h, 1B8h, 1BCh

CRX83h (POSP2)

Read / Write

Power-on Setting Programming 2

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

PD0LEN_
P

PD1LEN_
P

SD0LEN_P

SD1LEN_P

DSL1_P

DSL0_P

CRLK

CRSL_P

After power-on, the content of the POSP2 register is equal to that of the POSS2 register. The host
can program POSP2 to modify the power-on settings.

Bit 7

PD0LEN_P

Primary Drive 0 (PD0) local device control

0 Disable local device

1 Enable local device

Bit 6

PD1LEN_P

Primary Drive 1 (PD1) local device control

0 Disable local device

1 Enable local device

Bit 5

SD0LEN_P

Secondary Drive 0 (SD0) local device control

0 Disable local device

1 Enable local device

W83759A

- 16 -

Continued

Bit 4

SD1LEN_P

Secondary Drive 1(SD1) local device control

0 Disable local device

1 Enable local device

Bit 3, 2

DSL1, 0_P

Device ID selection (used in multi-chip mode or CR
protection scheme)

DSL1_P DSL0_P Device ID

0 0 60h
0 1 61h
1 0 62h
1 1 63h

Bit 1

CRLK

Configuration Register locked control

0 CR is auto-locked (multi-chip mode)

1 CR is not auto-locked (single-chip mode)

Bit 0

CRSL_P

Configuration Register selection

0 CR port address: 130h, 134h, 138h, 13Ch

1 CR port address: 1B0h, 1B4h, 1B8h, 1BCh

CRX84h (POSS3)

Read Only

Power-on Setting Status 3

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

PD0EM

PD1EM

SD0EM

SD1EM

SUSPEN

STBY#

APD

SWAP

Bit 7

PD0EM

Power-on setting value of IDD15 pin
Initial setting of PD0 enhanced timing enable

0 Enhanced timing

1 Programmable timing

Bit 6

PD1EM

Power-on setting value of IDD14 pin
Initial setting of PD1 enhanced timing enable

0 Enhanced timing

1 Programmable timing

Bit 5

SD0EM

Power-on setting value of IDD13 pin
Initial setting of SD0 enhanced timing enable

0 Enhanced timing

1 Programmable timing

W83759A

Publication Release Date: May 1995

- 17 -

Revision A1

Continued

Bit 4

SD1EM

Power-on setting value of IDD12 pin
Initial setting of SD1 enhanced timing enable

0 Enhanced timing

1 Programmable timing

Bit 3

SUSPEN

Power-on setting value of IDD11 pin
Initial setting of SUSPend function

0 Support DMA mode if

DMASL

_P = 0 and

ADV_P = 1

1 Support suspend function if

DMASL

_P = 0

and ADV_P = 1.

Bit 2

STBY

Power-on setting value of IDD10 pin
Initial setting of STandBy state

0 W83759A is in standby state

1 W83759A is in normal state

Bit 1

APD

Power-on setting value of IDD9 pin
Initial setting of auto Power-down

0 Auto power-down off

1 Auto power-down on

Bit 0

SWAP

Power-on setting value of IDD8 pin
Initial primary, secondary channel connection select

0 Primary channel connect to IDE1
Secondary channel connect to IDE0

1 Primary channel connect to IDE0
Secondary channel connect to IDE1

CRX85h (POSP3)

Read/ Write

Power-on Setting Programming 3

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

PD0EM

PD1EM

SD0EM

SD1EM

SUSPEN_P

STBY

APD_P

SWAP

Bit 7

PD0EM

Power-on setting programming of IDD15 pin
Programmable setting of PD0 enhanced timing enable

0 Enhanced timing

1 Programmable timing

W83759A

- 18 -

Continued

Bit 6

PD1EM

Power-on setting programming of IDD14 pin
Programmable setting of PD1 enhanced timing enable

0 Enhanced timing

1 Programmable timing

Bit 5

SD0EM

Power-on setting programming of IDD13 pin
Programmable setting of SD0 enhanced timing enable

0 Enhanced timing

1 Programmable timing

Bit 4

SD1EM

Power-on setting programming of IDD12 pin
Programmable setting of SD1 enhanced timing enable

0 Enhanced timing

1 Programmable timing

Bit 3

SUSPEN_P

Power-on setting value of IDD11 pin
Programmable setting of SUSPend function

0 Support suspend function if

DMASL

_P = 0

and ADV_P = 1

1 Support DMA transfer if

DMASL

_P = 0

and ADV_P = 1

Bit 2

STBY

Power-on setting value of IDD10 pin
Programmable setting of STandBy state

0 W83759A is in standby state

1 W83759A is in normal state

Bit 1

APD_P

Power-on setting value of IDD9 pin
Initial setting of auto power-down

0 Auto power-down off

1 Auto power-down on

Bit 0

SWAP

Power-on setting programming of IDD8 pin
Programmable primary, secondary channel connection
select

0 Primary channel connect to IDE1
Secondary channel connect to IDE0

1 Primary channel connect to IDE0
Secondary channel connect to IDE1

W83759A

Publication Release Date: May 1995

- 19 -

Revision A1

Continued

CRX86h (ALTCTL)

Read / Write

Alternative Control Register

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

DMASL

Reserved

EMD1

EMD0

PEMD1_P

PEMD0_P

SEMD1_P

SEMD0_P

Bit 7

DMASL

Power-on setting value of

VGAOEL

pin.

After power-on, this bit can be programmed to modify
the DMA disable/enable power-on setting.

0 DMA mode enabled if SUSPEN_P = 0 and
ADV_P = 1

1 DMA mode disabled

Bit 6

Reserved

0 (default)

Bit5

EMD1, 0

(Read Only)

Inverse of power-on setting value of

IDEIOR

IDEIOW

pin
Initial setting of enhanced timing of IDE0 and IDE1

EMD1 EMD0 ATA PIO Mode

Cycle time (nS)

0 0 2 240

0 1 3 80

1 0 3 80

1 1 4 120

Bit3

PEMD1, 0_P

Initial setting of primary drive enhanced timing
After power-on, these bits can be programmed to modify
the primary drive enhanced timing.

PEMD1_P PEMD0_P ATA PIO mode Cycle time (nS)

0 0 2 240

0 1 3 180

1 0 3 180

1 `1 4 120

Bit1

SEMD1, 0_P

Initial setting of secondary drive enhanced timing
After power-on, these bits can be programmed to modify
the secondary drive enhanced timing

SEMD1_P SEMD0_P ATA PIO Mode Cycle time (nS)

0 0 2 240

0 1 3 180

1 0 3 180

1 1 4 120

W83759A

- 20 -

CRX87h (REVID)

Read Only

Revision ID Number

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

DMASL

Reserved

PDRV

SDRV

Rev 3

Rev 2

Rev 1

Rev 0

Bit 7

DMASL

Power-on setting value of

VGAOEL

pin.

Initial DMA enable/disable setting

0 DMA mode enabled if SUSPEN_P = 0 and
ADV_P = 1

1 DMA mode disabled

Bit 6

Reserved

(Read/Write)

0 (default)

Bit 5

PDRV

Primary channel current drive select

0 Master drive (default)

1 Slave drive

Bit 4

SDRV

Secondary channel current drive select

0 Master drive (default)

1 Slave drive

Bit 3-Bit 0 Rev 3

Rev 0 1010b (default in A version)

W83759A

Publication Release Date: May 1995

- 21 -

Revision A1

CRX88h (PD0TIM0)

Read/Write

Primary Drive0 Timing Control 0

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

PD0ACT3

PD0ACT2

PD0ACT1

PD0ACT0

PD0RCV3

PD0RCV2

PD0RCV1

PD0RCV0

Bit 7

Bit 4

PD0ACT3

PD0 Data Register Port (1F0h) Read/Write Active Time
Read/Write active time (clocks)
0000 17/16
0001 3/2
0010 3/2
0011 4/3
0100 5/4
0101 6/5
0110 7/6
0111 8/7
1000 9/8
1001 10/9
1010 11/10
1011 12/11
1100 13/12
1101 14/13
1110 15/14
1111 16/15

Bit 3

Bit 0

PD0RCV3

PD0 Data Register Port (1F0h) Read/Write Recovery
Time

Write/Read recovery time (clocks)

0000 16/15

0001 2/1
0010 2/1
0011 3/2
0100 4/3
0101 5/4
0110 6/5
0111 7/6
1000 8/7
1001 9/8
1010 10/9
1011 11/10
1100 12/11
1101 13/12
1110 14/13
1111 15/14

W83759A

- 22 -

CRX89h (PD0TIM1)

Read/Write

Primary Drive0 Timing Control 1

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

PD0AST1

PD0AST0

PD0DHT1

PD0DHT0

PD0PRE

PD0DMA

PD0RDY

PD0ADV

Bit 7

Bit 6

PD0AST1

PD0 Data Register Port (1F0h) Address Setup Time

Read/Write extra address setup time (clocks)

00 0
01 2
10 2
11 3

Bit 5

Bit 4

PD0DHT1

PD0 Data Register Port (1F0h) Data Hold Time

Read/Write extra data hold time (clocks)

00 0
01 2
10 2
11 3

Bit 3

PD0PRE

Prefetch/Post write control

0 Prefetch/Post write enabled

1 Prefetch/Post write disabled

Bit 2

PD0DMA

PD0 DMA mode control

0 DMA mode enabled

1 DMA mode disabled

Bit 1

PD0RDY

PD0 Data Register Port (1F0h) IOCHRDY Control

0 IOCHRDY enabled

1 IOCHRDY disabled

Bit 0

PD0ADV

PD0 Data Register Port (1F0h) Advanced Timing
Enable

0 Normal timing (depends on SP1, MD1, MD0
setting)

1 Advanced timing (depends on PD0TIM1

setting)

W83759A

Publication Release Date: May 1995

- 23 -

Revision A1

CRX8Ah (PD1TIM0)

Read/Write

Primary Drive1 Timing Control 0

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

PD1ACT3

PD1ACT2

PD1ACT1

PD1ACT0

PD1RCV3

PD1RCV2

PD1RCV1

PD1RCV0

Bit 7

Bit 4

PD1ACT3

PD1 Data Register Port (1F0h) Read/Write Active Time

Definition of these bits same as PD0ACT3

Bit 3

Bit 0

PD1RCV3

PD1 Data Register Port (1F0h) Read/Write Recovery Time

Definition of these bits same as PD0RCV3

CRX8Bh (PD1TIM1)

Read/Write

Primary Drive 1 Timing Control 1

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

PD1AST1

PD1AST0

PD1DHT1

PD1DHT0

PD1PRE

PD1DMA

PD1RDY

PD1ADV

Bit 7-Bit 6

PD1AST1

PD1 Data Register Port (1F0h) Address Setup Time

Definition of these bits same as PD0AST1-0

Bit 5-Bit 4

PD1DHT1

PD1 Data Register Port (1F0h) Data Hold Time

Definition of these bits same as PD0DHT1

Bit 3

PD1PRE

PD1 Prefetch/Post write control

0 Prefetch/Post write enabled

1 Prefetch/Post write disabled

Bit 2

PD1DMA

PD1 DMA mode control

0 DMA mode enabled

1 DMA mode disabled

Bit 1

PD1RDY

PD1 Data Register Port (1F0h) IOCHRDY Control

0 OCHRDY enabled

1 IOCHRDY disabled

Bit 0

PD1ADV

PD1 Data Register Port (1F0h) Advanced Timing Enable

0 Normal timing (depends on SP1, MD1, MD0
setting)

1 Advanced timing (depends on PD1TIM1

0 setting)

W83759A

- 24 -

CRX8Ch (SD0TIM0)

Read/Write

Secondary Drive 0 Timing Control 0

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

SD0ACT3

SD0ACT2

SD0ACT1

SD0ACT0

SD0RCV3

SD0RCV2

SD0RCV1

SD0RCV0

Bit 7-Bit 4

SD0ACT3

SD0 Data Register Port (170h) Read/Write Active Time

Definition of these bits same as PD0ACT3

Bit 3-Bit 0

SD0RCV3

SD0 Data Register Port (170h) Read/Write Recovery Time

Definition of these bits same as PD0RCV3

CRX8Dh (SD0TIM1)

Read/Write

Secondary Drive 0 Timing Control 1

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

SD0AST1

SD0AST0

SD0DHT1

SD0DHT0

SD0PRE

SD0DMA

SD0RDY

SD0ADV

Bit 7-Bit 6

SD0AST1

SD0 Data Register Port (170h) Address Setup Time

Definition of these bits same as PD0AST1

Bit 5-Bit 4

SD0DHT1

SD0 Data Register Port (170h) Data Hold Time

Definition of these bits same as PD0RDHT1

Bit 3

SD0PRE

SD0 Prefetch/Post write control

0 Prefetch/Post write enabled

1 Prefetch/Post write disabled

Bit 2

SD0DMA

SD0 DMA mode control

0 DMA mode enabled

1 DMA mode disabled

Bit 1

SD0RDY

SD0 Data Register Port (170h) IOCHRDY Control

0 IOCHRDY enabled

1 IOCHRDY disabled

Bit 0

SD0ADV

SD0 Data Register Port (170h) Advanced Timing Enable

0 Normal timing (depends on SP1, MD1, MD0
setting)

1 Advanced timing (depends on SD0TIM1

0 setting)

W83759A

Publication Release Date: May 1995

- 25 -

Revision A1

CRX8Eh (SD1TIM0)

Read/Write

Secondary Drive 1 Timing Control 0

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

SD1ACT3

SD1ACT2

SD1ACT1

SD1ACT0

SD1RCV3

SD1RCV2

SD1RCV1

SD1RCV0

Bit 7

Bit 4

SD1ACT3

SD1 Data Register Port (170h) Read/Write Active Time

Definition of these bits same as PD0RCV3-0

Bit 3

Bit 0

SD1RCV3

SD1 Data Register Port (170h) Read/Write Recovery Time

Definition of these bits same as PD0RCV3-0

CRX8Fh (SD1TIM1)

Read/Write

Secondary Drive 1 Timing Control 1

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

SD1AST1

SD1AST0

SD1DHT1

SD1DHT0

SD1PRE

SD1DMA

SD1RDY

SD1ADV

Bit 7

Bit 6

SD1AST1

SD1 Data Register Port (170h) Address Setup Time

Definition of these bits same as PD0RCV3

Bit 5

Bit 4

SD1DHT1

SD1 Data Register Port (170h) Data Hold Time

Definition of these bits same as PD0RCV3

Bit 3

SD1PRE

SD1 Prefetch/Post write control

0 Prefetch/Post write enabled

1 Prefetch/Post write disabled

Bit 2

SD1DMA

SD1 DMA mode control

0 DMA mode enabled

1 DMA mode disabled

Bit 1

SD1RDY

SD1 Data Register Port (170h) IOCHRDY Control

0 IOCHRDY enabled

1 OCHRDY disabled

Bit 0

SD1ADV

SD1 Data Register Port (170h) Advanced Timing Enable

0 Normal timing (depends on SP1, MD1, MD0
setting)

1 Advanced timing (depends on SD1TIM1

0 setting)

W83759A

- 26 -

SYSTEM BLOCK DIAGRAM

Data Flow

VL-Bus

Chip Set

W83C491/492

(160-pin x2)

Super IO

W83787F

(100-pin)

CPU

VL_BUS

ISA Bus

IO Device

IDE ATA Bus x 2

IDD

VL_IDE

W83759AF
(100-pin)

Address Decode

IDE1CS

VL_IDE

W83759AF

(100-pin)

VL-Bus

Chip Set

W83C491/492

(160-pin x2)

W83757

Super IO

(100-pin)

CPU

VL_BUS

ISA Bus

IO Device

IDE ATA Bus x 2

LDEV

W83787F

IDEA[2:0]

IDE0CS

W83759A

Publication Release Date: May 1995

- 27 -

Revision A1

Control Signal

VL_IDE

W83759AF

(100-pin)

LADS,...

LDEV, LRDY

RDYRTN

XIOR

XIOW

VL-Bus

Chip Set

W83C491/492

(160-pin x2)

Super IO

W83787F

(100-pin)

CPU

VL_BUS

ISA Bus

IO Device

IDE ATA Bus x 2

LADS, ... *

LDEV, LRDY

RDYRTN

* LADS,... = LADS, HMIO, HWR, HDC, BE2, BE0

IDEIOR, IDEIOW

IORDY

XIOR

XIOW

XIOR

XIOW

FUNCTION BLOCK DIAGRAM

Command
Enable

1f0
/170

32
Bit

16
Bit

Data Flow
Control

DATA

BUFFER

ID[15:0]

SD[7:0]

HD[31:0]

HA[9:2]

BE2, BE0

SA1, SA0, AEN

HMIO, HWR, HDC

VGAOEH, VGAOEL

XIOR, XIOW

IDEA[2:0]
IDE0CS1
IDE0CS0

IDE1CS1
IDE1CS0
IDEIOR
IDEIOW

DECODE

LOGIC

PREFETCH

CONTROL

IORDY

CONTROL

LOGIC

LCLK

SYSRST

LADS

RDYRTN

SP1, MD1, MD0

LRDY

LDEV

TIMING

REGISTERS

MUX

W83759A

- 28 -

FUNCTIONAL DESCRIPTION

Reset Initialization

The CPU clock rate, hard disk access time, hard disk controller enable, and hard disk I/O select are

latched at the rising edge of

SYSRST

. These values are used to control the host and drive access

signal timing. Additionally, the W83759A is initialized to a known state by an active low on SYSRST .

Any operation in progress is immediately terminated by

SYSRST

Host in Terface

The W83759A operates as a slave device, responding only to cycles within the host I/O address
space. The IDE drive data port at address 1F0h (170h) is a 16-bit port that requests a double-word
data transfer at address 1F0h (170h). All byte swapping, conversion, word, and double-word assembly
are done at the host interface. Table 1 summarizes the W83759A host interface cycle decoding.

Table 1. W83759A Cycle Definition

HMIO

HDC

HWR

ADDRESS SPACE

HOST BUS

CYCLE

W83759A CYCLE

1F0h

1F7h and 3F6h

I/O Read

IDE0 Read Cycle

1F0h

1F7h and 3F6h

I/O Write

IDE0 Write Cycle

170h

177h and 376h

I/O Read

IDE1 Read Cycle

170h

177h and 376h

I/O Write

IDE1 Write Cycle

a. CPU WRITE CYCLES

Table 2. W83759A Write Data Operation

BYTE ENABLE

W83759A INPUT DATA

I/O ADDRESS

BE3

BE2

BE1

BE0

HD[31:16]

HD[15:0]

SD[7:0]

Valid

1F1

1F7 (171

177)

Valid

1F0 (170)

Valid

8-bit IDE Write Data Path:

CPU

Valid HD Byte

SD[7:0]

W83759A

ID[7:0]

16/32-bit IDE Write Data Path:

CPU

Valid HD Word

W83759A

ID[15:0]

W83759A

Publication Release Date: May 1995

- 29 -

Revision A1

b. CPU READ CYCLES

Table 3. W83759A Read Data Operation

BYTE ENABLE

W83759A OUTPUT DATA

I/O ADDRESS

BE3

BE2

BE1

BE0

HD[31:16]

HD[15:0]

SD[7:0]

Valid

1F1

1F7 (171

177)

Valid

1F0 (170)

Valid

8-bit IDE Read Data Path:

CPU

Valid HD Byte

Chip Set

SD[7:0]

W83759A

ID[7:0]

16/32-bit IDE Read Data Path:

CPU

Valid HD Word

W83759A

ID[15:0]

Drive Interface

The W83759A is designed to work with standard IDE disk drives. For the IDE interface, the W83759A
provides a 16-bit data path ID[15;0], address lines IDEA[2:0], decoded device select signals

IDE0CS0

(IDE1CS0) and

IDE0CS1

(

IDE1CS1

), and decoded command sigals

IDEIOR

and

IDEIOW

During normal operation, the drive address outputs IDEA[2:0] are used to select a register in an IDE

drive. These addresses are generated from

BE2

BE0

, HA2 and SA1, SA0. Table 4 summarizes the

type enable decoding for normal operation.

Table 4. IDEA[2:0] Generation

HA2

BE2

BE0

SA1

SA0

IDEA[2:0]

I/O ADDRESS

000

1F0 (170) 16-bit

000

1F0 (170) 32-bit

001

1F1 (171)

010

1F2 (172)

011

1F3 (173)

100

1F4 (174)

101

1F5 (175)

110

1F6 (176)

111

1F7 (177)

Two drive chip select signals,

IDE0CS0

(

IDE1CS0

) and

IDE0CS1

(

IDE1CS1

), are generated from

the local bus addresses and ISA bus address. The 16-bit data register may be read or written at I/O
address 1F0h(170h). The 8-bit IDE command and status registers are at I/O addresses 1F1h through

1F7h (and 171h through 177h). The

IDEIOR

IDEIOW

commands are generated for all address

W83759A

- 30 -

regions in which IDE0CS0 (

IDE1CS0

) and IDE0CS1 (

IDE1CS1

) are active. Table 5 summarizes the

decoding of these sgnals.

Table 5. Drive Select Signal Operation

SELECT SIGNAL

ADDRESS RANGE

IDE0CS0

I/O Address 1F0h through 1F7h

IDE0CS1

I/O Address 3F6h

IDE1CS0

I/O Address 170h through 177h

IDE1CS1

I/O Address 376h

IDE Timing Control

Pin SP1 is used to set the VL-Bus speed. The IDE drive interface will maintain the same ATA PIO
timing parameters for IDE drive 16-bit IO access cycles (1F0/170) regardless of whether the VL-Bus
operates at 33 or 50 MHz.

In W83759 mode, IDE drive timing is controlled by pins MD1 and MD0, which are used to select the
IDE drive PIO mode 0-2. The drive timing depends on the ATA specification for the IDE drive PIO
mode selected.

In W83759A mode, IDE drive timing is controlled by pins EMD1 and EMD0, which are used to select
the IDE drive PIO mode 2-4. The drive timing depends on the ATA specification for the IDE drive PIO
mode selected.

Table 6 summarizes the ATA Rev. 4.0 and ATA-2 PIO timing parameters.

Table 7 and Table 8 summarize the W83759A PIO read/write command pulse and cycle timing when
a 16-bit IDE IO access is performed. Because 8-bit IDE IO accesses are always passed to the ISA
bus, the W83759A transceives data through the ISA data bus and induces IDE read/write commands

from ISA

XIOR

XIOW

. Thus the 8-bit command timing will always meet ATA timing specifications.

Table 6. ATA Rev. 4.0 and ATA-2 PIO Minimum Timing Parameters

Unit: nS

ATA PIO

MODE 4

MODE 3

MODE 2

MODE 1

MODE 0

8/16-bit IO

access

Active

Pulse

Cycle

Time

Active

Pulse

Cycle

Time

Active

Pulse

Cycle

Time

Active

Pulse

Cycle

Time

Active

Pulse

Cycle

Time

16-bit

120

180

100

240

125

383

165

600

8-bit

120

180

290

383

290

600

Table 7. PIO Command Pulse and Cycle Timing (W83759 mode)

Unit: LCLK

SP1

MD1

MD0

IDE WRITE

ACTIVE PULSE

IDE READ

ACTIVE PULSE

READ/WRITE

CYCLE TIME

IDE MODE

SELECT

6 (180)

7 (210)

22 (660)

Mode 0

6 (180)

7 (210)

19 (570)

Mode 0+

W83759A

Publication Release Date: May 1995

- 31 -

Revision A1

Table 7. PIO Command Pulse and Cycle Timing, continued

SP1

MD1

MD0

IDE WRITE

ACTIVE PULSE

IDE READ

ACTIVE PULSE

READ/WRITE

CYCLE TIME

IDE MODE

SELECT

8 (240)

9 (270)

13 (390)

Mode 1

4 (120)

5 (150)

9 (270)

Mode 2

9 (180)

10 (200)

31 (620)

Mode 0

9 (180)

10 (200)

27 (540)

Mode 0+

7 (140)

8 (160)

19 (380)

Mode 1

6 (120)

7 (140)

13 (260)

Mode 2

Note: It is recommended that SP be set to 0 when LCLK is 33 MHz. The initial default value is SP1 = 0. The timing value (nS) is
based on LCLK = 20 nS when SP1 = 1 and LCLK = 30 nS when SP1 = 0.

Table 8. PIO Command Pulse and Cycle Timing (W83759A mode)

Unit: LCLK

SP1

EMD1

EMD0

IDE WRITE

ACTIVE PULSE

IDE READ

ACTIVE PULSE

READ/WRITE

CYCLE TIME

IDE MODE

SELECT

4 (120)

5 (150)

8 (240)

Mode 2

3 (90)

4 (120)

6 (180)

Mode 3

3 (90)

4 (120)

6 (180)

Mode 3

2 (60)

3 (90)

4 (120)

Mode 4

4 (80)

5 (100)

11 (220)

Mode 2

4 (80)

5 (100)

9 (180)

Mode 3

3 (60)

4 (80)

7 (140)

Mode 4-

2 (40)

3 (60)

5 (100)

Mode 4+

Note: It is recommended that SP be set to 0 when LCLK is 33 MHz. The initial default value is SP1 = 0. The timing value (nS) is
based on LCLK = 20 nS when SP1 = 1 and LCLK = 30 nS when SP1 = 0.

Prefetch Control

The W83759A IDE command prefetch feature provides concurrent operations by pipelined read-
ahead of the next data word(s) from the drive while the host is transferring previously requested disk
data into system memory. This reduces the amount of time that the host must pause and wait for data
to be accessed. While the host is writing data to memory, the W83759A reads data from the disk
drive. As soon as the host reads the W83759A data, new data are requested by the W83759A from
the disk drive. This prefetch feature is active only for disk data at the 1F0h and 170h IO addresses
and does not oprate on other disk register data.

Power-saving Control

The W83759A provides three power-saving modes. In the initial-level power-saving mode, all of the
drive's control, address, data, and other signals enter a logic 1 standby state when no IDE disk cycle
is active. This reduces unnecessary power use and decreases the amount of EMI radiation generated
by driving the long IDE cable continuously.

W83759A

- 32 -

After power on, the W83759A automatically enters the "Auto-Power-Down" (APD) mode. In this mode
the only active logic inside the W83759A is the host address decoder and bus tracking state machine.
Power is saved by not switching logic inside the W83759A that is not being utilized. Whenever an IDE
transfer cycle is detected, the W83759A leaves APD mode and the entire chip becomes active. The
W83759A enters APD mode again after the completion of an IDE transfer cycle.

To support deep-green systems, the W83759A also provides advanced power saving modes, standby

mode, and suspend mode. When standby mode is enabled (

STBY

bit goes low), all of the logic

inside the W83759A is stopped until standby mode is disabled (

STBY

bit goes high). When suspend

mode is enabled (SUSPEN bit goes high and

DMASL

is low on

SYSRST

rising), the W83759A will

enter suspend state when

SUSP

goes low and return to normal state when

SUSP

goes high.

ABSOLUTE MAXIMUM RATINGS

= 5 V

5%, V

= 0V )

PARAMETER

RATING

UNIT

Power Supply Voltage

-0.3 to 7.0

Input Voltage

-0.3 to V

+0.3

Operating Temperature (Ta)

0 to + 70

Storage Temperature

-55 to + 150

Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability of the
device.

DC CHARACTERISTICS

(TA = 0

C to +70

C, V

= 5V

5%, V

= 0V)

PARAMETER

SYM.

CONDITIONS

MIN.

MAX.

UNIT

Input Low Voltage

-0.3

0.8

Input High Voltage

2.0

+ 0.3

Input High Leakage
with Pull-Down

LIHD

= V

+500

Input Low Leakage
with Pull-Up

LILU

= 0V

-500

Input High Leakage

LIH

= V

+10

Input Low Leakage

LIL

= 0V

-10

Output Low Voltage

= 8 mA (

LDEV

, SD, IDE pins)

= 6 mA (other pins)

0.4

Output High Voltage

= -8 mA (

LDEV

, SD, IDE pins)

= -6 mA (other pins)

2.4

Input Capacitance

Output Capacitance

OUT

W83759A

Publication Release Date: May 1995

- 33 -

Revision A1

DC Characteristics, continued

PARAMETER

SYM.

CONDITIONS

MIN.

MAX.

UNIT

Operating Current

LCLK

= 50 MHz

Standby Current

STBY

All input and I/O pins pulled high,
LCLK = V

800

AC CHARACTERISTICS

All AC timing is measured from the 0.8V and 2.0V on the source signal to the 0.8V and 2.0V level on
the signal under test.

AC specifications are given for the following testing conditions:

= 5V

5%, Temp. = 0

C to 70

VL-Bus shared signal loading = 100 pF
VL-Bus non-shared signal loading = 33 pF
ISA Bus signal loading = 240 pF

IDE device interface loading = 30 pF

SYMBOL

PARAMETER

MIN.

MAX.

UNIT

FIG.

LCLK Period

Fig. 1

LCLK High Time

Fig. 1

LCLK Low Time

Fig. 1

SYSRST Pulse Width

LCLK

Fig. 1

POS Pin to SYSRST Setup Time

200

Fig. 1

POS Pin Hold Time from SYSRST

Fig. 1

LADS to LCLK Setup Time

Fig. 2

LADS Hold Time from LCLK

Fig. 2

LDEV Active Delay from Address

Fig. 2

t10

VESA IO Read Host Data Drive Delay

Fig. 2, 4

t11

HMIO, HDC , HWR to LCLK Setup Time when

LDEV asserted at T2

Fig. 2, 3

t12

HMIO, HDC , HWR to LCLK Setup Time when

LDEV asserted at T2

Fig. 2, 3

t13

LRDY Active Delay from LCLK

Fig. 2, 3

t14

LRDY Inactive Delay from LCLK

Fig. 2, 3

t15

RDYRTN to LCLK Setup Time

Fig. 2, 3

t16

RDYRTN Hold Time from LCLK

Fig. 2, 3

t17

VESA IO Write Host Data Valid Delay

Fig. 3

t18

VESA IO Write Host Data Hold Time

Fig. 3, 5

W83759A

- 34 -

AC Characteristics, continued

SYMBOL

PARAMETER

MIN.

MAX.

UNIT

FIG.

t19

IDEA[2:0] Valid Delay from Address Valid

Fig. 4, 5

t20

IDEA[2:0] Invalid Delay from Address Change

Fig. 4, 5

t21

IDE0CS0

IDE1CS0

Valid Delay from

Address valid

Fig. 4, 5

t22

IDE0CS0

IDE1CS0

Invalid Delay from

Address Change

Fig. 4, 5

t23

IDEIOR, IDEIOW Active Delay from LCLK

Fig. 4, 5

t24

IDEIOR

IDEIOW

Inactive Delay from LCLK

Fig. 4, 5

t25

IDE Read IDD Data Hold Time from LCLK

Fig. 4

t26

IDE Read IDD to HD Delay

Fig. 4

t27

IDE Read HD Float Delay from LCLK

Fig. 4

t28

IDE Write IDD Drive Delay

Fig. 5

t29

IDE Write IDD Float Delay

Fig. 5

t30

IDEA[2:0] Valid Delay from A2 SA[1:0] Valid

Fig. 6, 7

t31

IDEA[2:0] Invalid Delay from A2 SA[1:0]
Change

Fig. 6, 7

t32

IDE CS

1, IDE CS

1 Valid Delay from Address

Valid

Fig. 6, 7

t33

IDE0CS1

IDE1CS1

Invalid Delay from

Address Change

Fig. 6, 7

t34

ISA IDE Read IDD to SD Delay

Fig. 6

t35

ISA IDE Read IDD Data Hold Time from

IDEIOR

Fig. 6

t36

ISA IDE Write SD to IDD Delay

Fig. 7

t37

ISA IDE Wrtie SD Data Hold Time from

XIOW

Fig. 7

t38

VGA Read IDD to HD Delay

Fig. 8

t39

VGA Read HD Float Delay from

VGAOEL

Fig. 8

t40

VGA Write HD to IDD Delay

Fig. 9

t41

VGA Write HD Float Delay from

VGAOEH

Fig. 9

t42

ISA IDD Read

IDEIOR

Active Delay from

XIOR

Fig. 6

t43

ISA IDD Read

IDEIOR

Inactive Delay from

XIOR

Fig. 6

t44

ISA IDE Write

IDEIOW

Active Delay from

XIOW

Fig. 7

t45

ISA IDE Write

IDEIOW

Inactive Delay from

XIOW

Fig. 7

W83759A

Publication Release Date: May 1995

- 35 -

Revision A1

TIMING WAVEFORMS

All AC timing is measured from the 0.8V and 2.0V on the source signal to the 0.8V and 2.0V level on
the signal under test.

LCLK, SYSRST , Timing

LCLK

ENIDE, TEST

SP1, MD1, MD0

SYSRST

PRDYEN, SRDYEN

IDD[15:0], EMD1, EMD0

DMASL

Figure 1

Note: ENIDE, TEST, SP1, MD1, MD0, PRDYEN, SRDYEN, IDD[15:0], EMD1, EMD0, DMASL are POS (Power-On Setting)

pins. When

SYSRST

is low they are tri-stated as inputs.

VESA IO Read Timing

t11

t12

Local IDE Time

t15

t16

t13

t14

t10

LCLK

HD[31:0]

LADS

HA[9:2],

BE2, BE0

LDEV

RDYRTN

LRDY

HMIO = 0

HDC = 1

HWR = 0

Figure 2

Note: Local IDE cycle time is determined by SP1, MD1, and MD0 or by SP1, EMD1 and EMD0 at power-on. After power-on the

driver can program the timing register to tune the timing.

W83759A

Publication Release Date: May 1995

- 37 -

Revision A1

IDE IO Read Timing

Local IDE Cycle Time

LCLK

HD[31:0]

LADS

HA[9:2],

BE2, BE0

LDEV

RDYRTN

LRDY

t10

t26

t27

t24

t25

t23

Recovery
Time

Pulse Width

t19

t21

t20

t22

IEDA[2:0]

IDE0CS0

IDE1CS0

IDD[15:0]

IDEIOR

Figure 4

Note: At power-on the recovery time and pulse width are determined by SP1, MD1, and MD0, or by SP1, EMD1 and EMD0 as

indicated in Table 7. and Table 8. After power-on the driver can program the timing register to tune the timing.

Example: When SP = 1 and MD1 = MD0 = 0, the IDEIOR pulse width is 10 LCLK and recovery time is 21 LCLK (cycle time

is 31 LCLK).

W83759A

- 38 -

IDE IO Write Timing

Local IDE Cycle Time

LCLK

IDD[15:0]

LADS

HA[9:2],

BE2, BE0

LDEV

RDYRTN

LRDY

t28

t29

t24

t18

t23

Recovery
Time

Pulse Width

t19

t21

t20

t22

IEDA[2:0]

IDE0CS0

IDE1CS0

HD[31:0]

IDEIOW

Figure 5

Note: At power-on the recovery time and pulse width are determined by SP1, MD1, and MD0 or by SP1, EMD1, and EMD0 as

indicated in Table 7 and Table 8. After power-on the driver can program the timing register to tune the timing.

Example: When SP = 1 and MD1 = MD0 = 0, the

IDEIOW

pulse width is 9 LCLK and recovery time is 22 LCLK (cycle time is

31 LCLK).

W83759A

Publication Release Date: May 1995

- 41 -

Revision A1

PACKAGE DIMENSION

100-pin QFP

100

E H

Seating Plane

See Detail F

Detail F

1. Dimension D & E do not include interlead

flash.
2. Dimension b does not include dambar

protrusion/intrusion.
3. Controlling dimension: Millimeters
4. General appearance spec. should be based on final

visual inspection spec.

0.10

0.004

2.40

1.40

19.10

1.20

18.80

1.00

18.49

0.094

0.055

0.988

0.752

0.047

0.976

0.740

0.039

0.964

0.728

0.65

20.13

14.13

0.25

0.40

2.97

3.30

20.00

14.00

2.85

19.87

13.87

0.10

0.25

2.73

0.10

0.792

0.556

0.010

0.016

0.117

0.130

0.787

0.551

0.112

0.026

0.782

0.546

0.004

0.010

0.107

0.004

Notes:

Symbol

Min. Nom

Max.

Nom

Min.

Dimension in inches

Dimension in mm

b
c
D

e
H

y
0

A
A

0.012

0.006

0.15

0.30

24.49

24.80

25.10

0.020

0.087

0.032

0.103

0.50

0.80

2.21

2.62

Headquarters

No. 4, Creation Rd. III,
Science-Based Industrial Park,
Hsinchu, Taiwan
TEL: 886-3-5770066
FAX: 886-3-5792646
http://www.winbond.com.tw/
Voice & Fax-on-demand: 886-2-7197006

Taipei Office

11F, No. 115, Sec. 3, Min-Sheng East Rd.,
Taipei, Taiwan
TEL: 886-2-7190505
FAX: 886-2-7197502

Winbond Electronics (H.K.) Ltd.

Rm. 803, World Trade Square, Tower II,
123 Hoi Bun Rd., Kwun Tong,
Kowloon, Hong Kong
TEL: 852-27516023
FAX: 852-27552064

Winbond Electronics North America Corp.
Winbond Memory Lab.
Winbond Microelectronics Corp.
Winbond Systems Lab.

2730 Orchard Parkway, San Jose,
CA 95134, U.S.A.
TEL: 1-408-9436666
FAX: 1-408-9436668

Note: All data and specifications are subject to change without notice.

Part Number W83759