TOSHIBA
TOSHIBA CORPORATION
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TLCS-90 Series
TMP90CM40
The information contained here is subject to change without notice.
The information contained herein is presented only as guide for the applications of our products. No responsibility is assumed by TOSHIBA for any infringements of patents or other rights of the third parties
which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of TOSHIBA or others. These TOSHIBA products are intended for usage in general electronic
equipments (office equipment, communication equipment, measuring equipment, domestic electrification, etc.) Please make sure that you consult with us before you use these TOSHIBA products in equip-
ments which require high quality and/or reliability, and in equipments which could have major impact to the welfare of human life (atomic energy control, spaceship, traffic signal, combustion control, all types
of safety devices, etc.). TOSHIBA cannot accept liability to any damage which may occur in case these TOSHIBA products were used in the mentioned equipments without prior consultation with TOSHIBA.
CMOS 8Bit Microcontrollers
TMP90CM40N/TMP90CM40F
1. Outline and Characteristics
The TMP90CM40 is a high-speed advanced 8-bit microcontroller
applicable to a variety of equipment.
With its 8-bit CPU, ROM, RAM, A/D converter, multi-function
timer/event counter and general-purpose serial interface
integrated into a single CMOS chip, the TMP90C640A allows
the expansion of external memories for programs (up to 31K
byte) and data (1M byte).
The TMP90CM40N is a 64-pin shrink DIP product.
(SDIP64-P750)
The TMP90CM40F is a 64-pin flat package product.
(QFP64-P1420A)
The characteristics of the TMP90CM40 include:
(1)
Powerful instructions: 163 basic instructions, including
Multiplication, division, 16-bit arithmetic operations, bit
manipulation instructions
(2)
Minimum instruction executing time:
320ns (at 12.5MHz oscillation frequency)
(3)
Internal ROM: 32K byte
(4)
Internal RAM: 1K byte
(5)
Memory expansion
Program memory: 64K byte
Data memory: 1M byte
(6)
8-bit A/D converter (6 channels)
(7)
General-purpose serial interface
Asynchronous mode, I/O interface mode
(8)
Multi-function 16-bit timer/event counter (1 channel)
(9)
8-bit timers (4 channels)
10)
Stepping motor control port (2 channels)
(11)
Input/Output ports (54 pins)
(12)
Interrupt function: 10 internal interrupts and 4 external
interrupts
(13)
Micro Direct Memory Access (
µ
DMA) function (11 channels)
(14)
Watchdog timer
(15)
Standby function (4 HALT modes)
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TMP90CM40
Figure 1. TMP90CM40 Block Diagram
TOSHIBA CORPORATION
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TMP90CM40
2. Pin Assignment and Functions
The assignment of input/output pins, their names and functions
are described below.
2.1 Pin Assignment
Figure 2.1 (1) shows pin assignment of the TMP90CM40N.
Figure 2.1 (1). Pin Assignment
(Shrink Dual Inline Package)
Figure 2.1 (2) shows pin assignment of the TMP90CM40F.
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TOSHIBA CORPORATION
TMP90CM40
Figure 2.1 (2). Pin Assignment (Flat Package)
2.2 Pin Names and Functions
The names of input/output pins and their functions are summarized
in Table 2.2.
Table 2.2 Pin Names and Functions (1/3)
Pin Name
No. of pins
I/O 3 states
Function
P00 ~ P07
/D0 ~ D7
8
I/O
Port 0: 8-bit I/O port that allows selection of input/output on byte basis
3 states
Data bus: Also functions as 8-bit bidirectional data bus for external memory
P10 ~ P17
/A0 ~ A7
8
I/O
Port 1: 8-bit I/O port that allows selection on byte basis
Output
Address bus: The lower 8 bits address bus for external memory
P20 ~ P27
/A8 ~ A15
8
I/O
Port 2: 8-bit I/O port that allows selection on bit basis
Output
Address bus: The upper 8 bits address bus for external memory
P30
/RxD
1
Input
Port 30: 1-bit input port
Receiver Serial Data
P31
/RxD
1
Input
Port 31: 1-bit input port
Receiver Serial Data
P32
/TxD
/RTS
/SCLK
1
Output
Port 32: 1-bit input port
Transmitter Serial Data
Request to send Serial data
Serial clock output
P33
/TxD
1
Output
Port 33: 1-bit output port
Transmitter Serial Data
P34
/CTS
1
Input
Port 34: 1-bit input port
Clear to send Serial data
P35
/RD
1
Output
Port 35: 1-bit output port
Read: Generates strobe signal for reading external memory
P36
/WR
1
Output
Port 36: 1-bit output port
Write: Generates strobe signal for writing into external memory
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TMP90CM40
Table 2.2 Pin Names and Functions (2/3)
Pin Name
No. of Pins
I/O 3 states
Function
P37
/WAIT
1
Input
Port 37: 1-bit input port
Wait: Input pin for connecting slow speed memory or peripheral LSI
P40 ~ P43
/A16 ~ A19
4
Output
Port 4: 4-bit output port that allows selection of Port/Address Bus on bit basis
Address bus: Also functions as address bus for external memory
(4 bits of bank address)
P50 ~ P55
/AN0 ~ AN5
6
Input
Port 5: 6-bit input port
Analog input: 6 analog input to A/D converter
VREF
1
Input of reference voltage to A/D converter
AGND
1
Ground pin for A/D converter
P60 ~ P63
/M00 ~ M03
/TO1
4
I/O
Port 6: 4-bit I/O port that allows I/O selection on bit basis
Output
Stepping motor control port 0
Output
Timer output 1: Output of Timer 0 or 1
P70 ~ P73
/M10 ~ M13
/TO3
4
I/O
Port 7: 4-bit I/O port that allows I/O selection on bit basis
Output
Stepping motor control port 1
Output
Timer output 3: Output of Timer 2 or 3
P80
/INTO
1
Input
Port 80: 1-bit input port
Interrupt request pin 0: Interrupt request pin (Level/rising edge is
programmable)
P81
/INT1
/TI4
1
Input
Port 81: 1-bit input port
Interrupt request pin 1: Interrupt request pin (Rising/falling edge is
programmable)
Timer input 4: Counter/capture trigger signal for Timer 4
P82
/INT2
/TI5
1
Input
Port 82: 1-bit input port
Interrupt request pin 2: rising edge interrupt request pin
Timer input 5: capture trigger signal for Timer 4
P82
/TO3/T04
1
Output
Port 83: 1-bit output port
Timer output 3/4: Output of Timer 2, 3 or 4
NMI
1
Input
Non-maskable interrupt request pin: Falling edge interrupt request pin
CLK
1
Output
Clock output: Generates clock pulse at 1/4 frequency of clock oscillation. It is
Pulled up internally during resetting.
EA
1
Input
External access: Connect to the V
CC
pin in the internal ROMis used, connect to
the GND pin when an external memory is used.
RESET
1
Input
Reset: Initializes the TMP 90CM40A. (Built-in pull-up resistor)
X1/X2
2
Input/
Output
Pin for quartz crystal or ceramic resonator
V
CC
1
Power supply (+5V)
V
SS
(GND)
1
Ground (0V)
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TMP90CM40
3. Operation
The following explains the TMP90CM40 function and basic
operations. The CPU functions and internal I/O functions of
the TMP90CM40 are the same as the TMP90C840A.
Refer to the "TMP90C840A" section concerning functions
which are not explained in the following.
3.1 CPU
The TMP90CM40 has an internal high-performance 8-bit
CPU.
Refer to the book TLCS 90 Series CPU Core Architec-
ture concerning CPU operation.
3.2 Memory Map
The TMP90CM40 supports a program memory of up to 64K
bytes and a data memory of maximum 1Mbytes.
The program memory may be assigned to the address
space from 00000H to 0FFFFH, while the data memory can
be allocated to any address from 00000H to FFFFFH.
(1)
Internal ROM
The TMP90CM40 internally contains a 32K byte ROM.
The address space from 0000H to 7FFFH is provided to
the ROM. The CPU starts executing a program from
0000H by resetting.
The addresses 0010H to 007FH in this internal ROM
area are used for the entry area for the interrupt processing.
(2)
Internal RAM
The TMP90CM40 also contains a 1K byte RAM, which
is allocated to the address space from FBC0H to
FFBFH. The CPU allows the access to a certain RAM
area (FF00H to FFBFH, 192 bytes) by a short opera-
tion code (opcode) in a "direct addressing mode".
The addresses FF10H to FF7FH in this internal RAM
area can be used as parameter area for micro DMA
processing (and for any other purpose when the micro
DMA function is not used).
(3)
Internal I/O
The TMP90CM40 provides a 48-byte address space
as an internal I/O area, whose addresses range from
FFC0H to FFEFH. This I/O area can be accessed by
the CPU using a short opcode in the "direct
addressing mode".
Figure 3.1 (1) is a memory map indicating the areas
accessible by the CPU in the respective addressing
mode.
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TMP90CM40
Figure 3.2. Memory Map
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TOSHIBA CORPORATION
TMP90CM40
4. Electrical Characteristics
TMP90CM40N/TMP90CM40F
Note: I
DAR
is guaranteed for a total of up to 8 optional ports.
4.1 Absolute Maximum Ratings
Symbol
Parameter
Rating
Unit
V
CC
Supply voltage
-0.5 ~ + 7
V
V
IN
Input voltage
-0.5 ~ V
CC
+ 0.5
V
P
D
Power dissipation (Ta = 85
°
C)
F 500
mW
N 600
T
SOLDER
Soldering temperature (10s)
260
°
C
T
STG
Storage temperature
-65 ~ 150
°
C
T
OPR
Operating temperature
-40 ~ 85
°
C
4.2 DC Characteristics
V
CC
= 5V
±
10% TA = -40 ~ 85
°
C (1 ~ 10MHz)
TA = -20 ~ 70
°
C (10 ~ 12.5MHz)
Typical Values are for TA = 25
°
C V
CC
= 5V.
Symbol
Parameter
Min
Max
Unit
Test Conditions
V
IL
Input Low Voltage (P0)
-0.3
0.2V
CC
- 0.1
V
V
IL1
P1, P2, P3, P4, P5, P6, P7, P8
-0.3
0.3V
CC
V
V
IL2
RESET, INT0 (P80), NMI
-0.3
0.25V
CC
V
V
IL3
EA
-0.3
0.3
V
V
IL4
X1
-0.3
0.2V
CC
V
V
IH
Input High Voltage (P0)
0.2V
CC
+ 1.1
V
CC
+ 0.3
V
V
IH1
P1, P2, P3, P4, P5, P6, P7, P8
0.7V
CC
V
CC
+ 0.3
V
V
IH2
RESET, INT0 (P80), NMI
0.75V
CC
V
CC
+ 0.3
V
V
IH3
EA
V
CC
- 0.3
V
CC
+ 0.3
V
V
IH4
X1
0.8V
CC
V
CC
+ 0.3
V
V
OL
Output Low Voltage
0.45
V
I
OL
= 1.6mA
V
OH
V
OH1
V
OH2
Output High Voltage
2.4
0.75V
CC
0.9V
CC
V
V
V
I
OH
= -400
µ
A
I
OH
= -100
µ
A
I
OH
= -20
µ
A
I
DAR
Darlington Drive Current
(8 I/O pins) (Note)
-1.0
-3.5
mA
V
EXT
= 1.5V
R
EXT
= 1.1k
I
LI
Input Leakage Current
0.02 (Typ)
±
5
µ
A
0.0
Vin
V
CC
I
LO
Output Leakage Current
0.05 (Typ)
±
10
µ
A
0.2
Vin
V
CC
- 0.2
I
CC
Operating Current (RUN)
Idle 1
Idle 2
20 (Typ)
1.5 (Typ)
8 (Typ)
40
5
15
mA
mA
mA
tosc = 10MHz
(25% up @ 12.5MHz)
STOP (TA = -40 ~ 85
°
C)
STOP (TA = 0 ~ 50
°
C)
0.2 (Typ)
50
10
µ
A
µ
A
0.2
Vin
V
CC
- 0.2
V
STOP
Power Down Voltage (@STOP)
2
RAM BACK UP
6
V
V
IL2
= 0.2V
CC
,
V
IH2
= 0.8V
CC
R
RST
RESET Pull Up Register
50
150
K
CIO
Pin Capacitance
10
pF
testfreq = 1MHz
V
TH
Schmitt width RESET, NMI, INT0
0.4
1.0 (Typ)
V
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TMP90CM40
· AC output level High 2.2V/Low 0.8V
· AC input level High 2.4V/Low 0.45V (D0 D7)
High 0.8V
CC
/Low 0.2V
CC
(excluding D0 D7)
4.3 AC Characteristics
V
CC
= 5V
±
10% TA = -40 ~ 85
°
C (1 ~ 10MHz)
CL = 50pF TA = -20 ~ 70
°
C (10 ~ 12.5MHz)
Symbol
Parameter
Variable
10MHz Clock
12.5MHz Clock
Unit
Min
Max
Min
Max
Min
Max
t
OSC
OSC. Period = x
80
1000
100
80
ns
t
CYC
CLK Period
4x
4x
400
320
ns
t
WL
CLK Low width
2x - 40
160
120
ns
t
WH
CLK High width
2x - 40
160
120
ns
t
AC
Address Setup to RD, WR
x - 45
55
35
ns
t
RR
RD Low width
2.5x - 40
210
160
ns
t
CA
Address Hold Time After RD, WR
0.5x - 30
20
10
ns
t
AD
Address to Valid Data In
3.5x - 95
255
185
ns
t
RD
RD to Valid Data In
2.5x - 80
170
120
ns
t
HR
Input Data Hold After RD
0
0
0
ns
t
WW
WR Low width
2.5x - 40
210
160
ns
t
DW
Data Setup to WR
2x - 50
150
110
ns
t
WD
Data Hold After WR
30
90
30
90
30
90
ns
t
CWA
RD, WR to Valid WAIT
1.5x - 100
50
20
ns
t
AWA
Address to Valid WAIT
2.5x - 130
120
70
ns
t
WAS
WAIT Setup to CLK
70
70
70
ns
t
WAH
WAIT Hold After CLK
0
0
0
ns
t
RV
RD, WR Recovery Time
1.5x - 35
115
85
ns
t
CPW
CLK to Port Data Output
x + 200
300
280
ns
t
PRC
Port Data Setup to CLK
200
200
200
ns
t
CPR
Port Data Hold After CLK
100
100
100
ns
t
CHCL
RD/WR Hold After CLK
x - 60
40
20
ns
t
CLC
RD/WR Setup to CLK
1.5x - 50
100
70
ns
t
CLHA
Address Hold After CLK
1.5x - 80
70
40
ns
t
ACL
Address Setup to CLK
2.5x - 80
170
120
ns
t
CLD
Data Setup to CLK
x - 50
50
30
ns
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TMP90CM40
4.4 A/D Conversion Characteristics
V
CC
= 5V
±
10% TA = -40 ~ 85
°
C (1 ~ 10MHz)
TA = -20 ~ 70
°
C (10 ~ 12.5MHz)
Symbol
Parameter
Min
Typ
Max
Unit
V
REF
Analog reference voltage
V
CC
- 1.5
V
CC
V
CC
V
A
GND
Analog reference voltage
V
SS
V
SS
V
SS
V
AIN
Allowable analog input voltage
V
SS
V
CC
I
REF
Supply current for analog reference voltage
0.5
1.0
mA
Error
Total error
(TA = 25
°
C, V
CC
= V
REF
= 5.0V)
1.0
LSB
Total error
2.5
4.5 Zero-Cross Characteristics
V
CC
= 5V
±
10% TA = -40 ~ 85
°
C (1 ~ 10MHz)
TA = -20 ~ 70
°
C (10 ~ 12.5MHz)
Symbol
Parameter
Condition
Min
Max
Unit
V
ZX
Zero-cross detection input
AC coupling C = 0.1
µ
F
1
1.8
VAC p - p
A
ZX
Zero-cross accuracy
50/60Hz sine wave
135
mV
F
ZX
Zero-cross detection input frequency
0.04
1
kHz
4.6 Serial Channel Timing-I/O Interface Mode
V
CC
= 5V
±
10% TA = -40 ~ 85
°
C (1 ~ 10MHz)
CL = 50pF TA = -20 ~ 70
°
C (10 ~ 12.5MHz)
Symbol
Parameter
Variable
10MHz Clock
12.5MHz Clock
Unit
Min
Max
Min
Max
Min
Max
t
SCY
Serial Port Clock Cycle Time
8x
800
640
ns
t
OSS
Output Data Setup SCLK Rising Edge
6x - 150
450
330
ns
t
OHS
Output Data Hold After SCLK Rising Edge
2x - 120
80
40
ns
t
HSR
Input Data Hold After SCLK Rising Edge
0
0
0
ns
t
SRD
SCLK Rising Edge to Input DATA Valid
6x - 150
450
330
ns
4.7 16-bit Event Counter
V
CC
= 5V
±
10% TA = -40 ~ 85
°
C (1 ~ 10MHz)
TA = -20 ~ 70
°
C (10 ~ 12.5MHz)
Symbol
Parameter
Variable
10MHz Clock
12.5MHz Clock
Unit
Min
Max
Min
Max
Min
Max
t
VCK
TI4 clock cycle
8x + 100
900
740
ns
t
VCKL
TI4 Low clock pulse width
4x + 40
440
360
ns
t
VCKH
TI4 High clock pulse width
4x + 40
440
360
ns
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TMP90CM40
(Reference) Definition of I
DAR
4.9 I/O Interface Mode Timing
TMP90CM40A I/O Interface Mode Timing Waveforms
4.8 Interrupt Operation
V
CC
= 5V
±
10% TA = -40 ~ 85
°
C (1 ~ 10MHz)
TA = -20 ~ 70
°
C (10 ~ 12.5MHz)
Symbol
Parameter
Variable
10MHz Clock
12.5MHz Clock
Unit
Min
Max
Min
Max
Min
Max
t
INTAL
NMI, INT0 Low level pulse width
4x
400
320
ns
t
INTAH
NMI, INT0 High level pulse width
4x
400
320
ns
t
INTBL
INT1, INT2 Low level pulse width
8x + 100
900
740
ns
t
INTBH
INT1, INT2 High level pulse width
8x + 100
900
740
ns
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TOSHIBA CORPORATION
TMP90CM40
4.10 Timing Chart
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