TSB11LV01

3-V 1-PORT IEEE 1394-1995 CABLE TRANSCEIVER/ARBITER

SLLS232B MARCH 1996 REVISED MAY 1997

POST OFFICE BOX 655303

DALLAS, TEXAS 75265

Supports Provisions of IEEE 1394-1995
Standard for High Performance Serial Bus

Fully Interoperable With FireWire

Implementation of IEEE 1394-1995

Provides A Single Fully-Compliant Cable
Port at 100 Megabits per Second (Mbits/s)

Cable Port Monitors Line Conditions for
Active Connection to a Remote Node

Inactive Port Disabled to Save Power

Cable Inactivity Monitor Output and
Power-down Input Provided for Additional
Sleep-Mode Power Savings

Internal Bandgap Reference Provided for
Setting Stable Operating Bias Conditions

Logic Performs System Initialization and
Arbitration Functions

Encode and Decode Functions Included for
Data-Strobe Bit-Level Encoding

Incoming Data Resynchronized to Local
Clock

Data Interface to Link Layer Controller
(Link) Provided Through Two Parallel
Signal Lines at 50 Mbits/s

25-MHz Crystal Oscillator and PLL Provide
Transmit, Receive Data, and Link Layer
Controller Clocks at 50 MHz

Digital I/Os are 5 V tolerant

Node Power Class Information Signaling
for System Power Management

Cable Power Presence Monitoring

Cable Bias and Driver Termination Voltage
Supply

Single 3-V Supply Operation

Separate Multiple Package Terminals
Provided for Analog and Digital Supplies
and Grounds

High Performance 48-Pin TQFP (PT)
Package

description

The TSB11LV01 provides the analog transceiver functions needed to implement a single port node in a cable
based IEEE 1394-1995 network. The cable port incorporates two differential line transceivers. The transceivers
include circuitry to monitor the line conditions as needed for determining connection status, for initialization and
arbitration, and for packet reception and transmission. The TSB11LV01 is designed to interface with a link layer
controller, such as the TSB12C01A.

The TSB11LV01 requires an external 24.576-MHz crystal, which drives an internal phase-locked loop (PLL)
generating the required 98.304-MHz reference signal. The 98.304-MHz reference signal is internally divided
to provide the 49.152-MHz

100 ppm system clock signals that control transmission of the outbound encoded

strobe and data information. The 49.152-MHz clock signal is also supplied to the associated link for
synchronization of the two chips and is used for resynchronization of the received data. The power-down
function, when enabled by asserting the PWRDN terminal high, stops operation of the PLL.

Data bits to be transmitted are received from the link on two parallel paths and are latched internally in the
TSB11LV01 in synchronization with the 49.152-MHz system clock. These bits are combined serially, encoded,
and transmitted at 98.304-Mbits/s as the outbound data-strobe information stream. During transmit, the
encoded data information is transmitted differentially on the TPB cable pair, and the encoded strobe information
is transmitted differentially on the TPA cable pair.

NOTE

In this document, phy is the physical layer and link is the link layer controller.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.

1997, Texas Instruments Incorporated

Implements technology covered by one or more patents of Apple Computer, Incorporated and SGS Thomson, Limited.
FireWire is a trademark of Apple Computer, Incorporated.

TSB11LV01

3-V 1-PORT IEEE 1394-1995 CABLE TRANSCEIVER/ARBITER

SLLS232B MARCH 1996 REVISED MAY 1997

POST OFFICE BOX 655303

DALLAS, TEXAS 75265

description (continued)

During packet reception the TPA and TPB transmitters of the cable port are disabled, and the receivers of the
port are enabled. The encoded data information is received on the TPA cable pair, and the encoded strobe
information is received on the TPB cable pair. The received data-strobe information is decoded to recover the
receive clock signal and the serial data bits. The serial data bits are split into two parallel streams,
resynchronized to the local system clock and sent to the associated link.

Both the TPA and TPB cable interfaces incorporate differential comparators to monitor the line states during
initialization and arbitration. The outputs of these comparators are used by the internal logic to determine the
arbitration status. In addition, the TPB channel monitors the incoming cable common-mode voltage for the
presence of the remotely supplied twisted-pair bias voltage. The presence or absence of this bias voltage is an
indication of cable connection status. The cable connection status signal is internally debounced in the
TSB11LV01. The debounced cable connection status signal initiates a bus reset. On a cable
disconnect-to-connect, the debounce delay is 335 ms. On a connect-to-disconnect there is minimal debounce.

The TSB11LV01 provides a 1.86-V nominal bias voltage for driver load termination. This bias voltage, when
seen through a cable by a remote receiver, indicates the presence of an active connection. The value of this
bias voltage has been chosen to allow interoperation between transceiver chips operating from either 5-V
nominal supplies or 3-V nominal supplies. This bias voltage source should be stabilized by using an external
filter capacitor of at least 1

The transmitter circuitry is disabled under the following conditions: powerdown, cable not active, reset, or
transmitter disable. The receiver circuitry is disabled during powerdown, cable not active, or receiver disable.
The twisted-pair bias voltage circuitry is disabled during the powerdown or reset conditions. The power-down
condition occurs when the PWRDN input is asserted high. The cable-not-active condition occurs

TSB11LV01
3-V 1-PORT IEEE 1394-1995 CABLE TRANSCEIVER/ARBITER

SLLS232B MARCH 1996 REVISED MAY 1997

POST OFFICE BOX 655303

DALLAS, TEXAS 75265

description (continued)

when the cable connection status indicates no cable is connected and is not debounced. The device reset
condition occurs when the RESET input terminal is asserted low. The transmitter disable and receiver disable
conditions are determined from the internal logic.

The line drivers in the TSB11LV01 operate in the high-impedance current mode and are designed to work with
external 112-

line matching resistor networks. One network is provided at each end of each twisted-pair cable.

Each network is composed of a pair of series-connected 56-

resistors. The midpoint of the pair of resistors

that are directly connected to the twisted-pair A-package terminals is connected to the TPBIAS voltage terminal.
The midpoint of the pair of resistors that is directly connected to the twisted-pair B-package terminals is coupled
to ground through a parallel resistance-capacitance (R-C) network with the recommended value of 5 k

and

250 pF. The values of the external resistors are designed to meet the IEEE 1394-1995 standard specifications
when connected in parallel with the internal receiver circuits (see Figure 3).

An internal reference circuit (bandgap) provides stable bias voltages for the TSB11LV01 transceiver circuits.
The driver output current, along with other internal operating currents, is set by an external resistor. This resistor
is connected between terminals R1 and R0, and has a value of 6 k

0.5%.

Two of the package terminals set up various test conditions used in manufacturing. These terminals, TESTM1
and TESTM2, should be connected to V

for normal operation.

Four package terminals are inputs to set four configuration status bits in the self-identification (Self-ID) packet.
These terminals are hardwired high or low as a function of the equipment design. PC0, PC1, and PC2
(corresponds to bits 21, 22, and 23 of the Self-ID packet) are three terminals that indicate either the need for
power from the cable or the ability to supply power to the cable. The fourth terminal, C/LKON (corresponds to
bit 20 of the Self-ID packet), indicates if a node is a contender for bus manager. C/LKON may also output a
6.114-MHz

100 ppm signal, indicating reception of a link-on packet. See Table 4-29 of the IEEE 1394-1995

standard for additional details.

In order to operate with power supplies as low as 2.7 V, this device is restricted to applications that do not provide
cable power. See Note A in clause 4.2.2.2 of the IEEE 1394-1995 standard.

When the TSB11LV01 is used in applications with a 5-V link layer controller, such as the TSB12C01A, the
BIAS5V terminal should be connected to the link layer controller 5-V supply. Otherwise, connect this terminal
to DV

A power-down terminal (PWRDN) is provided to allow most of the TSB11LV01 circuits to be powered down to
conserve energy in battery-driven applications. A cable status terminal (CNA) provides a high output when the
twisted-pair cable port is disconnected. This output is not debounced. The CNA output can determine when to
power the device down. In the power-down mode all circuitry is disabled except the CNA detection circuitry.

If the power supply of the TSB11LV01 is removed while the twisted-pair cables are connected, the TSB11LV01
transmitter and receiver circuitry has been designed to present a high-impedance signal to the cable and not
load the TPBIAS voltage on the other end of the cable.

TSB11LV01
3-V 1-PORT IEEE 1394-1995 CABLE TRANSCEIVER/ARBITER

SLLS232B MARCH 1996 REVISED MAY 1997

POST OFFICE BOX 655303

DALLAS, TEXAS 75265

Terminal Functions

TERMINAL

I/O

TYPE

DESCRIPTION

NAME

NO.

I/O

TYPE

DESCRIPTION

ÁÁÁÁÁ

ÁÁÁ

ÁÁÁÁÁ

AGND

ÁÁÁ

21, 23,
24, 26,

ÁÁÁ

Supply

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Analog circuit ground. The AGND terminals should be tied to the low-im-
pedance circuit board ground plane.

ÁÁÁÁÁ

ÁÁÁ

ÁÁÁÁÁ

AVCC

ÁÁÁ

22, 28,

29, 44

ÁÁÁ

Supply

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Analog circuit power. AVCC supplies power to the analog portion of the
device. It is recommended that a combination of high-frequency decoupling
capacitors be connected to AVCC (i.e., paralleled 0.1

F and 0.001

F).

Lower frequency 10-

F filtering capacitors can also be used. These supply

pins are separated internally in the device to provide noise isolation. These
terminals should also be tied at a low-impedance point on the circuit board.
Individual filtering networks for each is desired.

ÁÁÁÁÁ

ÁÁÁ

ÁÁÁÁÁ

C/LKON

ÁÁÁ

I/O

ÁÁÁ

CMOS

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Bus manager capable (input). When set as an input, C/LKON is used to
specify in the Self-ID packet that the node is bus manager capable.

ÁÁÁÁÁ

ÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Link-on (output). When set as an output, C/LKON indicates the reception of
a link-on message by asserting a 6.114-MHz signal. The bit value program-
ming is done by tying the terminal through a 10-k

resistor to VCC (high) or

to GND (low). Using either the pullup or pulldown resistor allows the LKON
output to override the input value when necessary.

ÁÁÁÁÁ

ÁÁÁ

ÁÁÁÁÁ

CNA

ÁÁÁ

CMOS

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Cable not active. CNA is asserted high when the TSB11LV01 port is not
connected to another active port.

ÁÁÁÁÁ

ÁÁÁ

ÁÁÁÁÁ

CPS

ÁÁÁ

CMOS

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Cable power status. CPS is normally connected to the cable power through
a 400-k

resistor. This circuit drives an internal comparator that detects the

presence of cable power. This information is maintained in two internal
registers and is available to the link by way of a register read. See the Phy-
Link Interface Application Note in the IEEE 1394-1995 standard.

ÁÁÁÁÁ

ÁÁÁ

ÁÁÁÁÁ

CTL0, CTL1

ÁÁÁ

8, 9

ÁÁÁ

I/O

ÁÁÁ

CMOS

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Control I/O. The CTL terminals are bidirectional communications control
signals between the TSB11LV01 and the link. These signals control the
passage of information between the two devices.

ÁÁÁÁÁ

D0, D1

ÁÁÁ

10, 11

ÁÁÁ

I/O

ÁÁÁ

CMOS

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Data I/O. The D terminals are bidirectional and pass data between the
TSB11LV01 and the link.

ÁÁÁÁÁ

ÁÁÁ

ÁÁÁÁÁ

DGND

ÁÁÁ

13, 15,
17, 19,

20,

ÁÁÁ

Supply

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Digital circuit ground. The DGND terminals should be tied to the low-imped-
ance circuit board ground plane.

ÁÁÁÁÁ

ÁÁÁ

ÁÁÁÁÁ

DVCC

ÁÁÁ

14, 18,

ÁÁÁ

Supply

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Digital circuit power. DVCC supplies power to the digital portion of the de-
vice. It is recommended that a combination of high-frequency decoupling
capacitors be connected to DVCC (i.e., paralleled 0.1

F and 0.001

F).

Lower frequency 10-

F filtering capacitors can also be used. These supply

ÁÁÁÁÁ

ÁÁÁ

ÁÁÁÁÁ

BIAS5V

ÁÁÁ

Supply

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

5 V bias. BIAS-5V should be connected to the link VCC supply when a 5-V
link is connected to the phy. When a 3-V link is used, BIAS-5V should be
connected to the phy DVCC.

ÁÁÁÁÁ

ÁÁÁ

ÁÁÁÁÁ

LPS

ÁÁÁ

CMOS

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Link power status. This terminal is connected to either the VCC supplying
the link or to a pulsed output that is active when the link is powered for the
purpose of monitoring the link's power status. When this input is low for
more than 2.56

s, then the link is considered powered down. When this

input is high for more than 80 ns, then the link is considered powered up. If
the link is not powered, the phylink interface is disabled, and the
TSB11LV01 performs only the basic repeater functions required for network
initialization and operation.

ÁÁÁÁÁ

ÁÁÁ

ÁÁÁÁÁ

LREQ

ÁÁÁ

CMOS

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Link request. LREQ is an input from the link that signals the TSB11LV01 of
a request to perform some service.

TSB11LV01

3-V 1-PORT IEEE 1394-1995 CABLE TRANSCEIVER/ARBITER

SLLS232B MARCH 1996 REVISED MAY 1997

POST OFFICE BOX 655303

DALLAS, TEXAS 75265

Terminal Functions (continued)

TERMINAL

I/O

TYPE

DESCRIPTION

NAME

NO.

I/O

TYPE

DESCRIPTION

ÁÁÁÁÁÁ

ÁÁÁÁ

ÁÁÁÁÁÁ

PC0, PC1, PC2

ÁÁÁ

4, 5, 6

ÁÁ

ÁÁÁÁ

ÁÁ

ÁÁÁÁ

CMOS

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Power class indicators. the PC signals set the bit values of the three power
class bits in the Self-ID packet (bits 21, 22, and 23). These bits can be pro-
grammed by tying the terminals to VCC (high) or to GND (low).

ÁÁÁÁÁÁ

ÁÁÁÁ

ÁÁÁÁÁÁ

PLLFLT

ÁÁÁ

ÁÁ

ÁÁÁÁ

ÁÁ

ÁÁÁÁ

CMOS

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

PLL filter. PLLFLT is connected to a 0.1-

F capacitor and then to AGND to

complete the internal lag-lead filter. This filter is required for stable opera-
tion of the frequency multiplier PLL running off of the crystal oscillator.

ÁÁÁÁÁÁ

PLLGND

ÁÁÁ

39, 40

ÁÁ

ÁÁÁÁ

Supply

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

PLL circuit ground. The PLLGND terminals should be tied to the low-imped-
ance circuit board ground plane.

ÁÁÁÁÁÁ

ÁÁÁÁ

ÁÁÁÁÁÁ

PLLVCC

ÁÁÁ

ÁÁ

ÁÁÁÁ

ÁÁ

ÁÁÁÁ

Supply

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

PLL circuit power. PLLVCC supplies power to the PLL portion of the device.
It is recommended that a combination of high-frequency decoupling capaci-
tors be connected to PLLVCC (i.e., paralleled 0.1

F and 0.001

F). Lower

frequency 10-

F filtering capacitors can also be used. These supply pins

are separated internally in the device to provide noise isolation. These ter-
minals should also be tied at a low impedance point on the circuit board.
Individual filtering networks for each is desired.

ÁÁÁÁÁÁ

ÁÁÁÁ

ÁÁÁÁÁÁ

PWRDN

ÁÁÁ

ÁÁ

ÁÁÁÁ

ÁÁ

ÁÁÁÁ

CMOS

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Powerdown. When asserted high, PWRDN turns off all internal circuitry
except the CNA monitor circuits that drive the CNA terminal.

ÁÁÁÁÁÁ

ÁÁÁÁ

ÁÁÁÁÁÁ

R1, R0

ÁÁÁ

31, 32

ÁÁ

ÁÁÁÁ

ÁÁ

ÁÁÁÁ

Bias

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Current setting resistor. An internal reference voltage is applied to a resistor
connected between these two terminals to set the operating current and the
cable driver output current. A low TCR 6 k

5% resistor should be used to

meet the IEEE 1394-1995 standard requirements for output voltage limits.

ÁÁÁÁÁÁ

ÁÁÁÁ

ÁÁÁÁÁÁ

RESET

ÁÁÁ

ÁÁ

ÁÁÁÁ

ÁÁ

ÁÁÁÁ

CMOS

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Reset. When RESET is asserted low (active), a bus reset condition is set
on the active cable ports and the the internal logic is reset to the reset start
state. An internal pullup resistor, which is connected to VCC, is provided so
only an external delay capacitor is required. This input is a standard logic
buffer and can also be driven by an open-drain logic output buffer.

ÁÁÁÁÁÁ

ÁÁÁÁ

ÁÁÁÁÁÁ

SYSCLK

ÁÁÁ

ÁÁ

ÁÁÁÁ

ÁÁ

ÁÁÁÁ

CMOS

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

System clock. SYSCLK provides a 49.152-MHz clock signal, which is syn-
chronized with the data transfers, to the link.

ÁÁÁÁÁÁ

TESTM1,
TESTM2

ÁÁÁ

48, 47

ÁÁ

ÁÁÁÁ

CMOS

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Test mode control. TESTM1 and TESTM2 are used during manufacturing
test and should be tied to VCC.

ÁÁÁÁÁÁ

TPA +

ÁÁÁ

ÁÁ

I/O

ÁÁÁÁ

Cable

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Port cable pair A. TPA is the port A connection to the twisted pair cable.
Board traces from these terminal should be kept matched and as short as

ÁÁÁÁÁÁ

TPA

ÁÁÁ

ÁÁ

ÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Board traces from these terminal should be ke t matched and as short as
possible to the external load resistors and to the cable connector.

ÁÁÁÁÁÁ

ÁÁÁÁ

ÁÁÁÁÁÁ

TPB +

ÁÁÁ

ÁÁ

I/O

ÁÁÁÁ

ÁÁ

ÁÁÁÁ

Cable

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Port cable pair B. TPB is the port B connection to the twisted pair cable.
Board traces from these terminal should be kept matched and as short as

ÁÁÁÁÁÁ

TPB

ÁÁÁ

ÁÁ

ÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Board traces from these terminal should be ke t matched and as short as
possible to the external load resistors and to the cable connector.

ÁÁÁÁÁÁ

ÁÁÁÁ

ÁÁÁÁÁÁ

TPBIAS

ÁÁÁ

ÁÁ

ÁÁÁÁ

ÁÁ

ÁÁÁÁ

Cable

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Twisted-pair bias. TPBIAS provides the 1.86-V nominal bias voltage need-
ed for proper operation of the twisted-pair cable drivers and receivers and
for sending a valid cable connection signal to the remote nodes.

ÁÁÁÁÁÁ

ÁÁÁÁ

ÁÁÁÁÁÁ

XO, XI

ÁÁÁ

37, 38

ÁÁ

ÁÁÁÁ

ÁÁ

ÁÁÁÁ

Crystal

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Crystal oscillator. X0 and X1 connect to a 24.576-MHz parallel resonant
fundamental mode crystal. The optimum values for the external shunt ca-
pacitors are dependent on the specifications of the crystal used. The sug-
gested values of 12 pF are appropriate for a crystal with 15 pF specified
loads.

TSB11LV01
3-V 1-PORT IEEE 1394-1995 CABLE TRANSCEIVER/ARBITER

SLLS232B MARCH 1996 REVISED MAY 1997

POST OFFICE BOX 655303

DALLAS, TEXAS 75265

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

Supply voltage range, V

0.5 V to 4 V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Input voltage range, V

0.5 V to V

+ 0.5 V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Output voltage range at any output, V

0.5 V to V

+ 0.5 V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Continuous total power dissipation

See Dissipation Rating Table

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Operating free air temperature, T

C to 70

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Storage temperature range, T

stg

C to 150

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds

300

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and

functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

DISSIPATION RATING TABLE

PACKAGE

POWER RATING

OPERATING FACTOR

ABOVE TA = 25

TA = 70

POWER RATING

1315 mW

10.5 mW/

842 mW

This is the inverse of the traditional junction-to-case thermal resistance (R

JA) and uses a

board-mounted 95

C/W.

recommended operating conditions

MIN

NOM

MAX

UNIT

ÁÁÁÁÁÁÁÁÁÁÁÁÁ

Supply voltage, VCC(SP)

ÁÁÁÁÁÁÁÁÁÁÁÁ

ÁÁÁÁ

ÁÁÁ

3.3

ÁÁÁÁ

3.6

ÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁ

Supply voltage, VCC(NSP)

ÁÁÁÁÁÁÁÁÁÁÁÁ

ÁÁÁÁ

2.7

ÁÁÁ

ÁÁÁÁ

3.6

ÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁ

High-level input voltage, VIH

ÁÁÁÁÁÁÁÁÁÁÁÁ

CMOS inputs

ÁÁÁÁ

0.7 VCC

ÁÁÁ

ÁÁÁÁ

ÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁ

Low-level input voltage, VIL

ÁÁÁÁÁÁÁÁÁÁÁÁ

CMOS inputs

ÁÁÁÁ

ÁÁÁ

ÁÁÁÁ

0.2 VCC

ÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁ

Differential input voltage, VID

ÁÁÁÁÁÁÁÁÁÁÁÁ

Cable inputs

ÁÁÁÁ

142

ÁÁÁ

ÁÁÁÁ

260

ÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁ

Common mode input voltage V

ÁÁÁÁÁÁÁÁÁÁÁÁ

Cable inputs,

VCC > 3 V

ÁÁÁÁ

1.165

ÁÁÁ

ÁÁÁÁ

2.515

ÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁ

Common-mode input voltage, VIC

ÁÁÁÁÁÁÁÁÁÁÁÁ

Cable inputs,

VCC < 3 V

ÁÁÁÁ

1.165

ÁÁÁ

ÁÁÁÁ

2.015

ÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁ

Receive input jitter

ÁÁÁÁÁÁÁÁÁÁÁÁ

TPA, TPB cable inputs

ÁÁÁÁ

ÁÁÁ

ÁÁÁÁ

1.08

ÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁ

Receive input skew

ÁÁÁÁÁÁÁÁÁÁÁÁ

Between TPA and TPB cable inputs

ÁÁÁÁ

ÁÁÁ

ÁÁÁÁ

0.8

ÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁ

High or low level output current IOL or IOH

ÁÁÁÁÁÁÁÁÁÁÁÁ

SYSCLK

ÁÁÁÁ

ÁÁÁ

ÁÁÁÁ

ÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁ

High- or low-level output current, IOL or IOH

ÁÁÁÁÁÁÁÁÁÁÁÁ

CTL0, CTL1, D0, D1, CNA

ÁÁÁÁ

ÁÁÁ

ÁÁÁÁ

ÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁ

Output current, IO

ÁÁÁÁÁÁÁÁÁÁÁÁ

TPBIAS

ÁÁÁÁ

ÁÁÁ

ÁÁÁÁ

ÁÁÁ

This parameter is for a node that does not source power (see section 4.2.2.2 in IEEE 1394-1995 standard).

electrical characteristics over recommended ranges of operating conditions (unless otherwise
noted)

driver

PARAMETER

TEST CONDITION

MIN

MAX

UNIT

ÁÁÁÁ

VOD

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Differential output voltage

ÁÁÁÁÁÁÁÁÁÁ

56-

load

ÁÁÁ

172

ÁÁÁÁ

265

ÁÁÁ

ÁÁÁÁ

I(DIFF)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Driver difference output current

ÁÁÁÁÁÁÁÁÁÁ

Driver enabled

ÁÁÁ

1.05§

ÁÁÁÁ

1.05§

ÁÁÁ

ÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Off-state voltage

ÁÁÁÁÁ

ÁÁÁÁÁÁ

ÁÁÁ

ÁÁÁÁ

ÁÁÁ

§ This parameter limits are defined as algebraic sum of TPA+ and TPA driver currents. These limits also apply to TPB+ and TPA algebraic sum

of driver currents.

TSB11LV01

3-V 1-PORT IEEE 1394-1995 CABLE TRANSCEIVER/ARBITER

SLLS232B MARCH 1996 REVISED MAY 1997

POST OFFICE BOX 655303

DALLAS, TEXAS 75265

receiver

PARAMETER

TEST CONDITION

MIN

MAX

UNIT

ÁÁÁ

IIC

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Common-mode input current

ÁÁÁÁÁÁÁÁÁÁ

Driver disabled

ÁÁÁ

zID

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Differential input impedance

ÁÁÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁ

Driver disabled

ÁÁÁ

zIC

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Common-mode input impedance

ÁÁÁÁÁÁÁÁÁÁ

Driver disabled

ÁÁÁ

VIT1

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Receiver input threshold voltage

ÁÁÁÁÁÁÁÁÁÁ

ÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Cable-bias detect threshold, TPB cable input

ÁÁÁÁÁÁÁÁÁÁ

Driver disabled

ÁÁÁ

0.6

ÁÁÁ

device

PARAMETER

TEST CONDITION

MIN

TYP

MAX

UNIT

ÁÁÁÁ

VIT2

ÁÁÁÁÁÁÁÁÁÁÁ

Power status input threshold voltage (CPS)

ÁÁÁÁÁÁÁÁÁ

400-k

resistor

ÁÁÁÁÁ

4.7

ÁÁÁ

ÁÁÁÁ

7.5

ÁÁÁ

ÁÁÁÁ

VOH

ÁÁÁÁÁÁÁÁÁÁÁ

High-level output voltage

ÁÁÁÁÁ

IOH = max,

ÁÁÁÁÁ

VCC = min

ÁÁÁÁÁ

VCC 0.55

ÁÁÁ

ÁÁÁÁ

ÁÁÁ

ÁÁÁÁ

VOL

ÁÁÁÁÁÁÁÁÁÁÁ

Low-level output voltage

ÁÁÁÁÁ

IOL = min,

ÁÁÁÁÁ

VCC = max

ÁÁÁÁÁ

ÁÁÁ

ÁÁÁÁ

0.5

ÁÁÁ

ÁÁÁÁ

ÁÁ

ÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁ

Input current
(LREQ, LPS, PD, PC0, PC1, PC2)

ÁÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁÁ

VI=VCC or 0

ÁÁÁÁÁ

ÁÁÁ

ÁÁÁÁÁ

ÁÁÁ

ÁÁÁÁ

ÁÁ

ÁÁÁÁ

ÁÁÁ

ÁÁÁÁ

IOZ

ÁÁÁÁÁÁÁÁÁÁÁ

High-impedance-state output current
(CTL0, CTL1, D0, D1, C/LKON)

ÁÁÁÁÁÁÁÁÁ

VO= VCC or 0

ÁÁÁÁÁ

ÁÁÁ

ÁÁÁÁ

ÁÁÁ

ÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁ

P ll p inp t c rrent RESET

ÁÁÁÁÁ

VI =1.5 V

ÁÁÁÁÁ

ÁÁÁ

ÁÁÁÁ

ÁÁÁ

ÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁ

Pullup input current, RESET

ÁÁÁÁÁ

VI =0

ÁÁÁÁÁ

ÁÁÁ

ÁÁÁÁ

ÁÁÁ

ÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁ

Power-up reset time, RESET

ÁÁÁÁÁ

ÁÁÁ

ÁÁÁÁ

ÁÁÁ

ÁÁÁÁ

V(TO)+

ÁÁÁÁÁÁÁÁÁÁÁ

Positive arbitration comparator threshold
voltage

ÁÁÁÁÁ

ÁÁÁ

ÁÁÁÁ

168

ÁÁÁ

ÁÁÁÁ

ÁÁ

ÁÁÁÁ

V(TO)

ÁÁÁÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁ

Negative arbitration comparator threshold
voltage

ÁÁÁÁÁ

ÁÁÁ

ÁÁÁÁÁ

ÁÁÁ

ÁÁÁÁÁ

168

ÁÁÁ

ÁÁÁÁ

ÁÁ

ÁÁÁÁ

ÁÁÁ

ÁÁÁÁ

TPBIAS output voltage

ÁÁÁÁÁ

1.665

ÁÁÁ

ÁÁÁÁ

2.015

ÁÁÁ

ÁÁÁÁ

ICC

Supply current, receiver active

VCC = 3.6 V

ÁÁÁÁÁ

ÁÁÁ

ÁÁÁÁ

115

ÁÁÁ

ÁÁÁÁ

ICC(PD)

Supply current, power-down mode

VCC = 3 V

ÁÁÁÁÁ

ÁÁÁ

ÁÁÁÁ

ÁÁÁ

thermal characteristics

PARAMETER

TEST CONDITION

MIN

TYP

MAX

UNIT

ÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Junction-to-free-air thermal resistance

ÁÁÁÁÁ

Board mounted,

ÁÁÁÁÁ

No air flow

ÁÁÁ

C/W

ÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Junction-to-case-thermal resistance

ÁÁÁÁÁ

ÁÁÁ

C/W

switching characteristics

PARAMETER

ÁÁÁÁÁÁÁ

MEASURED

ÁÁÁÁÁÁÁ

TEST CONDITION

ÁÁÁ

MIN

ÁÁÁÁ

MAX

ÁÁÁ

UNIT

ÁÁ

Jitter, transmit

ÁÁÁÁÁÁÁ

TPA, TPB

ÁÁÁÁÁÁÁ

ÁÁÁ

ÁÁÁÁ

0.8

ÁÁÁ

ÁÁ

Skew time, transmit

ÁÁÁÁÁÁÁ

Between TPA and TPB

ÁÁÁÁÁÁÁ

ÁÁÁ

ÁÁÁÁ

0.4

ÁÁÁ

ÁÁ

Rise time, transmit

ÁÁÁÁÁÁÁ

10% to 90%

ÁÁÁÁÁÁÁ

RL = 55

, CL = 10 pF

ÁÁÁ

ÁÁÁÁ

3.2

ÁÁÁ

ÁÁ

Fall time, transmit

ÁÁÁÁÁÁÁ

90% to 10%

ÁÁÁÁÁÁÁ

RL = 55

, CL = 10 pF

ÁÁÁ

ÁÁÁÁ

3.2

ÁÁÁ

ÁÁ

tsu

Setup time, D, CTL, LREQ low or high before
SYSCLK

ÁÁÁÁÁÁÁ

50% to 50%

ÁÁÁÁÁÁÁ

See Figure 1

ÁÁÁ

ÁÁÁÁ

ÁÁÁ

ÁÁ

Hold time, D, CTL, LREQ low or high after
SYSCLK

ÁÁÁÁÁÁÁ

ÁÁÁÁÁ

ÁÁÁÁÁÁÁ

50% to 50%

ÁÁÁÁÁÁÁ

ÁÁÁÁÁ

ÁÁÁÁÁÁÁ

See Figure 1

ÁÁÁ

ÁÁÁÁ

ÁÁ

ÁÁÁÁ

ÁÁÁ

ÁÁ

Delay time, SYSCLK high to D, CTL low or high

ÁÁÁÁÁÁÁ

50% to 50%

ÁÁÁÁÁÁÁ

See Figure 2

ÁÁÁ

ÁÁÁÁ

ÁÁÁ

TSB11LV01

3-V 1-PORT IEEE 1394-1995 CABLE TRANSCEIVER/ARBITER

SLLS232B MARCH 1996 REVISED MAY 1997

POST OFFICE BOX 655303

DALLAS, TEXAS 75265

APPLICATION INFORMATION

internal register configuration

The accessible internal registers of this device are listed in Table 1. Descriptions of the internal register fields
are given in Table 2.

Table 1. Accessible Internal Registers

Address

0000

Physical ID

CPS

0001

RHB

IBR

0010

SPD

Rev

0011

AStat

BStat

Con

Reserved

0100

Reserved

0101

Reserved

0110

Looplnt

CPSlnt

CPS

Reserved

0111

Reserved

1000

Reserved

Table 2. Internal Register Field Descriptions

ÁÁÁÁ

ÁÁ

ÁÁÁÁ

Field

ÁÁÁ

Size

(Bits)

ÁÁÁÁÁ

ÁÁÁ

ÁÁÁÁÁ

Type

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Description

ÁÁÁÁ

ÁÁ

ÁÁÁÁ

AStat

ÁÁÁ

ÁÁÁÁÁ

ÁÁÁ

ÁÁÁÁÁ

Read only

AStat contains the line state of TPA. The status is indicated by the following:
11 = Z
01 = 1
10 = 0
00 = Invalid data state. Power-up reset initializes to this line state. This line state is also output dur-
ing transmit and receive operations. The line state outputs are generally valid during arbitration and
idle conditions on the bus.

ÁÁÁÁ

ÁÁ

ÁÁÁÁ

BStat

ÁÁÁ

ÁÁÁÁÁ

ÁÁÁ

ÁÁÁÁÁ

Read only

BStat contains the line state of TPB. The status is indicated by the following:
11 = Z
01 = 1
10 = 0
00 = Invalid data state. Power up reset initializes to this line state. This line state is also output dur-
ing transmit and receive operations. The line state outputs are generally valid during arbitration and
idle conditions on the bus.

ÁÁÁÁ

ÁÁ

ÁÁÁÁ

ÁÁÁ

ÁÁÁÁÁ

ÁÁÁ

ÁÁÁÁÁ

Read only

When Ch = 1, the port is a child, otherwise it is a parent. This bit is invalid after a hardware reset or a
bus reset until tree-ID processing is completed.

ÁÁÁÁ

ÁÁ

ÁÁÁÁ

Con

ÁÁÁ

ÁÁÁÁÁ

ÁÁÁ

ÁÁÁÁÁ

Read only

Con indicates the connection status of the port. When Con = 1, the port is connected, otherwise it is
disconnected. This bit is set to 1 by a hardware reset and is updated to reflect the actual cable con-
nection status of the port during bus reset. The TSB11LV01 contains connection debounce circuitry
that prevents a new cable connection on a port from initiating a bus reset until the connection status
has been stable for at least 335 ms. Similarly, a cable disconnect must be stable for 1.3 ms before a
bus reset is initiated.

ÁÁÁÁ

ÁÁ

ÁÁÁÁ

CPS

ÁÁÁ

ÁÁÁÁÁ

ÁÁÁ

ÁÁÁÁÁ

Read only

Cable power status (CPS) contains the status of the CPS input terminal. When cable power voltage
has dropped too low for reliable operation, this bit is reset (0). This bit is included twice in the internal
registers to expedite handling of the CPSInt.

CPSInt

Read/Write

CPSint indicates that a cable power status interrupt has occurred. This interrupt occurs whenever the
CPS input goes low. The interrupt indicates that the cable power voltage has dropped too low to ensure
reliable operation. This bit is cleared (0) by a hardware reset or by writing a 0 to this register. However,
if the CPS input is still low, another cable power status interrupt immediately occurs.

TSB11LV01
3-V 1-PORT IEEE 1394-1995 CABLE TRANSCEIVER/ARBITER

SLLS232B MARCH 1996 REVISED MAY 1997

POST OFFICE BOX 655303

DALLAS, TEXAS 75265

Table 2. Internal Register Field Descriptions (continued)

ÁÁÁÁÁ

ÁÁÁ

ÁÁÁÁÁ

Field

ÁÁÁ

Size

(Bits)

ÁÁÁÁ

ÁÁ

ÁÁÁÁ

Type

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Description

ÁÁÁÁÁ

ÁÁÁ

ÁÁÁÁÁ

ÁÁÁ

ÁÁÁÁ

ÁÁ

ÁÁÁÁ

Read/Write

The gap count (GC) register sets the fair and arb-reset gap times. The gap count may be set to a
particular value to optimize bus performance. Typically, the gap count should be set to 2 times the
maximum number of hops on the bus and should be set to the same value for all nodes on the bus.
The gap count can be set by either a write to this register or by reception or transmission of a
PHY_CONFIG packet. The gap count is reset to a 3Fh after a hardware reset or after two consecu-
tive bus resets without an intervening write to the gap count register (either a write to the gap count
register by the link or a PHY_CONFIG packet).

IBR

Read/Write

When set, initiate bus reset (IBR) causes this node to immediately initiate a bus reset. IBR is cleared
(0) after a hardware reset or a bus reset.

ÁÁÁÁÁ

ÁÁÁ

ÁÁÁÁÁ

ÁÁÁ

ÁÁÁÁ

ÁÁ

ÁÁÁÁ

Read/Write

IR indicates that the last bus reset was initiated in this TSB11LV01 phy. This bit is also included in
the Self-ID packet.

ÁÁÁÁÁ

ÁÁÁ

ÁÁÁÁÁ

LoopInt

ÁÁÁ

ÁÁÁÁ

ÁÁ

ÁÁÁÁ

Read/Write

LoopInt indicates that a configuration loop timeout has occurred. This interrupt occurs when the ar-
bitration controller waits for too long a period of time during tree-ID. This interrupt can indicate that
the bus is configured in a loop. This bit is cleared (0) by a hardware reset or by writing a 0 to this
register bit. It should be noted that the TSB11LV01 never generates this interrupt since it has only
one available port and, therefore, cannot be part of a loop.

ÁÁÁÁÁ

ÁÁÁ

ÁÁÁÁ

Read only

The number of ports (NP) contains the number of ports implemented in the core logic (not the num-
ber of ports actually on the device). For the TSB11LV01, NP is set to 0011.

ÁÁÁÁÁ

ÁÁÁ

ÁÁÁÁÁ

Physical ID

ÁÁÁ

ÁÁÁÁ

ÁÁ

ÁÁÁÁ

Read only

Physical ID contains the physical address of the local node. The physical ID defaults to a 09h after a
hardware reset or a bus reset until the Self-ID process has been completed. A complete Self-ID is
indicated by an unsolicited status transfer of the register 0 contents to the link.

ÁÁÁÁÁ

ÁÁÁ

ÁÁÁÁÁ

ÁÁÁ

ÁÁÁÁ

ÁÁ

ÁÁÁÁ

Read only

R indicates whether this node is the root node or not. This bit is cleared (0) on a hardware reset or a
bus reset. This bit is set during tree-ID when this node is root.

ÁÁÁÁÁ

Rev

ÁÁÁ

ÁÁÁÁ

Read only

The revision (Rev) bits indicate the design revision of the core logic. For the TSB11LV01, Rev is set
to 01.

ÁÁÁÁÁ

ÁÁÁ

ÁÁÁÁÁ

RHB

ÁÁÁ

ÁÁÁÁ

ÁÁ

ÁÁÁÁ

Read/Write

When set, the root hold-off bit (RHB) instructs the local node to try to become the root during the
next bus reset. RHB is reset (0) during a hardware reset and is not affected by a bus reset.

ÁÁÁÁÁ

ÁÁÁ

ÁÁÁÁÁ

SPD

ÁÁÁ

ÁÁÁÁ

ÁÁ

ÁÁÁÁ

Read only

The speed (SPD) bits indicates the top signaling speed of the local port and for the TSB11LV01 is
set to 00.

TSB11LV01
3-V 1-PORT IEEE 1394-1995 CABLE TRANSCEIVER/ARBITER

SLLS232B MARCH 1996 REVISED MAY 1997

POST OFFICE BOX 655303

DALLAS, TEXAS 75265

PRINCIPLES OF OPERATION

The TSB11LV01 is designed to operate with a link layer controller such as the Texas Instruments TSB12C01A.
These devices use a direct-connect interface such as described in Annex J of the IEEE 1394-1995 standard.
Details of how the TSB12C01A (link) devices operates are described in the TSB12C01A data sheet. The
following paragraphs describes the operation of the phy-link interface.

The TSB11LV01 supports 100 Mbits/s data transfers, and has two bidirectional data lines (D0 and D1 ) crossing
the interface. In addition there are two bidirectional control lines (CTL0 and CTL1 ), the 50-MHz SYSCLK line
from the phy to the link, and the link request line (LREQ) from the link to the phy. The TSB11LV01 phy has control
of all the bidirectional terminals. The link is allowed to drive these terminals only after it has been given
permission by the phy. The dedicated LREQ request terminal is used by the link for any activity that it wishes
to initiate.

There are four operations that may occur in the phy-link interface: request, status, transmit, and receive. With
the exception of the request operation, all actions are initiated by the phy.

When the phy has control of the bus, the CTL0 and CTL1 lines are encoded as shown in Table 3.

Table 3. CTL Status When Phy Has Control of the Bus

ÁÁÁÁÁ

CTL0, CTL1

ÁÁÁÁ

Name

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Description of Activity

ÁÁÁÁÁ

ÁÁÁÁ

Idle

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

No activity is occurring (this is the default mode)

ÁÁÁÁÁ

ÁÁÁÁ

Status

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Status information is being sent from the phy to the link

ÁÁÁÁÁ

ÁÁÁÁ

Receive

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

An incoming packet is being sent from the phy to the link

ÁÁÁÁÁ

ÁÁÁÁ

Transmit

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

The link has been given control of the bus to send an outgoing packet

When the link has control of the bus (with phy permission), the CTL0 and CTL1 lines are encoded as shown
in Table 4.

Table 4. CTL Status When Link Has Control of the Bus

ÁÁÁÁÁ

CTL0, CTL1

ÁÁÁÁ

Name

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Description of Activity

ÁÁÁÁÁ

ÁÁÁÁ

Idle

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

The link releases the bus (transmission has been completed)

ÁÁÁÁÁ

ÁÁÁ

ÁÁÁÁÁ

ÁÁÁÁ

ÁÁ

ÁÁÁÁ

Hold

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

The link is holding the bus while data is being prepared for transmission or sending another
packet without arbitrating

ÁÁÁÁÁ

ÁÁÁÁ

Transmit

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

An outgoing packet is being sent from the link to the phy

ÁÁÁÁÁ

ÁÁÁÁ

Reserved

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

None

When the link wishes to request the bus or access a register that is located in the TSB11LV01 phy, a serial stream
of information is sent across the LREQ line. The length of the stream varies depending on whether the transfer
is a bus request, a read command, or a write command (see Table 5). Regardless of the type of transfer, a start
bit of 1 is required at the beginning of the stream, and a stop bit of 0 is required at the end of the stream. Bit 0
is the most significant, and is transmitted first. The LREQ terminal is required to idle low.

Table 5. Link Bus Request or Register Access Request Bit Length

ÁÁÁÁÁÁÁÁÁÁÁÁ

Request Type

ÁÁÁÁÁ

Number of Bits

ÁÁÁÁÁÁÁÁÁÁÁÁ

Bus Request

ÁÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁ

Read Register Request

ÁÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁ

Write Register Request

ÁÁÁÁÁ

TSB11LV01

3-V 1-PORT IEEE 1394-1995 CABLE TRANSCEIVER/ARBITER

SLLS232B MARCH 1996 REVISED MAY 1997

POST OFFICE BOX 655303

DALLAS, TEXAS 75265

PRINCIPLES OF OPERATION

For a Bus Request the length of the LREQ data stream is 7 bits and is shown in Table 6.

Table 6. Link Bus Request

ÁÁÁÁÁ

Bit(s)

ÁÁÁÁÁÁ

Name

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Description

ÁÁÁÁÁ

ÁÁÁÁÁÁ

Start Bit

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

This bit indicates the beginning of the transfer (always 1).

ÁÁÁÁÁ

ÁÁÁÁÁÁ

Request Type

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

These bits indicate the type of bus request (see Table 9 for the encoding of this field).

ÁÁÁÁÁ

ÁÁÁÁÁÁ

Request Speed

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

These bits should always be 00 for TSB11LV01 100 Mbits/s speed.

ÁÁÁÁÁ

ÁÁÁÁÁÁ

Stop Bit

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

This bit indicates the end of the transfer (always 0).

For a Read Register Request the length of the LREQ data stream is 9 bits and is shown in Table 7.

Table 7. Link Read Register Access

ÁÁÁÁÁ

Bit(s)

ÁÁÁÁÁÁ

Name

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Description

ÁÁÁÁÁ

ÁÁÁÁÁÁ

Start Bit

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

This bit indicates the beginning of the transfer (always 1).

ÁÁÁÁÁ

ÁÁÁÁÁÁ

Request Type

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

These bits are always 100 indicating that this is a read register request.

ÁÁÁÁÁ

ÁÁÁÁÁÁ

Address

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

These bits are the address of the phy register to be read.

ÁÁÁÁÁ

ÁÁÁÁÁÁ

Stop Bit

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

This bit indicates the end of the transfer (always 0).

For a Write Register Request the length of the LREQ data stream is 17 bits and is shown in Table 8.

Table 8. Link Write Register Access

ÁÁÁÁÁ

Bit(s)

ÁÁÁÁÁÁ

Name

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Description

ÁÁÁÁÁ

ÁÁÁÁÁÁ

Start Bit

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

This bit indicates the beginning of the transfer (always 1).

ÁÁÁÁÁ

ÁÁÁÁÁÁ

Request Type

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

These bits are always 101 indicating that this is a write register request.

ÁÁÁÁÁ

ÁÁÁÁÁÁ

Address

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

These bits are the address of the phy register to be written to.

ÁÁÁÁÁ

815

ÁÁÁÁÁÁ

Data

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

These bits are the data that is written to the specified register address.

ÁÁÁÁÁ

ÁÁÁÁÁÁ

Stop Bit

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

This bit indicates the end of the transfer (always 0).

The 3-bit Request Type fields are described in Table 9.

Table 9. Link Bus Request Type

ÁÁÁÁÁ

LREQ1 LREQ3

ÁÁÁÁÁÁ

Name

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Description

ÁÁÁÁÁ

000

ÁÁÁÁÁÁ

ImmReq

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Immediate request. When an idle is detected, take control of the bus immediately (no arbitration).

ÁÁÁÁÁ

001

ÁÁÁÁÁÁ

IsoReq

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Isochronous request. Arbitrate for the bus with no gaps.

ÁÁÁÁÁ

010

ÁÁÁÁÁÁ

PriReq

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Priority request. Arbitrate after a subaction gap and ignore fair protocol.

ÁÁÁÁÁ

011

ÁÁÁÁÁÁ

FairReq

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Fair request. Arbitrate after a subaction gap and use fair protocol.

ÁÁÁÁÁ

100

ÁÁÁÁÁÁ

RdReg

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Read register. Return the specified register contents through a status transfer

ÁÁÁÁÁ

101

ÁÁÁÁÁÁ

WrReg

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Write register. Write to the specified register.

ÁÁÁÁÁ

110, 111

ÁÁÁÁÁÁ

Reserved

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Reserved

TSB11LV01
3-V 1-PORT IEEE 1394-1995 CABLE TRANSCEIVER/ARBITER

SLLS232B MARCH 1996 REVISED MAY 1997

POST OFFICE BOX 655303

DALLAS, TEXAS 75265

PRINCIPLES OF OPERATION

request

LR0

LR1

LR2

LR3

LR(n-2)

LR(n-1)

NOTE A: Each cell in this timing diagram represents one clock sample time.

Figure 5. LREQ Timing

bus request

For fair or priority access, the link requests control of the bus at least one clock after the phy-link interface
becomes idle. If the link senses that the CTL terminals are in a receive state (CTL0 and CTL1 = 10), then it knows
that its request has been lost. This is true anytime during or after the link sends the bus request transfer on
LREQ. Additionally, the phy ignores any fair or priority requests if it asserts the receive state while the link is
requesting the bus. The link then reissues the request one clock after the next interface idle.

The cycle master uses a priority request to send a cycle start message. After receiving a cycle start, the link
can issue an isochronous bus request. When arbitration is won, the link proceeds with the isochronous transfer
of data. The phy clears an isochronous request only when the bus has been won. The isochronous request
register is cleared in the phy once the link sends another type of request or when the isochronous transfer has
been completed. The isochronous request must be issued during a packet reception. Usually this occurs during
the reception of a cycle start packet.

The ImmReq request is issued when the link needs to send an acknowledgment after reception of a packet
addressed to it. This request must be issued during packet reception. This is done to minimize the delays that
a phy would have to wait between the end of a packet and the transmittal of an acknowledgment. As soon as
the packet ends, the phy immediately grants access of the bus to the link. The link sends an acknowledgment
to the sender unless the header cyclic redundancy check (CRC) of the packet turns out to be bad. In this case,
the link releases the bus immediately; it is not allowed to send another type of packet on this grant. To ensure
another packet is not sent, the link is forced to wait 160 ns after the end of the packet is received. The phy then
gains control of the bus and the acknowledgment with the CRC error is sent. Then the bus is released and
allowed to proceed with another request.

Although highly improbable, it is conceivable that two separate nodes could believe that an incoming packet
is intended for them. The nodes then issue a ImmReq request before checking the CRC of the packet. Since
each phy seizes control of the bus at the same time, a temporary, localized collision of the bus occurs
somewhere between the competing nodes. This collision would be interpreted by the other nodes on the
network as being a ZZ line state and not a bus reset. As soon as the two nodes check the CRC, the mistaken
node drops its request and the false line state is removed. The only side effect would be the loss of the intended
acknowledgment packet (this is handled by the higher-layer protocol).

phy register read/write requests

When the link requests to read the specified register contents, the phy sends the contents of the register to the
link through a status transfer. If an incoming packet is received while the phy is transferring status information
to the link, the phy continues to attempt to transfer the contents of the register until it is successful.

For write requests, the phy loads the data field into the appropriately addressed register as soon as the transfer
has been completed. The link is allowed to request register read or write operations at any time.

TSB11LV01

3-V 1-PORT IEEE 1394-1995 CABLE TRANSCEIVER/ARBITER

SLLS232B MARCH 1996 REVISED MAY 1997

POST OFFICE BOX 655303

DALLAS, TEXAS 75265

PRINCIPLES OF OPERATION

status

A status transfer is initiated by the phy when it has status information to transfer to the link. The phy waits until
the interface is idle before starting the transfer. The transfer is initiated by asserting the following on the the
control terminals: CTL0 and CTL1 = 01 along with the first two bits of status information on the D0 and D1
terminals. The phy maintains CTL0 and CTL1 = 01 for the duration of status transfer. The phy may prematurely
end a status transfer by asserting something else other than CTL0 and CTL1 = 01 on the control terminals. This
could be caused by an incoming packet from another node. The phy continues to attempt to complete the
transfer until the information has been successfully transmitted. There must be at least one idle cycle in between
consecutive status transfers.

The phy normally sends just the first four bits of status to the link. These bits are status flags that are needed
by the link state machines. The phy sends an entire status packet to the link after a request transfer that contains
a read request, or when the phy has pertinent information to send to the link or transaction layers. The only
defined condition where the phy automatically sends a register to the link is after Self-ID, when it sends the
Physical-ID register, which contains the new node address.

The descriptions of the bits in the status transfer are listed in Table 10 and the timing is shown in Figure 6.

Table 10. Status Transfer Bit Description

ÁÁÁÁÁÁ

Bit(s)

ÁÁÁÁÁÁÁ

Name

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Description

ÁÁÁÁÁÁ

ÁÁÁÁ

ÁÁÁÁÁÁ

ÁÁÁÁÁÁÁ

ÁÁÁÁÁ

ÁÁÁÁÁÁÁ

Arbitration Reset Gap

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

This bit indicates that the phy has detected that the bus has been idle for an arbitration
reset gap time (this time is defined in the IEEE 1394-1995 standard). This bit is used by
the link in its busy/retry state machine.

ÁÁÁÁÁÁ

ÁÁÁÁ

ÁÁÁÁÁÁ

ÁÁÁÁÁÁÁ

ÁÁÁÁÁ

ÁÁÁÁÁÁÁ

Subaction Gap

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

This bit indicates that the phy has detected that the bus has been idle for a subaction gap
time (this time is defined in the IEEE 1394-1995 standard). This bit is used by the link to
detect the completion of an isochronous cycle.

ÁÁÁÁÁÁ

ÁÁÁÁÁÁÁ

Bus Reset

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

This bit indicates that the phy has entered the bus reset state.

ÁÁÁÁÁÁ

ÁÁÁÁ

ÁÁÁÁÁÁ

ÁÁÁÁÁÁÁ

ÁÁÁÁÁ

ÁÁÁÁÁÁÁ

CPS

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

This bit indicates that the cable power has dropped below the threshold for reliable op-
eration.

ÁÁÁÁÁÁ

ÁÁÁÁÁÁÁ

Address

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

These bits hold the address of the phy register whose contents are transferred to the link.

ÁÁÁÁÁÁ

815

ÁÁÁÁÁÁÁ

Data

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

These bits contain the data that is to be sent to the link.

Phy

CTL0, CTL1

S[0,1]

Phy

D0, D1

S[2,3]

S[14,15]

Figure 6. Status Transfer Timing

TSB11LV01
3-V 1-PORT IEEE 1394-1995 CABLE TRANSCEIVER/ARBITER

SLLS232B MARCH 1996 REVISED MAY 1997

POST OFFICE BOX 655303

DALLAS, TEXAS 75265

PRINCIPLES OF OPERATION

transmit

When the link wants to transmit information, it first requests access to the bus through the LREQ terminal. Once
the phy receives this request, it arbitrates to gain control of the bus. When the phy wins ownership of the serial
bus, it grants the bus to the link by asserting the transmit state on the CTL terminals for at least one SYSCLK
cycle. The link takes control of the bus by asserting either hold or transmit on the CTL lines. Hold is used by
the link to keep control of the bus when it needs some time to prepare the data for transmission. The phy keeps
control of the bus for the link by asserting a data-on state on the bus. It is not necessary for the link to use hold
when it is ready to transmit as soon as bus ownership is granted.

When the link is prepared to send data, it asserts transmit on the CTL lines as well as sending the first bits of
the packet on the D0 and D1 lines (assuming 100 Mbits/s). The transmit state is held on the CTL terminals until
the last bits of data have been sent. The link then asserts idle on the CTL lines for one clock cycle after which
it releases control of the interface.

However, there are times when the link needs to send another packet without releasing the bus. For example,
the link may want to send consecutive isochronous packets or it may want to attach a response to an
acknowledgment. To do this, the link asserts a hold instead of an idle when the first packet of data has been
completely transmitted. Hold, in this case, informs the phy that the link needs to send another packet without
releasing control of the bus. The phy then waits a set amount of time before asserting transmit. The link can
then proceed with the transmittal of the second packet. After all data has been transmitted and the link has
asserted idle on the CTL terminals, the phy asserts its own idle state on the CTL lines. When sending multiple
packets in this fashion, it is required that all data be transmitted at the same speed. This is required because
the transmission speed is set during arbitration and since the arbitration step is skipped, there is no way of
informing the network of a change in speed.

Phy

CTL0, CTL1

Phy

D0, D1

Link

CTL0, CTL1

Link

D0, D1

Single Packet

Phy

CTL0, CTL1

Continued Packet

Phy

D0, D1

Link

CTL0, CTL1

Link

D0, D1

Dn-1

NOTE A: ZZ = High Impedance State

D0 => Dn = Packet data

Figure 7. Transmit Timing Waveforms

TSB11LV01

3-V 1-PORT IEEE 1394-1995 CABLE TRANSCEIVER/ARBITER

SLLS232B MARCH 1996 REVISED MAY 1997

POST OFFICE BOX 655303

DALLAS, TEXAS 75265

PRINCIPLES OF OPERATION

receive

When data is received by the phy from the serial bus, the phy transfers the data to the link for further processing.
The phy asserts receive on the CTL lines and asserts each D terminal high. The phy indicates the start of the
packet by placing the speed code on the data bus. The phy then proceeds with the transmittal of the packet to
the link on the D lines while still keeping the receive status on the CTL terminals. Once the packet has been
completely transferred, the phy asserts idle on the CTL terminals, which completes the receive operation.

NOTE

The speed is a phy-link protocol and not included in the CRC.

Phy

CTL0, CTL1

SPD

Phy

D0, D1

NOTE A: SPD = Speed Code

D0 => Dn = Packet data

Figure 8. Receive Timing Waveforms

Table 11. Speed Code For the Receiver

ÁÁÁÁÁÁ

ÁÁÁÁ

ÁÁÁÁÁÁ

Speed Code

(D0, D1)

ÁÁÁÁÁÁ

ÁÁÁÁ

ÁÁÁÁÁÁ

Data Rate

ÁÁÁÁÁÁ

100 Mbits/s

power class bits in the Self-ID packet

Table 12 contains a description of each power class bit in the power field (bits 21, 22, and 23) of the Self-ID
packet.

Table 12. Self-ID Packet Power Field Bit Description

PC0 PC2

Description

000

Node does not need power and does not repeat power.

001

Node is self powered and provides a minimum of 15 W to the bus.

010

Node is self powered and provides a minimum of 30 W to the bus.

011

Node is self powered and provides a minimum of 45 W to the bus.

100

Node may be powered from the bus and is using up to 1 W.

101

Node may be powered from the bus and is using up to 1 W. An additional 2 W is needed to enable the link and higher layers.

110

Node may be powered from the bus and is using up to 1 W. An additional 5 W is needed to enable the link and higher layers.

111

Node may be powered from the bus and is using up to 1 W. An additional 9 W is needed to enable the link and higher layers.

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Part Number TSB11LV01