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Part Number TPIC1321L

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TPIC1321L
3-HALF H-BRIDGE GATE-PROTECTED LOGIC-LEVEL
POWER DMOS ARRAY
SLIS042 ­ NOVEMBER 1994
Copyright
©
1994, Texas Instruments Incorporated
2­1
POST OFFICE BOX 655303
·
DALLAS, TEXAS 75265
·
Low r
DS(on)
. . . 0.35
Typ
·
Voltage Output . . . 60 V
·
Input Protection Circuitry . . . 18 V
·
Pulsed Current . . . 4 A Per Channel
·
Extended ESD Capability . . . 4000 V
·
Direct Logic-Level Interface
description
The TPIC1321L is a monolithic gate-protected
logic-level power DMOS array that consists of six
electrically isolated N-channel enhancement-
mode DMOS transistors configured as 3-half
H-bridges. Each transistor features integrated
high-current zener diodes (Z
CXa
and Z
CXb
) to
prevent gate damage in the event that an overstress condition occurs. These zener diodes also provide up to
4000 V of ESD protection when tested using the human-body model of a 100-pF capacitor in series with a 1.5-k
resistor.
The TPIC1321L is offered in a 24-pin wide-body surface-mount (DW) package and is characterized for
operation over the case temperature of ­ 40
°
C to 125
°
C.
schematic
D1
DRAIN3
D3
Z1
Z3
Z4
Z6
GND
GATE3
GATE6
OUTPUT3
DRAIN1
GATE1
OUTPUT1
GATE4
Q1
Q4
Q6
Q3
D2
Z2
Z5
Q2
Q5
SOURCE6
SOURCE4
OUTPUT2
GATE5
GATE2
DRAIN2
14, 15
21, 22
23
1, 24
2
3, 4
13
11, 12
10
8, 9
5, 6
19, 20
16
17, 18
7
D4
D5
NOTE A: For correct operation, no terminal may be taken below GND.
ZC1b
ZC1a
ZC4b
ZC4a
ZC2b
ZC2a
ZC5b
ZC5a
ZC3b
ZC3a
ZC6b
ZC6a
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
OUTPUT1
GATE4
SOURCE4
SOURCE4
GND
GND
GATE5
SOURCE6
SOURCE6
GATE6
OUTPUT3
OUTPUT3
OUTPUT1
GATE1
DRAIN1
DRAIN1
DRAIN2
DRAIN2
OUTPUT2
OUTPUT2
GATE2
DRAIN3
DRAIN3
GATE3
DW PACKAGE
(TOP VIEW)
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
TPIC1321L
3-HALF H-BRIDGE GATE-PROTECTED LOGIC-LEVEL
POWER DMOS ARRAY
SLIS042 ­ NOVEMBER 1994
2­2
POST OFFICE BOX 655303
·
DALLAS, TEXAS 75265
absolute maximum ratings over operating case temperature range (unless otherwise noted)
Drain-to-source voltage, V
DS
60 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output-to-GND voltage
60 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Drain-to-GND voltage
100 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SOURCE4, SOURCE6-to-GND voltage
60 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Gate-to-source voltage range, V
GS
­ 9 V to 18 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous drain current, each output, T
C
= 25
°
C
1.25 A
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous source-to-drain diode current, T
C
= 25
°
C
1.25 A
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Pulsed drain current, each output, I
max
, T
C
= 25
°
C (see Note 1 and Figure 15)
4 A
. . . . . . . . . . . . . . . . . . . . .
Continuous gate-to-source zener-diode current, T
C
= 25
°
C
±
50 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Pulsed gate-to-source zener-diode current, T
C
= 25
°
C
±
500 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Single-pulse avalanche energy, E
AS,
T
C
= 25
°
C (see Figures 4 and 16)
96 mJ
. . . . . . . . . . . . . . . . . . . . . . . . .
Continuous total dissipation, T
C
= 25
°
C (see Figure 15)
1.39 W
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating virtual junction temperature range, T
J
­ 40
°
C to 150
°
C
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating case temperature range, T
C
­ 40
°
C to 125
°
C
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range
­ 65
°
C to 150
°
C
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds
260
°
C
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: Pulse duration = 10 ms, duty cycle = 2%
TPIC1321L
3-HALF H-BRIDGE GATE-PROTECTED LOGIC-LEVEL
POWER DMOS ARRAY
SLIS042 ­ NOVEMBER 1994
2­3
POST OFFICE BOX 655303
·
DALLAS, TEXAS 75265
electrical characteristics, T
C
= 25
°
C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
V(BR)DSX Drain-to-source breakdown voltage
ID = 250
µ
A,
VGS = 0
60
V
VGS(th)
Gate-to-source threshold voltage
ID = 1 mA,
See Figure 5
VDS = VGS,
1.5
1.75
2.2
V
V(BR)GS
Gate-to-source breakdown voltage
IGS = 250
µ
A
18
V
V(BR)SG
Source-to-gate breakdown voltage
ISG = 250
µ
A
9
V
V(BR)
Reverse drain-to-GND breakdown voltage
(across D1 , D2, D3, D4, D5)
Drain-to-GND current = 250
µ
A
100
V
VDS(on)
Drain-to-source on-state voltage
ID = 1.25 A,
See Notes 2 and 3
VGS = 5 V,
0.44
0.5
V
VF(SD)
Forward on-state voltage, source-to-drain
IS = 1.25 A,
VGS = 0 (Z1 ­ Z6),
See Notes 2 and 3 and Figure 12
0.9
1.1
V
VF
Forward on-state voltage, GND-to-drain
ID = 1.25 A (D1 ­ D5)
See Notes 2 and 3
4
V
IDSS
Zero gate voltage drain current
VDS = 48 V,
TC = 25
°
C
0.05
1
µ
A
IDSS
Zero-gate-voltage drain current
DS
,
VGS = 0
TC = 125
°
C
0.5
10
µ
A
IGSSF
Forward-gate current, drain short circuited to source
VGS = 15 V,
VDS = 0
20
200
nA
IGSSR
Reverse-gate current, drain short circuited to source
VSG = 5 V,
VDS = 0
10
100
nA
Ilk
Leakage current drain to GND
VDGND = 48 V
TC = 25
°
C
0.05
1
µ
A
Ilkg
Leakage current, drain-to-GND
VDGND = 48 V
TC = 125
°
C
0.5
10
µ
A
rDS( )
Static drain to source on state resistance
VGS = 5 V,
ID = 1.25 A,
TC = 25
°
C
0.35
0.4
rDS(on)
Static drain-to-source on-state resistance
D
,
See Notes 2 and 3
and Figures 6 and 7
TC = 125
°
C
0.57
0.6
gfs
Forward transconductance
VDS = 15 V,
ID = 625 mA,
See Notes 2 and 3 and Figure 9
1.6
1.74
S
Ciss
Short-circuit input capacitance, common source
200
250
Coss
Short-circuit output capacitance, common source
VDS = 25 V,
VGS = 0,
175
220
pF
Crss
Short-circuit reverse-transfer capacitance,
common source
f = 1 MHz,
See Figure 11
40
75
F
NOTES:
2. Technique should limit TJ ­ TC to 10
°
C maximum.
3. These parameters are measured with voltage-sensing contacts separate from the current-carrying contacts.
source-to-drain and GND-to-drain diode characteristics, T
C
= 25
°
C
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
trr
Reverse-recovery time
IS = 625 mA,
VGS 0
VDS = 48 V,
di/dt
100 A/
µ
s
Z1 Z2 and Z3
45
ns
QRR
Total diode charge
VGS = 0,
See Figures 1 and 14
di/dt = 100 A/
µ
s,
Z1, Z2, and Z3
50
nC
TPIC1321L
3-HALF H-BRIDGE GATE-PROTECTED LOGIC-LEVEL
POWER DMOS ARRAY
SLIS042 ­ NOVEMBER 1994
2­4
POST OFFICE BOX 655303
·
DALLAS, TEXAS 75265
resistive-load switching characteristics, T
C
= 25
°
C
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
td(on)
Turn-on delay time
34
70
td(off)
Turn-off delay time
VDD = 25 V,
RL = 40
,
ten = 10 ns,
80
150
ns
tr
Rise time
DD
,
tdis = 10 ns,
L
,
See Figure 2
en
,
28
55
ns
tf
Fall time
15
30
Qg
Total gate charge
V
48 V
I
625
A
V
5 V
4.6
5.8
Qgs(th) Threshold gate-to-source charge
VDS = 48 V,
See Figure 3
ID = 625 mA,
VGS = 5 V,
0.7
0.88
nC
Qgd
Gate-to-drain charge
See Figure 3
2.5
3.13
LD
Internal drain inductance
5
nH
LS
Internal source inductance
5
nH
Rg
Internal gate resistance
0.25
thermal resistance
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
R
JA
Junction-to-ambient thermal resistance
See Notes 4 and 7
90
R
JB
Junction-to-board thermal resistance
See Notes 5 and 7
44.5
°
C/W
R
JP
Junction-to-pin thermal resistance
See Notes 6 and 7
28
NOTES:
4. Package mounted on an FR4 printed-circuit board with no heatsink.
5. Package mounted on a 24 in2, 4-layer FR4 printed-circuit board.
6. Package mounted in intimate contact with infinite heatsink.
7. All outputs with equal power
TPIC1321L
3-HALF H-BRIDGE GATE-PROTECTED LOGIC-LEVEL
POWER DMOS ARRAY
SLIS042 ­ NOVEMBER 1994
2­5
POST OFFICE BOX 655303
·
DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
trr(SD)
­ Source-to-Drain Diode Current ­
A
I S
1
0.5
0
­ 0.5
­ 1
­ 1.5
­ 2
­ 2.5
1.5
Reverse di/dt = 100 A/
µ
s
25% of IRM
IRM
IRM = maximum recovery current
Time ­ ns
0
50
100
150
200
250
300
350
400
450
500
Shaded Area = QRR
VDS = 48 V
VGS = 0
TJ = 25
°
C
Z1, Z2, and Z3
Figure 1. Reverse-Recovery-Current Waveform of Source-to-Drain Diode
Pulse Generator
50
Rgen
50
VGS
VDD = 25 V
DUT
VDS
TEST CIRCUIT
VDD
VDS(on)
tf
td(on)
tr
td(off)
VOLTAGE WAVEFORMS
VGS
VDS
RL
CL = 30 pF
(see Note A)
tdis
ten
5 V
0 V
NOTE A: CL includes probe and jig capacitance.
Figure 2. Resistive-Switching Test Circuit and Voltage Waveforms