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FEATURES

TMS470R1A128

16/32-Bit RISC Flash Microcontrollers

SPNS098 JANUARY 2005

Asynchronous/Isosynchronous Modes

High-Performance Static CMOS Technology

 Standard CAN Controller (SCC)

TMS470R1x 16/32-Bit RISC Core

16-Mailbox Capacity

(ARM7TDMITM)

Fully Compliant with CAN Protocol,

 28-MHz System Clock (48-MHz Pipeline

Version 2.0B

Mode)

 Class II Serial Interface (C2SIa)

 Independent 16/32-Bit Instruction Set

Two Selectable Data Rates

 Open Architecture With Third-Party Support

Normal Mode 10.4 Kbps and 4X Mode 41.6

 Built-In Debug Module

Kbps

 Big-Endian Format Utilized

High-End Timer (HET)

Integrated Memory

 16 Programmable I/O Channels:

 128K-Byte Program Flash

14 High-Resolution Pins

One Bank With Ten Contiguous Sectors

2 Standard-Resolution Pins

Internal State Machine for Programming

 High-Resolution Share Feature (XOR)

and Erase

 HET RAM (64-Instruction Capacity)

 8K-Byte Static RAM (SRAM)

10-Bit Multi-Buffered ADC (MibADC)

Operating Features

16-Channel

 Core Supply Voltage (V

): 1.81 V2.05 V

 64-Word FIFO Buffer

 I/O Supply Voltage (V

CCIO

): 3.0 V3.6 V

 Single- or Continuous-Conversion Modes

 Low-Power Modes: STANDBY and HALT

 1.55 µs Minimum Sample and Conversion

Time

 Industrial Temperature Range

 Calibration Mode and Self-Test Features

470+ System Module

Eight External Interrupts

 32-Bit Address Space Decoding

Flexible Interrupt Handling

 Bus Supervision for Memory and

Peripherals

11 Dedicated GIO Pins, 1 Input-Only GIO Pin,
and 38 Additional Peripheral I/Os

 Analog Watchdog (AWD) Timer

External Clock Prescale (ECP) Module

 Real-Time Interrupt (RTI)

 Programmable Low-Frequency External

 System Integrity and Failure Detection

Clock (CLK)

Zero-Pin Phase-Locked Loop (ZPLL)-Based

On-Chip Scan-Base Emulation Logic, IEEE

Clock Module With Prescaler

Standard 1149.1

(1)

(JTAG) Boundary-Scan

 Multiply-by-4 or -8 Internal ZPLL Option

Logic

 ZPLL Bypass Mode

100-Pin Plastic Low-Profile Quad Flatpack (PZ

Six Communication Interfaces:

Suffix)

 Two Serial Peripheral Interfaces (SPIs)

255 Programmable Baud Rates

(1)

The test-access port is compatible with the IEEE Standard

 Two Serial Communications Interfaces

1149.1-1990, IEEE Standard Test-Access Port and Boundary

(SCIs)

Scan Architecture. Boundary scan is not supported on this

Selectable Baud Rates

device.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

ARM7TDMI is a trademark of Advanced RISC Machines (ARM) Limited.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.

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100

75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51

10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25

ADIN[11]

ADIN[14]

ADIN[10]

ADIN[13]

ADIN[9]

ADIN[12]

REFHI

REFLO

CCAD

SSAD

TMS

TMS2

HET[0]

FLTP2

FLTP1

CCP

HET[2]

HET[4]

HET[6]

HET[7]

AWD

HET[18]

HET[20]

HET[21]

SPI2SCS

SPI2ENA

SPI2SOMI

SPI2SIMO

SPI2CLK

C2SIaRX

C2SIaTX

C2SIaLPN

HET[24]

HET[31]

SCI2TX

SCI2RX

GIOA[3]/INT3

GIOA[2]/INT2

GIOA[1]/INT1/ECLK

GIOA[0]/INT0

(A)

TEST

TRST

ADIN[8]

HET[19]

TMS470R1A128
16/32-Bit RISC Flash Microcontrollers

SPNS098 JANUARY 2005

TMS470R1A128 100-Pin PZ Package (Top View)

GIOA[0]/INT0 (pin 28) is an input-only GIO pin.

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DESCRIPTION

TMS470R1A128

16/32-Bit RISC Flash Microcontrollers

SPNS098 JANUARY 2005

The TMS470R1A128

(1)

devices are members of the Texas Instruments (TI) TMS470R1x family of gen-

eral-purpose16/32-bit reduced instruction set computer (RISC) microcontrollers. The A128 microcontroller offers
high performance utilizing the high-speed ARM7TDMI 16/32-bit RISC central processing unit (CPU), resulting in
a high instruction throughput while maintaining greater code efficiency. The ARM7TDMI 16/32-bit RISC CPU
views memory as a linear collection of bytes numbered upwards from zero. The TMS470R1A128 utilizes the
big-endian format, where the most significant byte of a word is stored at the lowest numbered byte and the least
significant byte at the highest numbered byte.

High-end embedded control applications demand more performance from their controllers while maintaining low
costs. The A128 RISC core architecture offers solutions to these performance and cost demands while
maintaining low power consumption.

The A128 devices contain the following:

ARM7TDMI 16/32-Bit RISC CPU

TMS470R1x system module (SYS) with 470+ enhancements

128K-byte Flash

8K-byte SRAM

Zero-pin phase-locked loop (ZPLL) clock module

Analog watchdog (AWD) timer

Real-time interrupt (RTI) module

Two serial peripheral interface (SPI) modules

Two serial communications interface (SCI) modules

Standard CAN controller (SCC)

Class II serial interface (C2SIa)

10-bit, 16-input channel multi-buffered analog-to-digital converter (MibADC)

High-end timer (HET) controlling 16 I/Os (A128)

External Clock Prescale (ECP)

Up to 49 I/O pins and 1 input-only pin

The functions performed by the 470+ system module (SYS) include:

Address decoding

Memory protection

Memory and peripherals bus supervision

Reset and abort exception management

Prioritization for all internal interrupt sources

Device clock control

Parallel signature analysis (PSA)

This data sheet includes device-specific information such as memory and peripheral select assignment, interrupt
priority, and a device memory map. For a more detailed functional description of the SYS module, see the
TMS470R1x System Module Reference Guide (literature number SPNU189).

The A128 memory includes general-purpose SRAM supporting single-cycle read/write accesses in byte,
halfword, and word modes.

The Flash memory on the A128 devices is a nonvolatile, electrically erasable and programmable memory
implemented with a 32-bit-wide data bus interface.The Flash operates with a system clock frequency of up to 28
MHz. In pipeline mode, the Flash operates with a system clock frequency of up to 48 MHz. For more detailed
information on the Flash, see the F05Flash section of this data sheet and the TMS470R1x F05 Flash Reference
Guide (literature number SPNU213).

(1)

Throughout the remainder of this document, the TMS470R1A128 device name will be referred to as either the full device name,
TMS470R1A128, or as A128.

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TMS470R1A128
16/32-Bit RISC Flash Microcontrollers

SPNS098 JANUARY 2005

The A128 devices have six communication interfaces: two SPIs, two SCIs, an SCC, and a C2SIa. The SPI
provides a convenient method of serial interaction for high-speed communications between similar shift-register
type devices. The SCI is a full-duplex, serial I/O interface intended for asynchronous communication between the
CPU and other peripherals using the standard non-return-to-zero (NRZ) format. The SCC uses a serial,
multimaster communication protocol that efficiently supports distributed real-time control with robust communi-
cation rates of up to 1 megabit per second (Mbps). The SCC is ideal for applications operating in noisy and
harsh environments (e.g., automotive and industrial fields) that require reliable serial communication or
multiplexed wiring. The C2SIa allows the A128 to transmit and receive messages on a class II network following
an SAE J1850 standard.

(2)

For more detailed functional information on the C2SIa peripheral, see the TMS470R1x Class II Serial Interface
(C2SIa) Reference Guide (literature number SPNU218).

The HET is an advanced intelligent timer that provides sophisticated timing functions for real-time applications.
The timer is software-controlled, using a reduced instruction set, with a specialized timer micromachine and an
attached I/O port. The HET can be used for compare, capture, or general-purpose I/O. It is especially well suited
for applications requiring multiple sensor information and drive actuators with complex and accurate time pulses.
For more detailed functional information on the HET, see the TMS470R1x High-End Timer (HET) Reference
Guide (literature number SPNU199).

The A128 devices have a 10-bit-resolution sample-and-hold MibADC. The MibADC channels can be converted
individually or can be grouped by software for sequential conversion sequences. There are three separate
groupings, two of which are triggerable by an external event. Each sequence can be converted once when
triggered or configured for continuous conversion mode. For more detailed functional information on the MibADC,
see the TMS470R1x Multi-Buffered Analog-to-Digital Converter (MibADC) Reference Guide (literature number
SPNU206).

The zero-pin phase-locked loop (ZPLL) clock module contains a phase-locked loop, a clock-monitor circuit, a
clock-enable circuit, and a prescaler (with prescale values of 18). The function of the ZPLL is to multiply the
external frequency reference to a higher frequency for internal use. The ZPLL provides ACLK to the system
(SYS) module. The SYS module subsequently provides system clock (SYSCLK), real-time interrupt clock
(RTICLK), CPU clock (MCLK), and peripheral interface clock (ICLK) to all other A128 device modules. For more
detailed functional information on the ZPLL, see the TMS470R1x Zero-Pin Phase-Locked Loop (ZPLL) Clock
Module Reference Guide (literature number SPNU212).

NOTE:

ACLK should not be confused with the MibADC internal clock, ADCLK. ACLK is the
continuous system clock from an external resonator/crystal reference.

The A128 devices also have an external clock prescaler (ECP) module that when enabled, outputs a continuous
external clock (ECLK) on a specified GIO pin. The ECLK frequency is a user-programmable ratio of the
peripheral interface clock (ICLK) frequency. For more detailed functional information on the ECP, see the
TMS470R1x External Clock Prescaler (ECP) Reference Guide (literature number SPNU202).

(2)

SAE Standard J1850 Class B Data Communication Network Interface

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device characteristics

TMS470R1A128

16/32-Bit RISC Flash Microcontrollers

SPNS098 JANUARY 2005

The TMS470R1A128 devices are a derivative of the F05 system emulation device SE470R1VB8AD. Table 1
identifies all the characteristics of the TMS470R1A128 devices except the SYSTEM and CPU, which are generic.

Table 1. Device Characteristics

CHARACTERISTICS

DEVICE DESCRIPTION

COMMENTS

MEMORY

For the number of memory selects on this device, see the "Memory Selection Assignment" table, Table 3.

Flash is pipeline-capable.

INTERNAL

128K-Byte Flash

The A128 RAM is implemented in one 8K array selected by two

MEMORY

8K-Byte SRAM

memory-select signals (see the "Memory Selection Assignment"
table, Table 3).

PERIPHERALS

For the device-specific interrupt priority configurations, see the Interrupt Priority table ( Table 6). For the 1K peripheral address ranges and
their peripheral selects, see the "A128 Peripherals, System Module, and Flash Base Addresses" table, Table 5).

CLOCK

ZPLL Zero-pin PLL has no external loop filter pins.

GENERAL-PURPOSE

11 I/O

For A128, Port A has 8 external pins, and Port B has 4 external pins.

I/Os

1 Input only

ECP

YES

C2SIa

1 (3-pin)

SCI2 has no external clock pin, only transmit/receive pins (SCI2TX

SCI

1 (2-pin)

and SCI2RX).

CAN

Standard CAN controller

1 SCC

(HECC and/or SCC)

SPI

2 (5-pin)

(5-pin, 4-pin or 3-pin)

The A128 devices have both the logic and registers for a full 32-I/O
HET implemented, even though not all 32 pins are available
externally.

The high-resolution (HR) SHARE feature allows even HR pins to
share the next higher odd HR pin structures. This HR sharing is

HET with XOR Share

16 I/O

independent of whether or not the odd pin is available externally. If an
odd pin is available externally and shared, then the odd pin can only
be used as a general-purpose I/O. For more information on HR
SHARE, see the TMS470R1x High-End Timer (HET) Reference
Guide (literature number SPNU199).

HET RAM

64-Instruction Capacity

10-bit, 16-channel

MibADC

Both the logic and registers for a full 16-channel MibADC are present.

64-word FIFO

CORE VOLTAGE

1.812.05 V

I/O VOLTAGE

3.03.6 V

PINS

100

PACKAGE

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ZPLL

MibADC

with

64-Word

FIFO

PLLDIS

OSCOUT

ADIN[15:0]

ADEVT

ADREFLO

ADREFHI

SPI2

SCI1

SCC

VSSAD

HET[31,24,21:18,

CANSRX

CANSTX

SCI1TX

SCI1CLK

VCCAD

RAM

(8K Bytes)

TMS470R1x

CPU

CPU Address/Data Bus

TMS470R1x 470+ SYSTEM MODULE

OSCIN

External Pins

VCCP

FLTP1

FLTP2

TCK

TMS

TDO

TDI

TRST

AWD

RST

TMS2

PORRST

CLKOUT

C2SIa

C2SIaTX

C2SIaLPN

C2SIaRX

SCI1RX

External Pins

SPI1

GIO

TEST

GIOA[1]/INT[1]/

ECP

ECLK

SCI2

SCI2TX

SCI2RX

GIOA[0]/INT[0]

GIOA[7:2]/INT[7:2]

GIOB[3:0]

(A)

SPI2SCS

SPI2ENA

SPI2SIMO

SPI2SOMI

SPI2CLK

SPI1SCS

SPI1ENA

SPI1SIMO

SPI1SOMI

SPI1CLK

Crystal

Expansion

Address/Data Bus

13:10,8:6,4,2,0]

FLASH

128 K-Bytes

(10 Sectors)

HET with

XOR Share

(64-Word)

TMS470R1A128
16/32-Bit RISC Flash Microcontrollers

SPNS098 JANUARY 2005

functional block diagram

GIOA[0]/INT[0] is an input-only GIO pin.

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TMS470R1A128

16/32-Bit RISC Flash Microcontrollers

SPNS098 JANUARY 2005

Table 2. Terminal Functions

TERMINAL

INTERNAL

TYPE

(1) (2)

PULLUP/

DESCRIPTION

PIN

NAME

PULLDOWN

(3)

NUMBER

HIGH-END TIMER (HET)

HET[0]

HET[2]

HET[4]

The A128 devices have both the logic and registers for a full 32-I/O HET

HET[6]

implemented, even though not all 32 pins are available externally.

HET[7]

100

Timer input capture or output compare. The HET[31:0] applicable pins

HET[8]

can be programmed as general-purpose input/output (GIO) pins.

HET[10]

HET[21:18, 13:10, 8, 7, 6, 4, 2, 0] are high-resolution pins and HET[31,
24] are standard-resolution pins for A128.

HET[11]

3.3-V I/O

IPD

The high-resolution (HR) SHARE feature allows even HR pins to share

HET[12]

the next higher odd HR pin structures. This HR sharing is independent of

HET[13]

whether or not the odd pin is available externally. If an odd pin is

HET[18]

available externally and shared, then the odd pin can only be used as a
general-purpose I/O.

HET[19]

For more information on HR SHARE, see the TMS470R1x High-End

HET[20]

Timer Reference Guide (literature number SPNU199).

HET[21]

HET[24]

HET[31]

STANDARD CAN CONTROLLER (SCC)

CANSRX

3.3-V I/O

SCC receive pin or GIO pin

CANSTX

3.3-V I/O

IPU

SCC transmit pin or GIO pin

CLASS II SERIAL INTERFACE (C2SIa)

C2SIaLPN

3.3-V 1/O

IPD

C2SIa module loopback enable pin or GIO pin

C2SIaRX

3.3-V I/O

C2SIa module receive data input pin or GIO pin

C2SIaTX

3.3-V I/O

IPD

C2SIa module transmit data input pin or GIO pin

(1)

I = input, O = output, PWR = power, GND = ground, REF = reference voltage, NC = no connect

(2)

All I/O pins, except RST, are configured as inputs while PORRST is low and immediately after PORRST goes high.

(3)

IPD = internal pulldown, IPU = internal pullup (all internal pullups and pulldowns are active on input pins, independent of the PORRST
state.)

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TMS470R1A128
16/32-Bit RISC Flash Microcontrollers

SPNS098 JANUARY 2005

Table 2. Terminal Functions (continued)

TERMINAL

INTERNAL

TYPE

(1) (2)

PULLUP/

DESCRIPTION

PIN

NAME

PULLDOWN

(3)

NUMBER

GENERAL-PURPOSE I/O (GIO)

GIOA[0]/

3.3-V I

INT0

GIOA[1]/

INT1/ECL
K

GIOA[2]/

INT2

GIOA[3]/

INT3

General-purpose input/output pins.

GIOA[4]/

GIOA[0]/INT[0] is an input-only pin. GIOA[7:0]/INT[7:0] are inter-

INT4

IPD

rupt-capable pins.

GIOA[5]/

3.3-V I/O

GIOA[1]/INT[1]/ECLK pin is multiplexed with the external clock-out

INT5

function of the external clock prescale (ECP) module.

GIOA[6]/

INT6

GIOA[7]/

INT7

GIOB[0]

GIOB[1]

GIOB[2]

GIOB[3]

MULTI-BUFFERED ANALOG-TO-DIGITAL CONVERTER (MibADC)

ADEVT

3.3-V I/O

IPD

MibADC event input. ADEVT can be programmed as a GIO pin.

ADIN[0]

ADIN[1]

ADIN[2]

ADIN[3]

ADIN[4]

ADIN[5]

ADIN[6]

16-channel MibADC.

ADIN[7]

3.3-V I

ADIN[8]

MibADC analog input pins

ADIN[9]

ADIN[10]

ADIN[11]

ADIN[12]

ADIN[13]

ADIN[14]

ADIN[15]

REFHI

3.3-V

MibADC module high-voltage reference input

REF I

REFLO

GND

MibADC module low-voltage reference input

REF I

CCAD

3.3-VPWR

MibADC analog supply voltage

SSAD

GND

MibADC analog ground reference

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TMS470R1A128

16/32-Bit RISC Flash Microcontrollers

SPNS098 JANUARY 2005

Table 2. Terminal Functions (continued)

TERMINAL

INTERNAL

TYPE

(1) (2)

PULLUP/

DESCRIPTION

PIN

NAME

PULLDOWN

(3)

NUMBER

SERIAL PERIPHERAL INTERFACE 1 (SPI1)

SPI1CLK

SPI1 clock. SPI1CLK can be programmed as a GIO pin.

SPI1ENA

SPI1 chip enable. SPI1ENA can be programmed as a GIO pin.

SPI1SCS

SPI1 slave chip select. SPI1SCS can be programmed as a GIO pin.

3.3-V I/O

IPD

SPI1SIMO

SPI1 data stream. Slave in/master out. SPI1SIMO can be programmed as
a GIO pin.

SPI1SOMI

SPI1 data stream. Slave out/master in. SPI1SOMI can be programmed as
a GIO pin.

SERIAL PERIPHERAL INTERFACE 2 (SPI2)

SPI2CLK

SPI2 clock. SPI2CLK can be programmed as a GIO pin.

SPI2ENA

SPI2 chip enable. SPI2ENA can be programmed as a GIO pin.

SPI2SCS

SPI2 slave chip select. SPI2SCS can be programmed as a GIO pin.

3.3-V I/O

IPD

SPI2SIMO

SPI2 data stream. Slave in/master out. SPI2SIMO can be programmed as
a GIO pin.

SPI2SOMI

SPI2 data stream. Slave out/master in. SPI2SOMI can be programmed as
a GIO pin.

ZERO-PIN PHASE-LOCKED LOOP (ZPLL)

OSCIN

1.8-V I

Crystal connection pin or external clock input

OSCOUT

1.8-V O

External crystal connection pin

Enable/disable the ZPLL. The ZPLL can be bypassed and the oscillator
becomes the system clock. If not in bypass mode, TI recommends that

PLLDIS

3.3-V I

IPD

PLLDIS be connected to ground or pulled down to ground by an external
resistor.

SERIAL COMMUNICATIONS INTERFACE 1 (SCI1)

SCI1CLK

3.3-V I/O

IPD

SCI1 clock. SCI1CLK can be programmed as a GIO pin.

SCI1RX

3.3-V I/O

IPU

SCI1 data receive. SCI1RX can be programmed as a GIO pin.

SCI1TX

3.3-V I/O

IPU

SCI1 data transmit. SCI1TX can be programmed as a GIO pin.

SERIAL COMMUNICATIONS INTERFACE 2 (SCI2)

SCI2RX

3.3-V I/O

IPU

SCI2 data receive. SCI2RX can be programmed as a GIO pin.

SCI2TX

3.3-V I/O

IPU

SCI2 data transmit. SCI2TX can be programmed as a GIO pin.

SYSTEM MODULE (SYS)

Bidirectional pin. CLKOUT can be programmed as a GIO pin or the

CLKOUT

3.3-V I/O

IPD

output of SYSCLK, ICLK, or MCLK.

Input master chip power-up reset. External V

monitor circuitry must

PORRST

3.3-V I

IPD

assert a power-on reset.

Bidirectional reset. The internal circuitry can assert a reset, and an
external system reset can assert a device reset.

On RST, the output buffer is implemented as an open drain (drives low

RST

3.3-V I/O

IPU

only).

To ensure an external reset is not arbitrarily generated, TI recommends
that an external pullup resistor be connected to RST .

WATCHDOG/REAL-TIME INTERRUPT (WD/RTI)

Analog watchdog reset. The AWD pin provides a system reset if the WD
KEY is not written in time by the system, providing an external RC
network circuit is connected. If the user is not using AWD, TI rec-
ommends that AWD be connected to ground or pulled down to ground by
an external resistor.

AWD

3.3-V I/O

IPD

For more details on the external RC network circuit, see the TMS470R1x
System Module Reference Guide (literature number SPNU189) and the
application note Analog Watchdog Resistor, Capacitor and Discharge
Interval Selection Constraints (literature number SPNA005).

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TMS470R1A128
16/32-Bit RISC Flash Microcontrollers

SPNS098 JANUARY 2005

Table 2. Terminal Functions (continued)

TERMINAL

INTERNAL

TYPE

(1) (2)

PULLUP/

DESCRIPTION

PIN

NAME

PULLDOWN

(3)

NUMBER

TEST/DEBUG (T/D)

TCK

3.3-V I

IPD

Test clock. TCK controls the test hardware (JTAG).

Test data in. TDI inputs serial data to the test instruction register, test

TDI

3.3-V I

IPU

data register, and programmable test address (JTAG).

Test data out. TDO outputs serial data from the test instruction register,

TDO

3.3-V O

IPD

test data register, identification register, and programmable test address
(JTAG).

Test enable. Reserved for internal use only. TI recommends that TEST

TEST

3.3-V I

IPD

be connected to ground or pulled down to ground by an external resistor.

Serial input for controlling the state of the CPU test access port (TAP)

TMS

3.3-V I

IPU

controller (JTAG).

Serial input for controlling the second TAP. TI recommends that TMS2 be

TMS2

3.3-V I

IPU

connected to V

CCIO

or be pulled up to V

CCIO

by an external resistor.

Test hardware reset to TAP1 and TAP2. IEEE Standard 1149-1 (JTAG)

TRST

3.3-V I

IPD

Boundary-Scan Logic. TI recommends that TRST be pulled down to
ground by an external resistor.

FLASH

FLTP1

Flash test pads 1 and 2. For proper operation, these pins must not be

connected (no connect [NC]).

FLTP2

CCP

3.3-V PWR

Flash external pump voltage (3.3 V)

SUPPLY VOLTAGE CORE (1.8 V)

1.8-VPWR

Core logic supply voltage

SUPPLY VOLTAGE DIGITAL I/O (3.3 V)

CCIO

3.3-VPWR

Digital I/O supply voltage

SUPPLY GROUND CORE

GND

Core supply ground reference

SUPPLY GROUND DIGITAL I/O

SSIO

GND

Digital I/O supply ground reference

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DEVICE-SPECIFIC INFORMATION

memory

0xFFFF_FFFF

System Module Control Registers

(512K Bytes)

Exception, Interrupt, and

Reset Vectors

Memory (4G Bytes)

Program

and

Data Area

Peripheral Control Registers

(512K Bytes)

Reserved

MPU Control Registers

Reserved

0xFFF8_0000

0xFFF7_FFFF

0xFFF0_0000

0xFFE8_BFFF

0xFFE8_7FFF

0xFFE8_4024
0xFFE8_4023
0xFFE8_4000

0xFFE0_0000

0x0000_0020

0x0000_001F

0x0000_0000

FIQ

IRQ

Reserved

Data Abort

Prefetch Abort

Software Interrupt

Undefined Instruction

Reset

0x0000_001F

0x0000_001C

0x0000_0018

0x0000_0014

0x0000_0010

0x0000_000C

0x0000_0008

0x0000_0004

0x0000_0000

Reserved

0xFFFF_FFFF

0xFFFF_FD00

0xFFF8_0000

HET

0xFFF7_FC00

0xFFF7_F800

0xFFF7_F400

0xFFF7_F000

0xFFF7_EC00

0xFFF7_E400

SPI1

SCI1

MibADC

GIO/ECP

Reserved

RAM

(8K Bytes)

FLASH

(128K Bytes)

10 Sectors

Flash Control Registers

Reserved

0xFFEF_FFFF

0xFFE8_C000

0xFFE8_8000

SCC RAM

SCC

0xFFF7_E000

0xFFF7_DC00

0xFFF7_D800

0xFFF7_D400

C2SIa

Reserved

0xFFF0_0000

SYSTEM

0xFFE8_3FFF

SCI2

0xFFF7_F500

Reserved

SPI2

0xFFF7_C800

0xFFF7_CC00

TMS470R1A128

16/32-Bit RISC Flash Microcontrollers

SPNS098 JANUARY 2005

Figure 1 shows the memory map of the TMS470R1A128 device.

Memory addresses are configurable by the system (SYS) module within the range of 0x0000_0000 to 0xFFE0_0000.

The CPU registers are not part of the memory map.

Figure 1. Memory Map

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memory selects

RAM

F05 Flash

TMS470R1A128
16/32-Bit RISC Flash Microcontrollers

SPNS098 JANUARY 2005

Memory selects allow the user to address memory arrays (i.e., Flash, RAM, and HET RAM) at user-defined
addresses. Each memory select has its own set (low and high) of memory base address registers (MFBAHRx
and MFBALRx) that together define the array's starting (base) address, block size, and protection.

The base address of each memory select is configurable to any memory address boundary that is a multiple of
the decoded block size. For more information on how to control and configure these memory select registers, see
the bus structure and memory sections of the TMS470R1x System Module Reference Guide (literature number
SPNU189).

For the memory selection assignments and the memory selected, see Table 3.

Table 3. Memory Selection Assignment

MEMORY

MEMORY SELECTED

MEMORY

STATIC MEM

MPU

MEMORY BASE ADDRESS REGISTER

SELECT

(ALL INTERNAL)

SIZE

CTL REGISTER

0 (fine)

FLASH

MFBAHR0 and MFBALR0

128K

1 (fine)

FLASH

MFBAHR1 and MFBALR1

2 (fine)

RAM

YES

MFBAHR2 and MFBALR2

(1)

3 (fine)

RAM

YES

MFBAHR3 and MFBALR3

4 (fine)

HET RAM

MFBAHR4 and MFBALR4

SMCR1

(1)

The starting addresses for both RAM memory-select signals cannot be offset from each other by a multiple of the user-defined block
size in the memory-base address register.

The A128 devices contain 8K bytes of internal static RAM configurable by the SYS module to be addressed
within the range of 0x0000_0000 to 0xFFE0_0000. This RAM is implemented in one 8K array selected by two
memory-select signals. This configuration imposes an additional constraint on the memory map for RAM; the
starting addresses for both RAM memory selects cannot be offset from each other by the multiples of the size of
the physical RAM (i.e., 8K for the A128 device). The RAM is addressed through memory selects 2 and 3.

The RAM can be protected by the memory protection unit (MPU) portion of the SYS module, allowing the user
finer blocks of memory protection than is allowed by the memory selects. The MPU is ideal for protecting an
operating system while allowing access to the current task. For more detailed information on the MPU portion of
the SYS module and memory protection, see the memory section of the TMS470R1x System Module Reference
Guide (literature number SPNU189).

The F05 Flash memory is a nonvolatile electrically erasable and programmable memory implemented with a
32-bit-wide data bus interface. The F05 Flash has an external state machine for programming and erase
functions. See the Flash read and Flash program and erase sections.

Flash protection keys

The A128 devices provide Flash protection keys. These four 32-bit protection keys prevent pro-
gram/erase/compaction operations from occurring until after the four protection keys have been matched by the
CPU loading the correct user keys into the FMPKEY control register. The protection keys on the A128 are
located in the last four words of the first 8K sector. For more detailed information on the Flash protection keys
and the FMPKEY control register, see the protection keys portions of the TMS470R1x F05 Flash Reference
Guide (literature number SPNU213).

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HET RAM

TMS470R1A128

16/32-Bit RISC Flash Microcontrollers

SPNS098 JANUARY 2005

Flash read

The A128 Flash memory is configurable by the SYS module to be addressed within the range of 0x0000_0000 to
0xFFE0_0000. The Flash is addressed through memory selects 0 and 1.

NOTE:

The Flash external pump voltage (V

CCP

) is required for all operations (program, erase,

and read).

Flash pipeline mode

When in pipeline mode, the Flash operates with a system clock frequency of up to 48 MHz (versus a system
clock in normal mode of up to 28 MHz). Flash in pipeline mode is capable of accessing 64-bit words and
provides two 32-bit pipelined words to the CPU. Also in pipeline mode, the Flash can be read with no wait states
when memory addresses are contiguous (after the initial 1-or 2-wait-state reads).

NOTE:

After a system reset, pipeline mode is disabled (ENPIPE bit [FMREGOPT.0] is a 0).
In other words, the A128 devices power up and come out of reset in non-pipeline
mode. Furthermore, setting the Flash configuration mode bit (GLBCTRL.4) will
override pipeline mode.

Flash program and erase

The A128 device Flash has one 128K-byte bank that consists of ten sectors. These ten sectors are shown in
Table 4.

Table 4. Flash Sectors

SECTOR NO.

SEGMENT

LOW ADDRESS

HIGH ADDRESS

8K Bytes

0x0000_0000

0x0000_1FFF

8K Bytes

0x0000_2000

0x0000_3FFF

16K Bytes

0x0000_4000

0x0000_7FFF

16K Bytes

0x0000_8000

0x0000_BFFF

16K Bytes

0x0000_C000

0x0000_FFFF

16K Bytes

0x0001_0000

0x0001_3FFF

16K Bytes

0x0001_4000

0x0001_7FFF

16K Bytes

0x0001_8000

0x0001_BFFF

8K Bytes

0x0001_C000

0x0001_DFFF

8K Bytes

0x0001_E000

0x0001_FFFF

The minimum size for an erase operation is one sector. The maximum size for a program operation is one 16-bit
word.

NOTE:

The Flash external pump voltage (V

CCP

) is required for all operations (program, erase,

and read).

For more detailed information on Flash program and erase operations, see the TMS470R1x F05 Flash
Reference Guide (literature number SPNU213).

The A128 devices contain HET RAM. The HET RAM has a 64-instruction capability. The HET RAM is
configurable by the SYS module to be addressed within the range of 0x0000_0000 to 0xFFE0_0000. The HET
RAM is addressed through memory select 4.

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XOR share

peripheral selects and base addresses

TMS470R1A128
16/32-Bit RISC Flash Microcontrollers

SPNS098 JANUARY 2005

The A128 HET peripheral contains the XOR-share feature. This feature allows two adjacent HET high-resolution
channels to be XORed together, making it possible to output smaller pulses than a standard HET. For more
detailed information on the HET XOR-share feature, see the TMS470R1x High-End Timer (HET) Reference
Guide (literature number SPNU199).

The A128 devices use 10 of the 16 peripheral selects to decode the base addresses of the peripherals. These
peripheral selects are fixed and transparent to the user since they are part of the decoding scheme used by the
SYS module.

Control registers for the peripherals, SYS module, and Flash begin at the base addresses shown in Table 5.

Table 5. TMS470R1A128 Peripherals, System Module, and Flash Base Addresses

ADDRESS RANGE

CONNECTING MODULE

PERIPHERAL SELECTS

BASE ADDRESS

ENDING ADDRESS

SYSTEM

0xFFFF_FD00

0xFFFF_FFFF

N/A

Reserved

0xFFF8_0000

0xFFFF_FCFF

N/A

HET

0xFFF7_FC00

0xFFF7_FFFF

PS[0]

SPI1

0xFFF7_F800

0xFFF7_FBFF

PS[1]

SCI2

0XFFF7_F500

0XFFF7_F7FF

PS[2]

SCI1

0xFFF7_F400

0xFFF7_F4FF

ADC

0xFFF7_F000

0xFFF7_F3FF

PS[3]

GIO/ECP

0xFFF7_EC00

0xFFF7_EFFF

PS[4]

Reserved

0xFFF7_E400

0xFFF7_EBFF

PS[5] - PS[6]

SCC

0xFFF7_E000

0xFFF7_E3FF

PS[7]

SCC RAM

0xFFF7_DC00

0xFFF7_DFFF

PS[8]

RESERVED

0XFFF7_D800

0XFFF7_DBFF

PS[9]

SPI2

0XFFF7_D400

0XFFF7_D7FF

PS[10]

Reserved

0xFFF7_CC00

0xFFF7_D3FF

PS[11] - PS[12]

C2SIA

0XFFF7_C800

0XFFF7_CBFF

PS(13)

Reserved

0xFFF7_C000

0xFFF7_C7FF

PS[14] - PS[15]

Reserved

0xFFF0_0000

0xFFF7_BFFF

N/A

Flash Control Registers

0xFFE8_8000

0xFFE8_BFFF

N/A

MPU Control Registers

0xFFE8_4000

0xFFE8_4023

N/A

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interrupt priority

TMS470R1A128

16/32-Bit RISC Flash Microcontrollers

SPNS098 JANUARY 2005

The central interrupt manager (CIM) portion of the SYS module manages the interrupt requests from the device
modules (i.e., SPI1 or SPI2, SCI1 or SCI2, and RTI, etc.).

Although the CIM can accept up to 32 interrupt request signals, the A128 devices only use 21 of those interrupt
request signals. The request channels are maskable so that individual channels can be selectively disabled. All
interrupt requests can be programmed in the CIM to be of either type:

Fast interrupt request (FIQ)

Normal interrupt request (IRQ)

The precedences of request channels decrease with ascending channel order in the CIM (0 [highest] and 31
[lowest] priority). For these channel priorities and the associated modules, see Table 6.

Table 6. Interrupt Priority

MODULES

INTERRUPT SOURCES

INTERRUPT LEVEL/CHANNEL

SPI1

SPI1 end-transfer/overrun

RTI

COMP2 interrupt

RTI

COMP1 interrupt

RTI

TAP interrupt

SPI2

SPI2 end-transfer/overrun

GIO

Interrupt A

Reserved

HET

Interrupt A

Reserved

SCI1/SCI2

SCI1/SCI2 error interrupt

SCI1

SCI1 receive interrupt

C2SIa

C2SIa interrupt

Reserved

SCC

Interrupt A

Reserved

MibADC

End event conversion

SCI2

SCI2 receive interrupt

Reserved

SCI1

SCI1 transmit interrupt

System

SW interrupt (SSI)

Reserved

HET

Interrupt B

Reserved

SCC

Interrupt B

SCI2

SCI2 transmit interrupt

MibADC

End Group1 conversion

Reserved

GIO

Interrupt B

MibADC

End Group2 conversion

Reserved

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MibADC

MibADC event trigger enhancements

TMS470R1A128
16/32-Bit RISC Flash Microcontrollers

SPNS098 JANUARY 2005

The multi-buffered analog-to-digital converter (MibADC) accepts an analog signal and converts the signal to a
10-bit digital value.

The A128 MibADC module can function in two modes: compatibility mode, where its programmer's model is
compatible with the TMS470R1x ADC module and its digital results are stored in digital result registers; or in
buffered mode, where the digital result registers are replaced with three FIFO buffers, one for each conversion
group [event, group1 (G1), and group2 (G2)]. In buffered mode, the MibADC buffers can be serviced by
interrupts.

The MibADC includes two major enhancements over the event-triggering capability of the TMS470R1x ADC.

Both group1 and the event group can be configured for event-triggered operation, providing up to two
event-triggered groups.

The trigger source and polarity can be selected individually for both group1 and the event group from the
three options identified in Table 7.

Table 7. MibADC Event Hookup Configuration

SOURCE SELECT BITS for G1 or EVENT

EVENT #

SIGNAL PIN NAME

(G1SRC[1:0] or EVSRC[1:0])

EVENT1

ADEVT

EVENT2

HET18

EVENT3

HET19

EVENT4

reserved

For group1, these event-triggered selections are configured via the group1 source select bits (G1SRC[1:0]) in the
AD event source register (ADEVTSRC.[5:4]). For the event group, these event-triggered selections are
configured via the event group source select bits (EVSRC[1:0]) in the AD event source register
(ADEVTSRC.[1:0]).

For more detailed functional information on the MibADC, see the TMS470R1x Multi-Buffered Analog-to-Digital
Converter (MibADC) Reference Guide (literature number SPNU206).

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documentation support

TMS470R1A128

16/32-Bit RISC Flash Microcontrollers

SPNS098 JANUARY 2005

Extensive documentation supports all of the TMS470 microcontroller family of devices. The types of
documentation available include data sheets with design specifications; complete user's guides for all devices
and development support tools; and hardware and software application notes. Useful reference documentation
includes:

Bulletin
TMS470 Microcontroller Family Product Bulletin (literature number SPNB086)

Data Sheets
TMS470R1A128 16/32Bit RISC Microcontroller (literature number SPNS098)
TMS470R1A64 16/32Bit RISC Microcontroller (literature number SPNS099)
TMS470RA256 16/32Bit RISC Microcontroller (literature number SPNS100)

User's Guides
TMS470R1x System Module Reference Guide (literature number SPNU189)
TMS470R1x GeneralPurpose Input/Output (GIO) Reference Guide (literature number SPNU192)
TMS470R1x Serial Peripheral Interface (SPI) Reference Guide SPNU195
TMS470R1x Serial Communication Interface (SCI) Reference Guide (literature number SPNU196)
TMS470R1x Controller Area Network (CAN) Reference Guide (literature number SPNU197)
TMS470R1x HighEnd Timer (HET) Reference Guide (literature number SPNU199)
TMS470R1x External Clock Prescale (ECP) Reference Guide (literature number SPNU202)
TMS470R1x MultiBuffered AnalogtoDigital (MibADC) Reference Guide (literature number SPNU206)
TMS470R1x ZeroPin PhaseLocked Loop (ZPLL) Clock Module Reference Guide (literature number

SPNU212)

TMS470R1x F05 Flash Reference Guide (literature number SPNU213)
TMS470R1x Class II Serial Interface B (C2SIb) Reference Guide (literature number SPNU214)
TMS470R1x Class II Serial Interface A (C2SIa) Reference Guide (literature number SPNU218)
TMS470 Peripherals Overview Reference Guide (literature number SPNU248)

Errata Sheet:
TMS470R1A128 TMS470 Microcontrollers Silicon Errata (literature number SPNZ132)

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device numbering conventions

PREFIX

470

FAMILY

DEVICE TYPE A

= 100-pin Low-Profile Quad Flatpack (LQFP)

TMS

470 = TMS470 RISC - Embedded

Microcontroller Family

PACKAGE TYPE

ARCHITECTURE

R1 = ARM7TDM1 CPU

TMS = Fully Qualified Device

128 = 128K-Bytes Flash Memory

128

REVISION CHANGE

Blank = Original

Blank = No options

OPTIONS

FLASH MEMORY

With 128K-Bytes Flash memory:

1.8V Core, 3.3V I/O

Flash Program Memory

Temperature Range: -40

to +85

Celsius

ZPLL Clock

8K-Byte Static RAM

1K-Byte HET RAM (64 Instructions)

Analog Watchdog (AWD)

Real-Time Interrupt (RTI)

10-bit, 16-input MibADC

Two SPI Modules

Two SCI Modules

C2SIa

CAN [SCC]

HET, 16 Channels

ECP

TMS470R1A128
16/32-Bit RISC Flash Microcontrollers

SPNS098 JANUARY 2005

Figure 2 illustrates the numbering and symbol nomenclature for the TMS470R1x family.

Figure 2. TMS470R1x Family Nomenclature

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device identification code register

TMS470R1A128

16/32-Bit RISC Flash Microcontrollers

SPNS098 JANUARY 2005

The device identification code register identifies the silicon version, the technology family (TF), a ROM or Flash
device, and an assigned device-specific part number (see Figure 3 and Table 8). The A128 device identification
code register value is 0x283F.

Reserved

VERSION

R/F

PART NUMBER

R-K

R-1

LEGEND:
For bits 3-15: R = Read only, -K = Value constant after RESET
For bits 0-2: R = Read only, -1 = Value after RESET

Figure 3. TMS470 Device ID Bit Allocation Register [FFFF-FFFO]

Table 8. TMS Device ID Bit Allocation Register Field Description

Bit

Name

Value

Description

3116

Reserved

Reads are undefined and writes have no effect.

1512

VERSION

Silicon version (revision)
These bits identify the silicon version of the device.

Technology family
This bit distinguishes the technology family core power supply.

3.3 V for F10/C10 devices

1.8 V for F05/C05 devices

R/F

ROM/Flash
This bit distinguishes between ROM and Flash devices:

Flash device

ROM device

PART NUMBER

Device-specific part number
These bits identify the assigned device-specific part number.
The assigned device-specific part number for the A128 devices is 0000111.

Mandatory High

"1" Mandatory High

Bits 2,1, and 0 are tied high by default.

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DEVICE ELECTRICAL SPECIFICATIONS AND TIMING PARAMETERS

absolute maximum ratings over operating free-air temperature range

(1)

device recommended operating conditions

(1)

TMS470R1A128
16/32-Bit RISC Flash Microcontrollers

SPNS098 JANUARY 2005

Supply voltage ranges:

(2)

-0.5 V to 2.5 V

Supply voltage ranges:

CCIO

, V

CCAD

, V

CCP

(Flash pump)

(2)

-0.5 V to 4.1 V

Input voltage range:

All input pins

-0.5 V to 4.1 V

Input clamp current:

< 0 or V

> V

CCIO

)

All pins except ADIN[0:11], PORRST, TRST,

20 mA

TEST and TCK

< 0 or V

> V

CCAD

)

ADIN[0:11]

10 mA

Operating free-air temperature ranges, T

-40

C to 85

Operating junction temperature range, T

-40

C to 150

Storage temperature range, T

stg

-65

C to 150

(1)

Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the devices at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2)

All voltage values are with respect to their associated grounds.

MIN

NOM

MAX

UNIT

Digital logic (and Flash supply voltage for A128) (Core)

1.81

2.05

CCIO

Digital logic supply voltage (I/O)

3.3

3.6

CCAD

ADC supply voltage

3.3

3.6

CCP

Flash pump supply voltage

3.3

3.6

Digital logic supply ground

SSAD

ADC supply ground

-0.1

0.1

Operating free-air temperature

-40

Operating junction temperature

-40

150

(1)

All voltages are with respect to V

, except V

CCAD

, which is with respect to V

SSAD

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electrical characteristics over recommended operating free-air temperature range

(1)

TMS470R1A128

16/32-Bit RISC Flash Microcontrollers

SPNS098 JANUARY 2005

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

hys

Input hysteresis

0.15

Low-level input volt-

All inputs

(2)

except

-0.3

0.8

age

OSCIN

OSCIN only

-0.3

0.35 V

High-level input volt-

All inputs except

CCIO

age

OSCIN

0.3

OSCIN only

0.85 V

+ 0.3

Input threshold volt-

AWD only

1.35

1.8

age

Drain to source on re-

RDS

AWD only

(3)

= 0.35V @ I

= 8mA

sistance

= I

MAX

0.2 V

CCIO

Low-level output voltage

(4)

= 50 µA

0.2

= I

MIN

0.8 V

CCIO

High-level output voltage

(4)

= 50 µA

CCIO

- 0.2

Input clamp current (I/O pins)

(5)

< V

SSIO

- 0.3 or V

> V

CCIO

+ 0.3

-2

Pulldown

= V

-1

Pulldown

= V

CCIO

Input current (I/O

Pullup

= V

-40

-5

µA

pins)

Pullup

= V

CCIO

-1

All other pins

No pullup or pulldown

-1

CLKOUT, AWD, TDO

= V

MAX

RST, SPI1CLK,
SPI1SOMI,

Low-level output

SPI1SIMO, SPI2CLK,

= V

MAX

current

SPI2SOMI,
SPI2SIMO

All other output pins

= V

MAX

(6)

CLKOUT, TDO

= V

MIN

-8

SPI1CLK, SPI1SOMI,
SPI1SIMO, SPI2CLK,

High-level output

= V

MIN

-4

SPI2SOMI,

current

SPI2SIMO

All other output pins

= V

MIN

-2

except RST

(6)

Digital supply

Pipeline

SYSCLK = 48 MHz,

current (operating

ICLK = 24 MHz, V

= 2.05 V

mode)

Non-pipeline

SYSCLK = 28 MHz,

ICLK = 14 MHz, V

= 2.05 V

Digital supply current (standby mode)

(7)

OSCIN = 6 MHz, V

= 2.05 V

3.0

Digital supply current (halt mode)

(7)

All frequencies, V

= 2.05 V

1.0

CCIO

Digital supply current (operating mode)

No DC load, V

CCIO

= 3.6 V

(8)

CCIO

Digital supply current (standby mode)

No DC load, V

CCIO

= 3.6 V

(8)

300

µA

CCIO

Digital supply current (halt mode)

No DC load, V

CCIO

= 3.6 V

(8)

300

µA

(1)

Source currents (out of the device) are negative while sink currents (into the device) are positive.

(2)

This does not apply to the PORRST pin. For PORRST exceptions, see the RST and PORRST timings section.

(3)

These values help to determine the external RC network circuit. For more details, see the TMS470R1x System Module Reference Guide
(literature number SPNU189).

(4)

and V

are linear with respect to the amount of load current (I

) applied.

(5)

Parameter does not apply to input-only or output-only pins.

(6)

The 2 mA buffers on these devices are called zero-dominant buffers. If two of these buffers are shorted together and one is outputting a
low level and the other is outputting a high level, the resulting value will always be low.

(7)

For Flash banks/pumps in sleep mode.

(8)

I/O pins configured as inputs or outputs with no load. All pulldown inputs

0.2 V. All pullup inputs

CCIO

- 0.2 V.

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PARAMETER MEASUREMENT INFORMATION

Tester Pin

Electronics

LOAD

Output
Under
Test

Where:

= I

MAX for the respective pin

(A)

= I

MIN for the respective pin

(A)

LOAD

= 1.5 V

= 150-pF typical load-circuit capacitance

(B)

TMS470R1A128
16/32-Bit RISC Flash Microcontrollers

SPNS098 JANUARY 2005

electrical characteristics over recommended operating free-air temperature range (continued)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

CCAD

supply current (operating mode)

All frequencies, V

CCAD

= 3.6 V

CCAD

supply current (standby mode)

All frequencies, V

CCAD

= 3.6 V

µA

CCAD

supply current (halt mode)

All frequencies, V

CCAD

= 3.6 V

µA

CCP

= 3.6 V read operation

CCP

= 3.6 V program and erase

CCP

= 3.6 V standby mode oper-

CCP

pump supply current

µA

ation

(7)

CCP

= 3.6 V halt mode oper-

µA

ation

(7)

Input capacitance

Output capacitance

For these values, see the "electrical characteristics over recommended operating free-air temperature range" table.

All timing parameters measured using an external load capacitance of 150 pF unless otherwise noted.

Figure 4. Test Load Circuit

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timing parameter symbology

TMS470R1A128

16/32-Bit RISC Flash Microcontrollers

SPNS098 JANUARY 2005

PARAMETER MEASUREMENT INFORMATION (continued)

Timing parameter symbols have been created in accordance with JEDEC Standard 100. To shorten the symbols,
some of the pin names and other related terminology have been abbreviated as follows:

COMPACTION, CMPCT

Read

CLKOUT

RST

Reset, RST

Erase

SCInRX

ICLK

Interface clock

Slave mode

Master mode

SCC

SCInCLK

OSC, OSCI OSCIN

SIMO

SPInSIMO

OSCO

OSCOUT

SOMI

SPInSOMI

Program, PROG

SPC

SPInCLK

Ready

SYS

System clock

Read margin 0, RDMRGN0

SCInTX

Read margin 1, RDMRGN1

Lowercase subscripts and their meanings are:

access time

rise time

cycle time (period)

setup time

delay time

transition time

fall time

valid time

hold time

pulse duration (width)

The following additional letters are used with these meanings:

High

Unknown, changing, or don't care level

Low

High impedance

Valid

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external reference resonator/crystal oscillator clock option

External

Clock Signal

(toggling 0-1.8 V

OSCOUT

OSCIN

Crystal

OSCOUT

OSCIN

(a)

(b)

(A)

TMS470R1A128
16/32-Bit RISC Flash Microcontrollers

SPNS098 JANUARY 2005

PARAMETER MEASUREMENT INFORMATION (continued)

The oscillator is enabled by connecting the appropriate fundamental 420 MHz resonator/crystal and load
capacitors across the external OSCIN and OSCOUT pins as shown in Figure 5(a). The oscillator is a
single-stage inverter held in bias by an integrated bias resistor. This resistor is disabled during leakage test
measurement and HALT mode. TI strongly encourages each customer to submit samples of the device to
the resonator/crystal vendors for validation. The vendors are equipped to determine what load capacitors will
best tune their resonator/crystal to the microcontroller device for optimum start-up and operation over
temperature/voltage extremes.

An external oscillator source can be used by connecting a 1.8 V clock signal to the OSCIN pin and leaving the
OSCOUT pin unconnected (open) as shown in Figure 5(b).

The values of C1 and C2 should be provided by the resonator/crystal vendor.

Figure 5. Crystal/Clock Connection

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ZPLL and clock specifications

timing requirements for ZPLL circuits enabled or disabled

switching characteristics over recommended operating conditions for clocks

(1) (2)

TMS470R1A128

16/32-Bit RISC Flash Microcontrollers

SPNS098 JANUARY 2005

MIN

MAX

UNIT

(OSC)

Input clock frequency

MHz

c(OSC)

Cycle time, OSCIN

w(OSCIL)

Pulse duration, OSCIN low

w(OSCIH)

Pulse duration, OSCIN high

(OSCRST)

OSC FAIL frequency

(1)

kHz

(1)

Causes a device reset (specifically a clock reset) by setting the RST OSC FAIL (GLBCTRL.15) and the OSC FAIL flag (GLBSTAT.1)
bits equal to 1. For more detailed information on these bits and device resets, see the TMS470R1x System Module Reference Guide
(literature number SPNU189).

PARAMETER

TEST CONDITIONS

(3)

MIN

MAX

UNIT

Pipeline mode enabled

(SYS)

System clock frequency

(4)

MHz

Pipeline mode disabled

(CONFIG)

System clock frequency - Flash config mode

MHz

Pipeline mode enabled

(ICLK)

Interface clock frequency

MHz

Pipeline mode disabled

Pipeline mode enabled

(ECLK)

External clock output frequency for ECP Module

MHz

Pipeline mode disabled

Pipeline mode enabled

20.8

c(SYS)

Cycle time, system clock

Pipeline mode disabled

35.7

c(CONFIG)

Cycle time, system clock - Flash config mode

41.6

Pipeline mode enabled

c(ICLK)

Cycle time, interface clock

Pipeline mode disabled

41.6

Pipeline mode enabled

c(ECLK)

Cycle time, ECP module external clock output

Pipeline mode disabled

41.6

(1)

(SYS)

= M

(OSC)

/ R, where M = {4 or 8}, R = {1,2,3,4,5,6,7,8} when PLLDIS = 0. R is the system-clock divider determined by the

CLKDIVPRE [2:0] bits in the global control register (GLBCTRL.[2:0]) and M is the PLL multiplier determined by the MULT4 bit, also in
the GLBCTRL register (GLBCTRL.3).
f

(SYS)

= f

(OSC)

/ R, where R = {1,2,3,4,5,6,7,8} when PLLDIS = 1.

(ICLK)

= f

(SYS)

/ X, where X = {1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16}. X is the interface clock divider ratio determined by the PCR0.[4:1]

bits in the SYS module.

(2)

(ECLK)

= f

(ICLK)

/ N, where N = {1 to 256}. N is the ECP prescale value defined by the ECPCTRL.[7:0] register bits in the ECP module.

(3)

Pipeline mode enabled or disabled is determined by the ENPIPE bit (FMREGOPT.0).

(4)

Flash Vread must be set to 5V to achieve maximum system clock frequency.

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switching characteristics over recommended operating conditions for external clocks

(1) (2) (3)

CLKOUT

ECLK

TMS470R1A128
16/32-Bit RISC Flash Microcontrollers

SPNS098 JANUARY 2005

(see Figure 6 and Figure 7)

NO.

PARAMETER

TEST CONDITIONS

MIN

MAX

UNIT

SYSCLK or MCLK

(4)

0.5t

c(SYS)

- t

w(COL)

Pulse duration, CLKOUT low

ICLK, X is even or 1

(5)

0.5t

c(ICLK)

- t

ICLK, X is odd and not 1

(5)

0.5t

c(ICLK)

+ 0.5t

c(SYS)

- t

SYSCLK or MCLK

(4)

0.5t

c(SYS)

- t

w(COH)

Pulse duration, CLKOUT high

ICLK, X is even or 1

(5)

0.5t

c(ICLK)

- t

ICLK, X is odd and not 1

(5)

0.5t

c(ICLK)

- 0.5t

c(SYS)

- t

N is even and X is even or odd

0.5t

c(ECLK)

- t

w(EOL)

Pulse duration, ECLK low

N is odd and X is even

N is odd and X is odd and not 1

0.5t

c(ECLK)

+ 0.5t

c(SYS)

- t

N is even and X is even or odd

0.5t

c(ECLK)

- t

w(EOH)

Pulse duration, ECLK high

N is odd and X is even

N is odd and X is odd and not 1

0.5t

c(ECLK)

- 0.5t

c(SYS)

- t

(1)

X = {1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16}. X is the interface clock divider ratio determined by the PCR0.[4:1] bits in the SYS module.

(2)

N = {1 to 256}. N is the ECP prescale value defined by the ECPCTRL.[7:0] register bits in the ECP module.

(3)

CLKOUT/ECLK pulse durations (low/high) are a function of the OSCIN pulse durations when PLLDIS is active.

(4)

Clock source bits selected as either SYSCLK (CLKCNTL.[6:5] = 11 binary) or MCLK (CLKCNTL.[6:5] = 10 binary).

(5)

Clock source bits selected as ICLK (CLKCNTL.[6:5] = 01 binary).

Figure 6. CLKOUT Timing Diagram

Figure 7. ECLK Timing Diagram

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RST and PORRST timings

timing requirements for PORRST

(1)

CCP

CCIO

CCPORH

CCIOPORL

IL(PORRST)

CCIOPORH

CCIOPORL

CCPORL

PORRST

CCIO

CCPORH

CCPORL

IL(PORRST)

switching characteristics over recommended operating conditions for RST

(1)

TMS470R1A128

16/32-Bit RISC Flash Microcontrollers

SPNS098 JANUARY 2005

(see Figure 8)

NO.

MIN

MAX

UNIT

CCPORL

low supply level when PORRST must be active during power up

0.6

CCPORH

high supply level when PORRST must remain active during power up and

1.5

become active during power down

CCIOPORL

CCIO

low supply level when PORRST must be active during power up

1.1

CCIOPORH

CCIO

high supply level when PORRST must remain active during power up and

2.75

become active during power down

Low-level input voltage after V

CCIO

> V

CCIOPORH

0.2 V

CCIO

IL(PORRST)

Low-level input voltage of PORRST before V

CCIO

> V

CCIOPORL

0.5

su(PORRST)r

Setup time, PORRST active before V

CCIO

> V

CCIOPORL

during power up

su(VCCIO)r

Setup time, V

CCIO

> V

CCIOPORL

before V

> V

CCPORL

h(PORRST)r

Hold time, PORRST active after V

> V

CCPORH

su(PORRST)f

Setup time, PORRST active before V

CCPORH

during power down

µs

h(PORRST)rio

Hold time, PORRST active after V

> V

CCIOPORH

h(PORRST)d

Hold time, PORRST active after V

< V

CCPORL

su(PORRST)fio

Setup time, PORRST active before V

CCIOPORH

during power down

su(VCCIO)f

Setup time, V

< V

CCPORE

before V

CCIO

< V

CCIOPORL

(1)

When the V

timing requirements for PORRST are satisfied, there are no timing requirements for V

CCP

Figure 8. PORRST Timing Diagram

PARAMETER

MIN

MAX

UNIT

Valid time, RST active after PORRST inactive

4112t

c(OSC)

v(RST)

Valid time, RST active (all others)

c(SYS)

(1)

Specified values do NOT include rise/fall times. For rise and fall timings, see the "switching characteristics for output timings versus load
capacitance" table.

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output timings

switching characteristics for output timings versus load capacitance (C

)

80%

20%

Output

TMS470R1A128

16/32-Bit RISC Flash Microcontrollers

SPNS098 JANUARY 2005

(see Figure 10)

PARAMETER

MIN

MAX

UNIT

= 15 pF

0.5

2.50

= 50 pF

1.5

Rise time, CLKOUT, AWD, TDO

= 100 pF

= 150 pF

4.5

12.5

= 15 pF

0.5

2.5

= 50 pF

1.5

Fall time, CLKOUT, AWD, TDO

= 100 pF

= 150 pF

4.5

12.5

= 15 pF

2.5

= 50 pF

Rise time, SPI1CLK, SPI1SOMI, SPI1SIMO, SPI2CLK,

SPI2SOMI, SPI2SIMO

= 100 pF

= 150 pF

= 15 pF

2.5

= 50 pF

Fall time, RST, SPI1CLK, SPI1SOMI, SPI1SIMO, SPI2CLK,

SPI2SOMI, SPI2SIMO

= 100 pF

= 150 pF

= 15 pF

2.5

= 50 pF

6.0

Rise time, all other output pins

= 100 pF

= 150 pF

= 15 pF

= 50 pF

8.5

Fall time, all other output pins

= 100 pF

= 150 pF

Figure 10. CMOS-Level Outputs

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input timings

timing requirements for input timings

(1)

80%

20%

Input

Flash timings

timing requirements for program Flash

(1)

TMS470R1A128
16/32-Bit RISC Flash Microcontrollers

SPNS098 JANUARY 2005

(see Figure 11)

MIN

MAX

UNIT

Input minimum pulse width

c(ICLK)

+ 10

(1)

c(ICLK)

= interface clock cycle time = 1/f

(ICLK)

Figure 11. CMOS-Level Inputs

MIN

TYP

MAX

UNIT

prog(16-bit)

Half word (16-bit) programming time

200

µs

prog(Total)

128K-byte programming time

(2)

erase(sector)

Sector erase time

wec

Write/erase cycles at T

= 125

100

cycles

(1)

For more detailed information on the Flash core sectors, see the Flash program and erase section of this data sheet.

(2)

The 128K-byte programming times include overhead of the state machine.

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SPIn MASTER MODE TIMING PARAMETERS

SPIn MASTER MODE EXTERNAL TIMING PARAMETERS

(1) (2) (3)

SPInSOMI

SPInSIMO

SPInCLK

(clock polarity = 1)

SPInCLK

(clock polarity = 0)

Master In Data

Must Be Valid

Master Out Data Is Valid

TMS470R1A128

16/32-Bit RISC Flash Microcontrollers

SPNS098 JANUARY 2005

(CLOCK PHASE = 0, SPInCLK = OUTPUT, SPInSIMO = OUTPUT, AND SPInSOMI = INPUT) (see Figure 12)

NO.

MIN

MAX

Unit

c(SPC)M

Cycle time, SPInCLK

(4)

100

256t

c(ICLK)

w(SPCH)M

Pulse duration, SPInCLK high (clock polarity = 0)

0.5t

c(SPC)M

- t

0.5t

c(SPC)M

+ 5

(5)

w(SPCL)M

Pulse duration, SPInCLK low (clock polarity = 1)

0.5t

c(SPC)M

- t

0.5t

c(SPC)M

+ 5

w(SPCL)M

Pulse duration, SPInCLK low (clock polarity = 0)

0.5t

c(SPC)M

- t

0.5t

c(SPC)M

+ 5

(5)

w(SPCH)M

Pulse duration, SPInCLK high (clock polarity = 1)

0.5t

c(SPC)M

- t

0.5t

c(SPC)M

+ 5

Delay time, SPInCLK high to SPInSIMO valid

d(SPCH-SIMO)M

(clock polarity = 0)

(5)

Delay time, SPInCLK low to SPInSIMO valid

d(SPCL-SIMO)M

(clock polarity = 1)

Valid time, SPInSIMO data valid after SPInCLK low

v(SPCL-SIMO)M

c(SPC)M

- 5 - t

(clock polarity = 0)

(5)

Valid time, SPInSIMO data valid after SPInCLK high

v(SPCH-SIMO)M

c(SPC)M

- 5 - t

(clock polarity = 1)

Setup time, SPInSOMI before SPInCLK low

su(SOMI-SPCL)M

(clock polarity = 0)

(5)

Setup time, SPInSOMI before SPInCLK high

su(SOMI-SPCH)M

(clock polarity = 1)

Valid time, SPInSOMI data valid after SPInCLK low

v(SPCL-SOMI)M

(clock polarity = 0)

(5)

Valid time, SPInSOMI data valid after SPInCLK high

v(SPCH-SOMI)M

(clock polarity = 1)

(1)

The MASTER bit (SPInCTRL2.3) is set and the CLOCK PHASE bit (SPInCTRL2.0) is cleared.

(2)

c(ICLK)

= interface clock cycle time = 1/f

(ICLK)

(3)

For rise and fall timings, see the switching characteristics for output timings versus load capacitance table.

(4)

When the SPI is in Master mode, the following must be true:
For PS values from 1 to 255: t

c(SPC)M

(PS +1)t

c(ICLK)

100 ns, where PS is the prescale value set in the SPInCTL1.[12:5] register bits.

For PS values of 0: t

c(SPC)M

= 2t

c(ICLK)

100 ns.

(5)

The active edge of the SPInCLK signal referenced is controlled by the CLOCK POLARITY bit (SPInCTRL2.1).

Figure 12. SPIn Master Mode External Timing (CLOCK PHASE = 0)

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SPIn MASTER MODE EXTERNAL TIMING PARAMETERS

(1) (2) (3)

Data Valid

SPInSOMI

SPInSIMO

SPInCLK

(clock polarity = 1)

SPInCLK

(clock polarity = 0)

Master In Data

Must Be Valid

Master Out Data Is Valid

TMS470R1A128
16/32-Bit RISC Flash Microcontrollers

SPNS098 JANUARY 2005

(CLOCK PHASE = 1, SPInCLK = OUTPUT, SPInSIMO = OUTPUT, AND SPInSOMI = INPUT) (see Figure 13)

NO.

MIN

MAX

Unit

c(SPC)M

Cycle time, SPInCLK

(4)

100

256t

c(ICLK)

w(SPCH)M

Pulse duration, SPInCLK high (clock polarity = 0)

0.5t

c(SPC)M

- t

0.5t

c(SPC)M

+ 5

(5)

w(SPCL)M

Pulse duration, SPInCLK low (clock polarity = 1)

0.5t

c(SPC)M

- t

0.5t

c(SPC)M

+ 5

w(SPCL)M

Pulse duration, SPInCLK low (clock polarity = 0)

0.5t

c(SPC)M

- t

0.5t

c(SPC)M

+ 5

(5)

w(SPCH)M

Pulse duration, SPInCLK high (clock polarity = 1)

0.5t

c(SPC)M

- t

0.5t

c(SPC)M

+ 5

v(SIMO-SPCH)M

Valid time, SPInCLK high after SPInSIMO data valid

0.5t

c(SPC)M

- 10

(clock polarity = 0)

(5)

v(SIMO-SPCL)M

Valid time, SPInCLK low after SPInSIMO data valid

0.5t

c(SPC)M

- 10

(clock polarity = 1)

v(SPCH-SIMO)M

Valid time, SPInSIMO data valid after SPInCLK high

0.5t

c(SPC)M

- 5 - t

(clock polarity = 0)

(5)

v(SPCL-SIMO)M

Valid time, SPInSIMO data valid after SPInCLK low

0.5t

c(SPC)M

- 5 - t

(clock polarity = 1)

su(SOMI-SPCH)M

Setup time, SPInSOMI before SPInCLK high

(clock polarity = 0)

(5)

su(SOMI-SPCL)M

Setup time, SPInSOMI before SPInCLK low

(clock polarity = 1)

v(SPCH-SOMI)M

Valid time, SPInSOMI data valid after SPInCLK high

(clock polarity = 0)

(5)

v(SPCL-SOMI)M

Valid time, SPInSOMI data valid after SPInCLK low

(clock polarity = 1)

(1)

The MASTER bit (SPInCTRL2.3) is set and the CLOCK PHASE bit (SPInCTRL2.0) is set.

(2)

c(ICLK)

= interface clock cycle time = 1/f

(ICLK)

(3)

For rise and fall timings, see the "switching characteristics for output timings versus load capacitance" table.

(4)

When the SPI is in master mode, the following must be true:
For PS values from 1 to 255: t

c(SPC)M

(PS +1)t

c(ICLK)

100 ns, where PS is the prescale value set in the SPInCTL1.[12:5] register bits.

For PS values of 0: t

c(SPC)M

= 2t

c(ICLK)

100 ns.

(5)

The active edge of the SPInCLK signal referenced is controlled by the CLOCK POLARITY bit (SPInCTRL2.1).

Figure 13. SPIn Master Mode External Timing (CLOCK PHASE = 1)

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SPIn SLAVE MODE TIMING PARAMETERS

SPIn SLAVE MODE EXTERNAL TIMING PARAMETERS

(1) (2) (3) (4)

TMS470R1A128

16/32-Bit RISC Flash Microcontrollers

SPNS098 JANUARY 2005

(CLOCK PHASE = 0, SPInCLK = INPUT, SPInSIMO = INPUT, AND SPInSOMI = OUTPUT) (see Figure 14)

MIN

MAX

Unit

c(SPC)S

Cycle time, SPInCLK

(5)

100

256t

c(ICLK)

w(SPCH)S

Pulse duration, SPInCLK high (clock polarity = 0)

0.5t

c(SPC)S

- 0.25t

c(ICLK)

0.5t

c(SPC)S

+ 0.25t

c(ICLK)

(6)

w(SPCL)S

Pulse duration, SPInCLK low (clock polarity = 1)

0.5t

c(SPC)S

- 0.25t

c(ICLK)

0.5t

c(SPC)S

+ 0.25t

c(ICLK)

w(SPCL)S

Pulse duration, SPInCLK low (clock polarity = 0)

0.5t

c(SPC)S

- 0.25t

c(ICLK)

0.5t

c(SPC)S

+ 0.25t

c(ICLK)

(6)

w(SPCH)S

Pulse duration, SPInCLK high (clock polarity = 1)

0.5t

c(SPC)S

- 0.25t

c(ICLK)

0.5t

c(SPC)S

+ 0.25t

c(ICLK)

d(SPCH-

Delay time, SPInCLK high to SPInSOMI valid

6 + t

SOMI)S

(clock polarity = 0)

(6)

d(SPCL-

Delay time, SPInCLK low to SPInSOMI valid

6 + t

SOMI)S

(clock polarity = 1)

v(SPCH-

Valid time, SPInSOMI data valid after SPInCLK high

c(SPC)S

- 6 - t

SOMI)S

(clock polarity =0)

(6)

v(SPCL-

Valid time, SPInSOMI data valid after SPInCLK low

c(SPC)S

- 6 - t

SOMI)S

(clock polarity =1)

su(SIMO-

Setup time, SPInSIMO before SPInCLK low

SPCL)S

(clock polarity = 0)

(6)

su(SIMO-

Setup time, SPInSIMO before SPInCLK high

SPCH)S

(clock polarity = 1)

v(SPCL-

Valid time, SPInSIMO data valid after SPInCLK low

SIMO)S

(clock polarity = 0)

(6)

v(SPCH-

Valid time, SPInSIMO data valid after SPInCLK high

SIMO)S

(clock polarity = 1)

(1)

The MASTER bit (SPInCTRL2.3) is cleared and the CLOCK PHASE bit (SPInCTRL2.0) is cleared.

(2)

If the SPI is in slave mode, the following must be true: t

c(SPC)S

(PS + 1) t

c(ICLK)

, where PS = prescale value set in SPInCTL1.[12:5].

(3)

For rise and fall timings, see the switching characteristics for output timings versus load capacitance table.

(4)

c(ICLK)

= interface clock cycle time = 1/f

(ICLK)

(5)

When the SPIn is in slave mode, the following must be true:
For PS values from 1 to 255: t

c(SPC)S

(PS +1)t

c(ICLK)

100 ns, where PS is the prescale value set in the SPInCTL1.[12:5] register bits.

For PS values of 0: t

c(SPC)S

= 2t

c(ICLK)

100 ns.

(6)

The active edge of the SPInCLK signal referenced is controlled by the CLOCK POLARITY bit (SPInCTRL2.1).

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SPIn SLAVE MODE EXTERNAL TIMING PARAMETERS

(1) (2) (3) (4)

TMS470R1A128

16/32-Bit RISC Flash Microcontrollers

SPNS098 JANUARY 2005

(CLOCK PHASE = 1, SPInCLK = INPUT, SPInSIMO = INPUT, AND SPInSOMI = OUTPUT) (see Figure 15)

MIN

MAX

Unit

c(SPC)S

Cycle time, SPInCLK

(5)

100

256t

c(ICLK)

Pulse duration, SPInCLK high (clock polarity =

w(SPCH)S

0.5t

c(SPC)S

-0.25t

c(ICLK)

0.5t

c(SPC)S

+ 0.25t

c(ICLK)

(6)

Pulse duration, SPInCLK low (clock polarity =

w(SPCL)S

0.5t

c(SPC)S

-0.25t

c(ICLK)

0.5t

c(SPC)S

+ 0.25t

c(ICLK)

Pulse duration, SPInCLK low (clock polarity =

w(SPCL)S

0.5t

c(SPC)S

-0.25t

c(ICLK)

0.5t

c(SPC)S

+ 0.25t

c(ICLK)

(6)

Pulse duration, SPInCLK high (clock polarity =

w(SPCH)S

0.5t

c(SPC)S

-0.25t

c(ICLK)

0.5t

c(SPC)S

+ 0.25t

c(ICLK)

Valid time, SPInCLK high after SPInSOMI data

v(SOMI-SPCH)S

0.5t

c(SPC)S

- 6 - t

valid (clock polarity = 0)

(6)

Valid time, SPInCLK low after SPInSOMI data

v(SOMI-SPCL)S

0.5t

c(SPC)S

- 6 - t

valid (clock polarity = 1)

Valid time, SPInSOMI data valid after SPInCLK

v(SPCH-SOMI)S

0.5t

c(SPC)S

- 6 - t

high (clock polarity =0)

(6)

Valid time, SPInSOMI data valid after SPInCLK

v(SPCL-SOMI)S

0.5t

c(SPC)S

- 6 - t

low (clock polarity =1)

Setup time, SPInSIMO before SPInCLK high

su(SIMO-SPCH)S

(clock polarity = 0)

(6)

Setup time, SPInSIMO before SPInCLK low

su(SIMO-SPCL)S

(clock polarity = 1)

Valid time, SPInSIMO data valid after SPInCLK

v(SPCH-SIMO)S

high (clock polarity = 0)

(6)

Valid time, SPInSIMO data valid after SPInCLK

v(SPCL-SIMO)S

low (clock polarity = 1)

(1)

The MASTER bit (SPInCTRL2.3) is cleared and the CLOCK PHASE bit (SPInCTRL2.0) is set.

(2)

If the SPI is in slave mode, the following must be true: t

c(SPC)S

(PS + 1) t

c(ICLK)

, where PS = prescale value set in SPInCTL1.[12:5].

(3)

For rise and fall timings, see the switching characteristics for output timings versus load capacitance table.

(4)

c(ICLK)

= interface clock cycle time = 1/f

(ICLK)

(5)

When the SPIn is in slave mode, the following must be true:
For PS values from 1 to 255: t

c(SPC)S

(PS +1)t

c(ICLK)

100 ns, where PS is the prescale value set in the SPInCTL1.[12:5] register bits.

For PS values of 0: t

c(SPC)S

= 2t

c(ICLK)

100 ns.

(6)

The active edge of the SPInCLK signal referenced is controlled by the CLOCK POLARITY bit (SPInCTRL2.1).

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Data Valid

SPInSIMO

SPInSOMI

SPInCLK

(clock polarity = 1)

SPInCLK

(clock polarity = 0)

SPISIMO Data Must

Be Valid

SPISOMI Data Is Valid

SCIn ISOSYNCHRONOUS MODE TIMINGS INTERNAL CLOCK

TIMING REQUIREMENTS FOR INTERNAL CLOCK SCIn ISOSYNCHRONOUS MODE

(1) (2) (3)

TMS470R1A128
16/32-Bit RISC Flash Microcontrollers

SPNS098 JANUARY 2005

Figure 15. SPIn Slave Mode External Timing (CLOCK PHASE = 1)

(BAUD + 1)

IS EVEN OR BAUD = 0

IS ODD AND BAUD

NO.

UNIT

MIN

MAX

MIN

MAX

c(SCC)

Cycle time, SCInCLK

c(ICLK)

-1) t

c(ICLK)

Pulse duration,

w(SCCL)

0.5t

c(SCC)

- t

0.5t

c(SCC)

+ 5

0.5t

c(SCC)

+0.5t

c(ICLK)

- t

0.5t

c(SCC)

+0.5t

c(ICLK)

SCInCLK low

Pulse duration,

w(SCCH)

0.5t

c(SCC)

- t

0.5t

c(SCC)

+ 5

0.5t

c(SCC)

-0.5t

c(ICLK)

- t

0.5t

c(SCC)

-0.5t

c(ICLK)

SCInCLK high

d(SCCH-

Delay time, SCInCLK

TXV)

high to SCInTX valid

Valid time, SCInTX

v(TX)

data after SCInCLK

c(SCC)

- 10

c(SCC)

- 10

low

su(RX-

Setup time, SCInRX

c(ICLK)

+ t

+ 20

c(ICLK)

+ t

+ 20

SCCL)

before SCInCLK low

Valid time, SCInRX

v(SCCL-RX)

data after SCInCLK

- t

c(ICLK)

+ t

+ 20

- t

c(ICLK)

+ t

+ 20

low

(1)

BAUD = 24-bit concatenated value formed by the SCI[H,M,L]BAUD registers.

(2)

c(ICLK)

= interface clock cycle time = 1/f

(ICLK)

(3)

For rise and fall timings, see the "switching characteristics for output timings versus load capacitance" table.

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SCIn ISOSYNCHRONOUS MODE TIMINGS EXTERNAL CLOCK

TIMING REQUIREMENTS FOR EXTERNAL CLOCK SCIn ISOSYNCHRONOUS MODE

(1) (2)

Data Valid

SCICLK

SCITX

SCIRX

TMS470R1A128
16/32-Bit RISC Flash Microcontrollers

SPNS098 JANUARY 2005

NO.

MIN

MAX

UNIT

c(SCC)

Cycle time, SCInCLK

(3)

c(ICLK)

w(SCCH)

Pulse duration, SCInCLK high

0.5t

c(SCC)

- 0.25t

c(ICLK)

0.5t

c(SCC)

+ 0.25t

c(ICLK)

w(SCCL)

Pulse duration, SCInCLK low

0.5t

c(SCC)

- 0.25t

c(ICLK)

0.5t

c(SCC)

+ 0.25t

c(ICLK)

d(SCCH-TXV)

Delay time, SCInCLK high to SCInTX valid

c(ICLK)

+ 12 + t

v(TX)

Valid time, SCInTX data after SCInCLK low

c(SCC)

-10

su(RX-SCCL)

Setup time, SCInRX before SCInCLK low

v(SCCL-RX)

Valid time, SCInRX data after SCInCLK low

c(ICLK)

+ 10

(1)

c(ICLK)

= interface clock cycle time = 1/f

(ICLK)

(2)

For rise and fall timings, see the "switching characteristics for output timings versus load capacitance" table.

(3)

When driving an external SCInCLK, the following must be true: t

c(SCC)

c(ICLK)

Data transmission/reception characteristics for isosynchronous mode with external clocking are similar to the
asynchronous mode. Data transmission occurs on the SCICLK rising edge, and data reception on the SCICLK falling
edge.

Figure 17. SCIn Isosynchronous Mode Timing Diagram for External Clock

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HIGH-END TIMER (HET) TIMINGS

minimum PWM output pulse width

minimum input pulses we can capture

STANDARD CAN CONTROLLER (SCC) MODE TIMINGS

DYNAMIC CHARACTERISTICS FOR THE CANSTX AND CANSRX PINS

MULTI-BUFFERED A-TO-D CONVERTER (MibADC)

TMS470R1A128

16/32-Bit RISC Flash Microcontrollers

SPNS098 JANUARY 2005

This is equal to one high resolution clock period (HRP). The HRP is defined by the 6-bit high resolution prescale
factor (hr), which is user defined, giving prescale factors of 1 to 64, with a linear increment of codes.

Therefore, the minimum PWM output pulse width = HRP(min) = hr(min)/SYSCLK = 1/SYSCLK

For example, for a SYSCLK of 30 MHz, the minimum PWM output pulse width = 1/30 = 33.33ns

The input pulse width must be greater than or equal to the low resolution clock period (LRP), i.e., the HET loop
(the HET program must fit within the LRP). The LRP is defined by the 3-bit loop-resolution prescale factor (lr),
which is user defined, with a power of 2 increment of codes. That is, the value of lr can be 1, 2, 4, 8, 16, or 32.

Therefore, the minimum input pulse width = LRP(min) = hr(min) * lr(min)/SYSCLK = 1 * 1/SYSCLK

For example, with a SYSCLK of 30 MHz, the minimum input pulse width = 1 * 1/30 = 33.33 ns

NOTE:

Once the input pulse width is greater than LRP, the resolution of the measurement is
still HRP. (That is, the captured value gives the number of HRP clocks inside the
pulse.)

Abbreviations:

hr = HET high resolution divide rate = 1, 2, 3,...63, 64

lr = HET low resolution divide rate = 1, 2, 4, 8, 16, 32

High resolution clock period = HRP = hr/SYSCLK

Loop resolution clock period = LRP = hr*lr/SYSCLK

PARAMETER

MIN

MAX

UNIT

(CANSTX)

Delay time, transmit shift register to CANSTX pin

(1)

(CANSRX)

Delay time, CANSRX pin to receive shift register

(1)

These values do not include the rise/fall times of the output buffer.

The multi-buffered A-to-D converter (MibADC) has a separate power bus for its analog circuitry that enhances
the A-to-D performance by preventing digital switching noise on the logic circuitry which could be present on
V

and V

from coupling into the A-to-D analog stage. All A-to-D specifications are given with respect to

REFLO

unless otherwise noted.

Resolution

10 bits (1024 values)

Monotonic

Assured

Output conversion code

00h to 3FFh [00 for V

REFLO

; 3FF for V

REFHI

]

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MibADC RECOMMENDED OPERATING CONDITIONS

(1)

OPERATING CHARACTERISTICS OVER FULL RANGES OF RECOMMENDED OPERATING

Parasitic
Capacitance

src

MibADC

Input Pin

Sample
Capacitor

leak

Sample Switch

External

TMS470R1A128
16/32-Bit RISC Flash Microcontrollers

SPNS098 JANUARY 2005

MIN

MAX

UNIT

REFHI

A-to-D high -voltage reference source

SSAD

CCAD

REFLO

A-to-D low-voltage reference source

SSAD

CCAD

Analog input voltage

SSAD

- 0.3

CCAD

+ 0.3

Analog input clamp current

(2)

AIC

-2

< V

SSAD

- 0.3 or V

> V

CCAD

+ 0.3)

(1)

For V

CCAD

and V

SSAD

recommended operating conditions, see the "device recommended operating conditions" table.

(2)

Input currents into any ADC input channel outside the specified limits could affect conversion results of other channels.

CONDITIONS

(1) (2)

PARAMETER

DESCRIPTION/CONDITIONS

MIN

TYP

MAX

UNIT

Analog input resistance

See Figure 18.

250

500

Conversion

Analog input capacitance

See Figure 18.

Sampling

AIL

Analog input leakage current

See Figure 18.

-1

µA

ADREFHI

REFHI

input current

REFHI

= 3.6 V, AD

REFLO

= V

SSAD

Conversion range over which specified

REFHI

- AD

REFLO

3.6

accuracy is maintained

Difference between the actual step width and the

DNL

Differential nonlinearity error

LSB

ideal value after offset correction. See Figure 19.

Maximum deviation from the best straight line
through the MibADC. MibADC transfer character-

INL

Integral nonlinearity error

LSB

istics, excluding the quantization error after offset
correction. See Figure 20.

Maximum value of the difference between an

TOT

Total error/Absolute accuracy

analog value and the ideal midstep value. See

LSB

Figure 20.

(1)

CCIO

= V

CCAD

= AD

REFHI

(2)

1 LSB = (AD

REFHI

- AD

REFLO

)/2

for the MibADC

Figure 18. MibADC Input Equivalent Circuit

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MULTI-BUFFER ADC (MibADC) TIMING REQUIREMENTS

0 ... 101

0 ... 100

0 ... 011

0 ... 010

0 ... 001

0 ... 000

0 ... 110

Analog Input Value (LSB)

1 LSB

0 ... 101

0 ... 100

0 ... 011

0 ... 010

0 ... 001

0 ... 000

0 ... 110

1 LSB

Differential Linearity
Error(- 1/2 LSB)

Differential Linearity
Error(1/2 LSB)

TMS470R1A128

16/32-Bit RISC Flash Microcontrollers

SPNS098 JANUARY 2005

MIN

MAX

UNIT

c(ADCLK)

Cycle time, MibADC clock

0.05

µs

d(SH)

Delay time, sample and hold time

µs

d(C)

Delay time, conversion time

0.55

µs

d(SHC)

(1)

Delay time, total sample/hold and conversion time

1.55

µs

(1)

This is the minimum sample/hold and conversion time that can be achieved. These parameters are dependent on many factors; for
more details, see the TMS470R1x Multi-Buffered Analog-to-Digital Converter (MibADC) Reference Guide (literature number SPNU206).

The differential nonlinearity error shown in Figure 19 (sometimes referred to as differential linearity) is the
difference between an actual step width and the ideal value of 1 LSB.

1 LSB = (AD

REFH

I - AD

REFLO

)/2

Figure 19. Differential Nonlinearity (DNL)

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Analog Input Value (LSB)

At Transition
011/100
( 1/2 LSB)

End-Point Lin. Error

At Transition
001/010 ( 1/4 LSB)

Ideal

Transition

Actual

Transition

0 ... 101

0 ... 100

0 ... 011

0 ... 010

0 ... 001

0 ... 111

0 ... 110

0 ... 000

0 ... 101

0 ... 100

0 ... 011

0 ... 010

0 ... 001

0 ... 000

0 ... 111

0 ... 110

Analog Input Value (LSB)

Total Error
At Step 0 ... 101
(-1 1/4 LSB)

Total Error
At Step 0 ... 001
(1/2 LSB)

TMS470R1A128
16/32-Bit RISC Flash Microcontrollers

SPNS098 JANUARY 2005

The integral nonlinearity error shown in Figure 20 (sometimes referred to as linearity error) is the deviation of the
values on the actual transfer function from a straight line.

1 LSB = (AD

REFH

I - AD

REFLO

)/2

Figure 20. Integral Nonlinearity (INL) Error

The absolute accuracy or total error of an MibADC as shown in Figure 21 is the maximum value of the difference
between an analog value and the ideal midstep value.

1 LSB = (AD

REFH

I - AD

REFLO

)/2

Figure 21. Absolute Accuracy (Total) Error

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Part Number TMS470R1A128

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