TLV320AIC12, TLV320AIC13
TLV320AIC14, TLV320AIC15, TLV320AIC20
TLV320AIC21, TLV320AIC24, TLV320AIC25
OCTOBER 2003
PRODUCT NOTIFICATION
DEVICE
LITERATURE NO.
TLV320AIC12
SLWS115
TLV320AIC13
SLWS139
TLV320AIC14
SLWS140
TLV320AIC15
SLWS141
TLV320AIC20
SLAS363
TLV320AIC21
SLAS365
TLV320AIC24
SLAS366
TLV320AIC25
SLAS367
Texas Instruments (TI) has recently identified a problem in the product models listed above related to DLL
clock-generation. When a clock-generation mode is used that powers up the delay-locked-loop (DLL), the DLL
may not startup properly when initiated, resulting in the audio master clock not functioning. This results in the
codec in the products not functioning. This issue does not affect applications that do not enable the product's
DLL.
Since this issue does not affect operation if the DLL is not enabled, customers are recommended to ensure their
system does not enable the product's DLL. The DLL is enabled anytime the P value in control register #4
(pertaining to clock generation) is NOT set equal to 8. The DLL is used whenever the part is in fine sampling
mode, as described in Section 3.1 of the data manual, so the recommended mode to use is the coarse sampling
mode, which requires P=8.
At present, TI does not have a screening procedure in place to detect product with the DLL issue, but the
company also realizes that many customers do not use the DLL in their systems and will be unaffected by this
issue.
TI is not confident of the operation of the DLL in this product at this time. To ensure customers have been made
aware of this issue, orders for these parts will only be filled upon return of a signed waiver until this issue is
resolved. The company has initiated an investigation to fully understand the root cause of this problem and
determine what appropriate long-term corrective action should be taken. TI recommends that all customers
presently using these parts contact the company immediately, so they can receive updates on this investigation
and plans for its resolution.
We apologize for the inconvenience placed upon customers in ordering this product. However, we wish to
ensure that our customers are aware of the device shortcomings from the specification. We are working in
earnest to remove this waiver requirement.
For further information, please contact
Neeraj Magotra
WW Strategic Marketing Manager for Voice/Audio Systems
Office: (214) 480 - 7486
nmagotra@ti.com
www.ti.com
Copyright
2003, Texas Instruments Incorporated
TLV320AIC14
Low Power CMOS, 16 Bit, 26 KSPS Codec With
Smart Time Division Multiplexed (SMARTDM
)
Serial Port
May 2002
HPA Data Acquisition
Data Manual
SLWS140A
IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications,
enhancements, improvements, and other changes to its products and services at any time and to discontinue
any product or service without notice. Customers should obtain the latest relevant information before placing
orders and should verify that such information is current and complete. All products are sold subject to TI's terms
and conditions of sale supplied at the time of order acknowledgment.
TI warrants performance of its hardware products to the specifications applicable at the time of sale in
accordance with TI's standard warranty. Testing and other quality control techniques are used to the extent TI
deems necessary to support this warranty. Except where mandated by government requirements, testing of all
parameters of each product is not necessarily performed.
TI assumes no liability for applications assistance or customer product design. Customers are responsible for
their products and applications using TI components. To minimize the risks associated with customer products
and applications, customers should provide adequate design and operating safeguards.
TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right,
copyright, mask work right, or other TI intellectual property right relating to any combination, machine, or process
in which TI products or services are used. Information published by TI regarding thirdparty products or services
does not constitute a license from TI to use such products or services or a warranty or endorsement thereof.
Use of such information may require a license from a third party under the patents or other intellectual property
of the third party, or a license from TI under the patents or other intellectual property of TI.
Reproduction of information in TI data books or data sheets is permissible only if reproduction is without
alteration and is accompanied by all associated warranties, conditions, limitations, and notices. Reproduction
of this information with alteration is an unfair and deceptive business practice. TI is not responsible or liable for
such altered documentation.
Resale of TI products or services with statements different from or beyond the parameters stated by TI for that
product or service voids all express and any implied warranties for the associated TI product or service and
is an unfair and deceptive business practice. TI is not responsible or liable for any such statements.
Mailing Address:
Texas Instruments
Post Office Box 655303
Dallas, Texas 75265
Copyright
2002, Texas Instruments Incorporated
v
Contents
Section
Title
Page
1
Introduction
11
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.1
Description
11
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.2
Features
11
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.3
Functional Block Diagram
13
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2
Terminal Descriptions
21
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.1
Ordering Information
21
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.2
Terminal Functions
21
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.3
Definitions and Terminology
22
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3
Functional Description
31
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.1
Operating Frequencies
31
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.2
Internal Architecture
31
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.2.1
Antialiasing Filter
31
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.2.2
Sigma-Delta ADC
31
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.2.3
Decimation Filter
31
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.2.4
Sigma-Delta DAC
32
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.2.5
Interpolation Filter
32
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.2.6
Analog/Digital/Side-Tone Loopback
32
. . . . . . . . . . . . . . . . . . .
3.2.7
ADC PGA
32
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.2.8
DAC PGA
32
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.3
Analog Input/Output
32
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.3.1
MIC Input
32
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.3.2
INP and INM Input
33
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.3.3
Single-Ended Analog Input
33
. . . . . . . . . . . . . . . . . . . . . . . . . . .
3.3.4
Analog Output
34
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.4
IIR/FIR Control
34
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.4.1
Overflow Flags
34
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.4.2
IIR/FIR Bypass Mode
34
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.5
System Reset and Power Management
34
. . . . . . . . . . . . . . . . . . . . . . . .
3.5.1
Software and Hardware Reset
34
. . . . . . . . . . . . . . . . . . . . . . . .
3.5.2
Power Management
35
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.6
Digital Interface
35
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.6.1
Clock Source (MCLK, SCLK)
35
. . . . . . . . . . . . . . . . . . . . . . . . .
3.6.2
Serial Data Out (DOUT)
35
. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.6.3
Serial Data In (DIN)
36
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.6.4
Frame-Sync FS
36
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.6.5
Cascade Mode and Frame-Sync Delayed (FSD)
36
. . . . . . . .
3.6.6
Stand-Alone Slave
36
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.6.7
Asynchronous Sampling (Codecs in cascade
are sampled at different sampling frequency)
36
. . . . . . . . . . .
vi
3.7
Host Port Interface
38
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.7.1
S
2
C (Start-Stop Communication)
39
. . . . . . . . . . . . . . . . . . . . .
3.7.2
I
2
C
39
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.8
Smart Time Division Multiplexed Serial Port (SMARTDM)
311
. . . . . . . . .
3.8.1
Programming Mode
311
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.8.2
Continuous Data Transfer Mode
312
. . . . . . . . . . . . . . . . . . . . . .
3.8.3
Turbo Mode (SCLK)
313
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.9
Control Register Programming
314
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.9.1
Data Frame Format
315
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.9.2
Control Frame Format (Programming Mode)
315
. . . . . . . . . . .
3.9.3
Broadcast Register Write
315
. . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.9.4
Register Map
316
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4
Control Register Content Description
41
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.1
Control Register 1
41
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.2
Control Register 2
42
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.3
Control Register 3
42
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.4
Control Register 4
43
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.5
Control Register 5A
43
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.6
Control Register 5B
45
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.7
Control Register 5C
47
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.8
Control Register 5D
47
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.9
Control Register 6
48
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5
Electrical Characteristics
51
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.1
Absolute Maximum Ratings Over Operating Free-Air
Temperature Range
51
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.2
Recommended Operating Conditions
51
. . . . . . . . . . . . . . . . . . . . . . . . . .
5.3
Electrical Characteristics Over Recommended Operating
Free-Air Temperature Range, AV
DD
= 3.3 V,
DV
DD
= 1.8 V, IOV
DD
= 3.3 V
52
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.3.1
Digital Inputs and Outputs, f
s
= 8 kHz,
Outputs Not Loaded
52
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.4
ADC Path Digital Filter, f
s
= 8 kHz
52
. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.4.1
FIR Filter
52
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.4.2
IIR Filter
52
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.5
ADC Dynamic Performance, f
s
= 8 kHz
53
. . . . . . . . . . . . . . . . . . . . . . . . .
5.5.1
ADC Signal-to-Noise
53
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.5.2
ADC Signal-to-Distortion
53
. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.5.3
ADC Signal-to-Distortion + Noise
53
. . . . . . . . . . . . . . . . . . . . .
5.5.4
ADC Channel Characteristics
53
. . . . . . . . . . . . . . . . . . . . . . . .
5.6
DAC Path Digital Filter, fs = 8 kHz
54
. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.6.1
FIR Filter
54
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.6.2
IIR Filter
54
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.7
DAC Dynamic Performance
54
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.7.1
OUTP/OUTM Signal-to-Noise When Load Is 600
54
. . . . .
5.7.2
OUTP/OUTM Signal-to-Distortion When Load Is 600
54
. .
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