TL16PNP550A
ASYNCHRONOUS COMMUNICATIONS ELEMENT
WITH PLUG-AND-PLAY (PnP) AND AUTOFLOW CONTROL
SLLS190B MARCH 1995 REVISED MARCH 1996
1
POST OFFICE BOX 655303
·
DALLAS, TEXAS 75265
D
PnP Card Autoconfiguration Sequence
Compliant
D
External Terminal-to-Bypass PnP
Autoconfiguration Sequence
D
In UART Bypass Mode, the Stand-Alone
PnP Controller is Configured With One
Logical Device
D
Provides 10-Interrupts IRQ3 IRQ7,
IRQ9 IRQ12, IRQ15
D
Simple 3-Pin Interface to SGS-Thomson
TM
EEPROM 2K/4K ST93C56/66
D
High Output Current Drive. No External
Buffer Needed for Data and Interrupt
Signals
D
Programmable Auto-RTS and Auto-CTS
D
In Auto-CTS Mode, CTS Controls
Transmitter
D
In Auto-RTS Mode, Receiver FIFO Contents
and Threshold Control RTS
D
The Serial and Modem Control Outputs
Drive a 1-Meter RJ11 Cable Directly if
Equipment Is on the Same Power Drop
D
Capable of Running With All Existing
TL16C450 Software
D
After Reset, All Registers Are Identical to
the TL16C450 Register Set
D
Clock Prescalar Allows 22-MHz Oscillator
Clock to be Divided by 12, 6, 3, or 1
D
In the TL16C450 Mode, Hold and Shift
Registers Eliminate the Need for Precise
Synchronization Between the CPU and
Serial Data
D
Programmable Baud Rate Generator Allows
Division of Any Input Reference Clock by 1
to (2
16
1) and Generates an Internal 16
×
Clock
D
On-Chip I/O Port Address Decoding
D
In PnP Bypass Mode, 6 External Terminals
Configure the I/O Base Address and
Interrupt Mapping
D
Adds or Deletes Standard Asynchronous
Communication Bits (Start, Stop, and
Parity) to or From the Serial Data Stream
D
Independent Control of Transmit, Receive,
Line Status, and Data Set Interrupts on
Each Channel
D
Programmable Serial Interface
Characteristics:
5-, 6-, 7-, or 8-Bit Characters
Even-, Odd-, or No-Parity-Bit Generation
and Detection
1-, 1 1/2-, or 2-Stop Bit Generation
Baud Generation (DC to 1 Mbit Per
Second)
D
False Start Bit Detection
D
Complete Status Reporting Capabilities
D
3-State Outputs Provide TTL Drive for
Bidirectional Data Bus and Interrupt Lines
D
Line Break Generation and Detection
D
Internal Diagnostic Capabilities:
Loopback Controls for Communications
Link Fault Isolation
Break, Parity, Overrun, and Framing
Error Simulation
D
Fully Prioritized Interrupt System Controls
D
Modem Control Functions (CTS, RTS, DSR,
DTR, RI, and DCD)
D
Transmitter and Receiver Run at the Same
Speed
D
Up to 16-MHz Clock Rate for Up to 1-Mbaud
Operation for the Internal ACE
D
Available in 68-Pin PLCC
description
The TL16PNP550A is a functional upgrade of the TL16C550C asynchronous communications element (ACE),
which in turn is a functional upgrade of the TL16C450. Functionally equivalent to the TL16C450 on power up
(character or TL16C450 mode), the TL16PNP550A, like the TL16C550C, can be placed in an alternate mode
(FIFO mode). This relieves the CPU of excessive software overhead by buffering received and transmitted
characters. The receiver and transmitter FIFOs store up to 16 bytes including three additional bits of error status
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright
©
1996, Texas Instruments Incorporated
SGS-Thomson is a trademark of SGS-Thomson Incorporated.
TL16PNP550A
ASYNCHRONOUS COMMUNICATIONS ELEMENT
WITH PLUG-AND-PLAY (PnP) AND AUTOFLOW CONTROL
SLLS190B MARCH 1995 REVISED MARCH 1996
2
POST OFFICE BOX 655303
·
DALLAS, TEXAS 75265
description (continued)
per byte for the receiver FIFO. In the FIFO mode, there is a selectable autoflow control feature that can
significantly reduce software overload and increase system efficiency by automatically controlling serial data
flow using RTS output and CTS input signals.
The TL16PNP550A responds to the plug-and-play (PnP) autoconfiguration process. The autoconfiguration
process puts all PnP cards in a configuration mode, isolates one PnP card at a time, assigns a card select
number (CSN), and reads the card resource data structure from the EEPROM. After the resource requirements
and capabilities are determined for all cards, the autoconfiguration process uses the CSN to configure the card
by writing to the configuration registers. The TL16PNP550A only implements configuration registers for I/O
applications with one logical device and no direct memory access (DMA) support. Finally, the process activates
the TL16PNP550A card and removes it from configuration mode. After the configuration process, the ACE starts
responding to industry standard architecture (ISA) bus cycles. This device can also be configured to bypass
the PnP autoconfiguration sequence. In this mode the TL16PNP500A can be configured to select the COM port
address and IRQ level. In the UART bypass mode, the UART is disabled and this device is configured to be a
stand-alone PnP controller that supports one logical device and no DMA support.
The TL16PNP550A performs serial-to-parallel conversion on data received from a peripheral device or modem
and parallel-to-serial conversion on data received from its CPU. The CPU can read and report on the status of
the ACE operation. Reported status information includes the type of transfer operation in progress, the status
of the operation, and any error conditions encountered.
The TL16PNP550A includes a clock prescalar that divides the 22-MHz input clock by 12, 6, 3, or 1. The prescalar
output clock is fed to the programmable baud rate generator, which is capable of dividing this clock by divisors
from 1 to (2
16
1).
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