TL16PC564B, TL16PC564BLV
PCMCIA UNIVERSAL ASYNCHRONOUS RECEIVER TRANSMITTER
SLLS225A MARCH 1996 REVISED FEBRUARY 1998
1
POST OFFICE BOX 655303
·
DALLAS, TEXAS 75265
D
Integrated Asynchronous Communications
Element (ACE) Compatible With PCMCIA
PC Card Standard Release 2.01
D
Consists of a Single TL16C550 ACE Plus
PCMCIA Interface Logic
D
Provides Common I-Bus/Z-Bus
Microcontroller Inputs for Most Intel
TM
and
Zilog
TM
Subsystems
D
Fully Programmable 256-Byte Card
Information Structure (CIS) and 8-Byte Card
Configuration Register (CCR)
D
Adds or Deletes Standard Asynchronous
Communication Bits (Start, Stop and
Parity) to or From Serial Data Stream
D
Independently Controlled Transmit,
Receive, Line Status, and Data Set
Interrupts
D
Subsystem Selectable Serial-Bypass Mode
Provides Subsystem With Direct Parallel
Access to the FIFOs
D
Fully Programmable Serial-Interface
Characteristics:
5-, 6-, 7-, or 8-Bit Characters
Even-, Odd-, or No-Parity Bit Generation
and Detection
1-, 1 1/2-, or 2-Stop Bit Generation
Baud-Rate Generation
D
Fully Prioritized Interrupt System Controls
D
Modem Control Functions
D
Provides TL16C450 Mode at Reset Plus
Selectable Normal TL16C550 Operation or
Extended 64-Byte FIFO Mode
D
Selectable Auto-RTS Mode Deactivates
RTS at 14 Bytes in 550 Mode and at
56 Bytes in Extended 550 Mode
D
Selectable Auto-CTS Mode Deactivates
Serial Transfers When CTS is Inactive
D
Available in 100 Pin Thin Quad Flatpack
(PZ) Package
description
The TL16PC564B/BLV
is designed to provide all the functions necessary for a Personal Computer Memory
Card International Association (PCMCIA) universal asynchronous receiver transmitter (UART) subsystem
interface. This interface provides a serial-to-parallel conversion for data to and from a modem
coder-decoder/digital signal processor (CODEC/DSP) function to a PCMCIA parallel data-port format. A
computer central processing unit (CPU), through a PCMCIA host controller, can read the status of the
asynchronous communications element (ACE) interface at any point in the operation. Reported status
information includes the type of transfer operation in process, the status of the operation, and any error
conditions encountered.
Attribute memory consists of a 256-byte card information structure (CIS) and eight 8-byte card configuration
registers (CCR). The CIS, implemented with a dual-port random-access memory (DPRAM), is available to both
the host CPU and subsystem (modem), as are the CCRs. This DPRAM is used in place of the electrically
erasable programmable read-only memory (EEPROM) normally used for the CIS. At power up, attribute
memory is initialized by the subsystem.
The TL16PC564B/BLV uses a TL16C550 ACE-type core with an expanded 64
×
11 receiver first-in-first-out
(FIFO) memory and a 64
×
8 transmitter FIFO memory. The receiver trigger logic flags have been adjusted in
order to take full advantage of the increased capacity when in the extended mode. In addition, eight of the UART
registers have been mapped into the subsystem (modem) memory space as read-only registers. This allows
the subsystem to read UART status information.
A subsystem-selectable serial-bypass mode has been implemented to allow the subsystem to bypass the serial
portion of the UART and write directly to the receiver FIFO and read directly from the transmitter FIFO. Interrupt
operation is not affected in this mode.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Intel is a registered trademark of Intel System, Inc.
Zilog is a registered trademark of Zilog Incorporated
Patent pending
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright
©
1998, Texas Instruments Incorporated
TL16PC564B, TL16PC564BLV
PCMCIA UNIVERSAL ASYNCHRONOUS RECEIVER TRANSMITTER
SLLS225A MARCH 1996 REVISED FEBRUARY 1998
2
POST OFFICE BOX 655303
·
DALLAS, TEXAS 75265
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
HD2
STSCHG
REG
INPACK
GND
GND
RESET
GND
SA7
IOWR
IORD
CE2
SA6
SA5
SA4
SA2
SA1
GND
SA0
UARTCLK
EXTEND
SSAB
GND
ARBCLKI
GND
ARBCLKO
ARBPGM0
ARBPGM1
RST
NANDOUT
SAD7
SAD6
GND
SAD5
SAD4
SAD3
SAD2
SAD1
SA8
SAD0
HD3
HD4
HD5
HD6
HD7
CE1
OE
HA9
WE
IREQ
HA6
HA5
HA4
HA3
HA2
GND
HA1
HA0
HD0
HD1
ALE (AS)
IRQ
SELZ/I
RD(DS)
GND
WR(R/W)
CS
DTR
RT
S
OUT1
BAUDOUT
GND
RCLK
GND
GND
OUT2
DSR
DCD
CTS
RI
V
CC
CC
V
CC
V
XIN
CC
V
PZ PACKAGE
(TOP VIEW)
VTEST
GND
V
CC
HA7
GND
HA8
TESTOUT
V
CC
SA3
SIN
CC
V
SOUT
V
CC
The terminal names not enclosed in parentheses correspond to an Intel microcontroller signal, and the terminal
names enclosed in parentheses correspond to a Zilog microcontroller signal.
V
CC
V
CC
TL16PC564B, TL16PC564BLV
PCMCIA UNIVERSAL ASYNCHRONOUS RECEIVER TRANSMITTER
SLLS225A MARCH 1996 REVISED FEBRUARY 1998
3
POST OFFICE BOX 655303
·
DALLAS, TEXAS 75265
block diagram
SELZ / I
Reset
Reset
Reset
Reset
Reset
Host CPU
Control
Logic
Control
ARBCLKO
INPACK
STSCHG
UARTCLK
IREQ
IRQ
BAUDOUT
DTR
RTS
OUT2
OUT1
SOUT
Attribute
Memory
(CIS 256
×
8,
CCR 8
×
8
plus arbitration
logic)
UART
TL16C550C
Subsystem
Control
Logic
Divide by N
Master Clock
UART Select
OE
WE
DATA
ADDR
HA9 HA0
REG
WE
CE2
CE1
OE
IORD
SAD7 SAD0
SA8SA0
WR(R/W)
ALE(AS)
RD(DS)
CS
ARBCLKI
ARBPGM1
ARBPGM0
SIN
RCLK
DCD
CTS
DSR
RI
XIN
EXTEND
IOWR
HD7 HD0
95, 96, 98 100, 75 77
92, 90, 87, 85 81,
79, 78
73
94
62
89
93
63
5
9,8
14, 15, 17 20,
23, 25
24,65,61,
59 55,53
28
26
31
29
32
33
40
49
48
46
64
1
42
50
7
71
74
27
88
51
38
34
37
44
35
45
8
10
10
10
8
2
8
8
6
Reset
Validation
RESET
67
SSAB
3
RST
11
DATA
ADDR
OE
WE
9
9
Bit 0 is the least significant bit.
TL16PC564B, TL16PC564BLV
PCMCIA UNIVERSAL ASYNCHRONOUS RECEIVER TRANSMITTER
SLLS225A MARCH 1996 REVISED FEBRUARY 1998
4
POST OFFICE BOX 655303
·
DALLAS, TEXAS 75265
Terminal Functions
TERMINAL
INTER-
I/O
DESCRIPTION
NAME
NO.
INTER
FACE
I/O
DESCRIPTION
ALE (AS)
26
S
I
Address-latch enable/address strobe. ALE(AS) is an address-latch enable in the Intel mode
and an address strobe in the Zilog mode. ALE (AS) is active high for an Intel subsystem and
active low for a Zilog subsystem.
ARBCLKO
7
M
O
Arbitration clock output. ARBCLKO is equal to the input on ARBCLKI divided by the
binary-coded divisor input on ARBPGM (1 0).
ARBCLKI
5
M
I
Arbitration clock input. ARBCLKI is the base clock used in arbitration for the attribute memory
DRAM and the reset validation circuitry.
ARBPGM0
ARBPGM1
8
9
M
I
Arbitration clock divisor program. These two bits set the divisor for ARBCLKI. Divide by 1, 2,
4, and 8 are available.
BAUDOUT
38
U
O
Baud output. BAUDOUT is an active-low 16
×
signal for the transmitter section of the UART.
The clock rate is established by the reference clock (UARTCLK) frequency divided by a divisor
specified by the baud generator divisor latches. BAUDOUT may also be used for the receiver
section by tying this output to the RCLK input.
CE1
CE2
94
62
H
I
Card enable 1 and card enable 2 are active-low signals. CE1 enables even-numbered
address bytes, and CE2 enables odd-numbered address bytes. A multiplexing scheme based
on HA0, CE1, and CE2 allows an 8-bit host to access all data on HD0 through HD7 if desired.
These signals have internal pullup resistors.
CS
32
S
I
Chip select. CS is the active-low chip select from the Zilog or Intel microcontroller.
CTS
49
U
I
Clear to send. CTS is an active-low modem status signal whose condition can be checked by
reading bit 4 (CTS) of the modem status register (MSR). Bit 0 (delta clear to send) of the MSR
indicates that the signal has changed states since the last read from the MSR. If the
modem-status interrupt is enabled when CTS changes states, an interrupt is generated.
DCD
48
U
I
Data carrier detect. DCD is an active-low modem-status signal whose condition can be
checked by reading bit 7 (DCD) of the MSR. Bit 3 (delta data carrier detect) of the MSR
indicates that the signal has changed states since the last read from the MSR. If the
modem-status interrupt is enabled when DCD changes states, an interrupt is generated.
DSR
46
U
I
Data set ready. DSR is an active-low modem status signal whose condition can be checked
by reading bit 5 (DSR) of the MSR. Bit 1 (delta data set ready) of the MSR indicates that the
signal has changed states since the last read from the MSR. If the modem-status interrupt is
enabled when DSR changes states, an interrupt is generated.
DTR
34
U
O
Data terminal ready. DSD is an active-low signal. When active, DTR informs the modem or
data set that the UART is ready to establish communication. DTR is placed in the active state
by setting the DTR bit 0 of the modem control register (MCR) to a high level. DTR is placed
in the inactive state either as a result of a reset, doing a loop-mode operation, or resetting bit
0 (DTR) of the MCR.
EXTEND
1
U
I
FIFO extend. When EXTEND is high, the UART is configured as a standard TL16C550 with
16-byte transmit and receive FIFOs. When EXTEND is low and FIFO control register (FCR)
bit 5 is high, the FIFOs are extended to 64 bytes and the receiver-interrupt trigger levels adjust
accordingly. EXTEND low in conjunction with FIFO control register (FCR) bit 4 set high
enables the auto-RTS function.
GND
4, 6, 13,16,30,
39,41, 43, 54,
66, 68, 69,80, 91
M
Common ground
Host = H, Subsystem = S, UART = U, Miscellaneous = M
TL16PC564B, TL16PC564BLV
PCMCIA UNIVERSAL ASYNCHRONOUS RECEIVER TRANSMITTER
SLLS225A MARCH 1996 REVISED FEBRUARY 1998
5
POST OFFICE BOX 655303
·
DALLAS, TEXAS 75265
Terminal Functions
TERMINAL
INTER-
I/O
DESCRIPTION
NAME
NO.
INTER
FACE
I/O
DESCRIPTION
HA0
HA1
HA2
HA3
HA4
HA5
HA6
HA7
HA8
HA9
78
79
81
82
83
84
85
87
90
92
H
I
The 10-bit address bus addresses the attribute memory (bits 1 8) and addresses the internal
UART as either PCMCIA I/O (bits 0 2) or as a standard COM port (bits 0 9).
HD0
HD1
HD2
HD3
HD4
HD5
HD6
HD7
77
76
75
100
99
98
96
95
H
I/O
The 8-bit bidirectional data bus transfers data to and from the attribute memory and the internal
UART.
INPACK
71
H
O
Input port acknowledge. INPACK is an active-low output signal that is asserted when the card
responds to an I/O read cycle at the address on the HA bus.
IORD
63
H
I
I/O read strobe. IORD is an active-low input signal activated to read data from the card I/O space.
The REG signal and at least one of the card enable inputs (CE1, CE2) must also be active for the
I/O transfer to take place. This signal has an internal pullup resistor.
IOWR
64
H
I
I/O write strobe. IORW is an active-low input signal activated to write data to the card I/O space.
The REG signal and at least one of the card enable inputs (CE1, CE2) must also be active for the
I/O transfer to take place. This signal has an internal pullup resistor.
IREQ
88
H
O
Interrupt request. IREQ is an active-low output signal asserted by the card to indicate to the host
CPU that a card device requires host software service. This signal doubles as READY/BUSY
during power-up initialization.
IRQ
27
S
O
Interrupt request. This active-high IRQ to the subsystem indicates a host CPU write to attribute
memory has occurred.
NANDOUT
12
M
O
This is a production test output.
OE
93
H
I
Output enable. OE is an active-low input signal used to gate memory read data from the card. This
signal has an internal pullup resistor.
OUT1
OUT2
37
44
U
O
Output 1 and output 2 are active-low signals. OUT1 and OUT2 are user-defined output terminals
that are set to their active state by setting respective MCR bits (OUT1 and OUT2) high. OUT1 and
OUT2 are set to their inactive (high) state as a result of a reset, doing loop-mode operation, or by
resetting bit 2 (OUT1) or bit 3 (OUT2) of the MCR. This signal has an open-drain outputs.
RCLK
40
U
I
Receiver clock. RCLK is the 16
×
-baud-rate clock input for the receiver section of the UART.
RD(DS)
29
S
I
Read enable or data strobe input. RD(DS) is the active-low read enable in the Intel mode and the
active-low data strobe in the Zilog mode.
REG
73
H
I
Attribute memory select. This active-low input signal is generated by the host CPU and accesses
attribute memory (OE and WE active) and I/O space (IORD or IOWR active). PCMCIA common
memory access is excluded. This signal has an internal pullup resistor and hysteresis on the input
buffer.
RESET
67
H
I
Reset. RESET is an active-high input that serves as the master reset for the device. RESET clears
the UART, placing the card in an unconfigured state. This signal has an internal pullup resistor.
RI
50
U
I
Ring indicator. RI is an active-low modem status signal whose condition can be checked by reading
bit 6 (RI) of the MSR. The trailing-edge ring indicator (TERI) bit 2 of the MSR indicates that RI has
transitioned from a low to a high state since the last read from the MSR. If the modem status
interrupt is enabled when this transition occurs, an interrupt is generated.
Host = H, Subsystem = S, UART = U, Miscellaneous = M
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