TL16C752B

3.3-V DUAL UART WITH 64-BYTE FIFO

SLLS405 DECEMBER 1999

POST OFFICE BOX 655303

DALLAS, TEXAS 75265

Pin Compatible With ST16C2550 With
Additional Enhancements

Up to 1.5 Mbps Baud Rate When Using
Crystal (24 MHz Input Clock)

Up to 2.25 Mbps Baud Rate When Using
Oscillator or Clock Source (36 MHz Input
Clock)

64-Byte Transmit FIFO

64-Byte Receive FIFO With Error Flags

Programmable and Selectable Transmit and
Receive FIFO Trigger Levels for DMA and
Interrupt Generation

Programmable Receive FIFO Trigger Levels
for Software/Hardware Flow Control

Software/Hardware Flow Control
Programmable Xon/Xoff Characters
Programmable Auto-RTS and Auto-CTS

Optional Data Flow Resume by Xon Any
Character

DMA Signalling Capability for Both
Received and Transmitted Data

Supports 3.3-V Operation

Software Selectable Baud Rate Generator

Prescaler Provides Additional Divide By 4
Function

Fast Access Time 2 Clock Cycle IOR/IOW
Pulse Width

Programmable Sleep Mode

Programmable Serial Interface
Characteristics
5, 6, 7, or 8 Bit Characters
Even, Odd, or No Parity Bit Generation

and Detection

 1, 1.5, or 2 Stop Bit Generation

False Start Bit Detection

Complete Status Reporting Capabilities in
Both Normal and Sleep Mode

Line Break Generation and Detection

Internal Test and Loopback Capabilities

Fully Prioritized Interrupt System Controls

Modem Control Functions (CTS, RTS, DSR,
DTR, RI, and CD)

14 15

RESET
DTRB
DTRA
RTSA
OPA
RXRDYA
INTA
INTB
A0
A1
A2
NC

D5
D6
D7

RXB
RXA

TXRDYB

TXA
TXB

OPB

CSA
CSB

17 18 19 20

RIA

CDA

DSRA

CTSA

47 46 45 44 43

TSB

CTSB

IOW

GND

RXRDYB

IOR

DSRB

RIB

40 39 38

21 22 23 24

TXRDY

AL2

AL1

CDB

PACKAGE

(TOP VIEW)

NC No internal connection

PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

1999, Texas Instruments Incorporated

TL16C752B
3.3-V DUAL UART WITH 64-BYTE FIFO

SLLS405 DECEMBER 1999

POST OFFICE BOX 655303

DALLAS, TEXAS 75265

description

The TL16C752B is a dual universal asynchronous receiver/transmitter (UART) with 64-byte FIFOs, automatic
hardware/software flow control, and data rates up to 3.125 Mbps. The TL16C752B offers enhanced features.
It has a transmission control register (TCR) that stores received FIFO threshold level to start/stop transmission
during hardware and sofware flow control. With the FIFO RDY register, the software gets the status of
TXRDY/RXRDY for all four ports in one access. On-chip status registers provide the user with error indications,
operational status and modem interface control. System interrupts may be tailored to meet user requirements.
An internal loopback capability allows onboard diagnostics.

The UART transmits data sent to it from the peripheral 8-bit bus on the TX signal and receives characters on
the RX signal. Characters can be programmed to be 5, 6, 7, or 8 bits. The UART has a 64-byte receive FIFO
and transmit FIFO and can be programmed to interrupt at different trigger levels. The UART generates its own
desired baud rate based upon a programmable divisor and its input clock. It can transmit even, odd, or no parity
and 1, 1.5, or 2 stop bits. The receiver can detect break, idle, or framing errors, FIFO overflow, and parity errors.
The transmitter can detect FIFO underflow. The UART also contains a software interface for modem control
operations, and has software flow control and hardware flow control capabilities.

The TL16C752B is available in a 48-pin PT (LQFP) package. The 48-pin version offers three state interrupt
control and provides constant active interrupt outputs.

Terminal Functions

TERMINAL

I/O

DESCRIPTION

NAME

NO.

I/O

DESCRIPTION

Address 0 select bit. Internal registers address selection

Address 1 select bit. Internal registers address selection

Address 2 select bit. Internal registers address selection

CDA, CDB

40, 16

Carrier detect (active low). These inputs are associated with individual UART channels A and B. A low on
these pins indicates that a carrier has been detected by the modem for that channel.

CSA, CSB

10, 11

Chip select A and B (active low). These pins enable data transfers between the user CPU and the TL16C752B
for the channel(s) addressed. Individual UART sections (A, B) are addressed by providing a low on the
respective CS A and CS B pins.

CTSA, CTSB

38, 23

Clear to send (active low). These inputs are associated with individual UART channels A and B. A logic low
on the CTS pins indicates the modem or data set is ready to accept transmit data from the 752B. Status can
be tested by reading MSR bit 4. These pins only affect the transmit and receive operations when auto CTS
function is enabled through the enhanced feature register (EFR) bit 7, for hardware flow control operation.

D0D4
D5D7

4448,

I/O

Data bus (bidirectional). These pins are the eight bit, 3-state data bus for transferring information to or from
the controlling CPU. D0 is the least significant bit and the first data bit in a transmit or receive serial data
stream.

DSRA, DSRB

39, 20

Data set ready (active low). These inputs are associated with individual UART channels A and B. A logic low
on these pins indicates the modem or data set is powered on and is ready for data exchange with the UART.

DTRA, DTRB

34, 35

Data terminal ready (active low). These outputs are associated with individual UART channels A and B. A
logic low on these pins indicates that the 752B is powered on and ready. These pins can be controlled through
the modem control register. Writing a 1 to MCR bit 0 sets the DTR output to low, enabling the modem. The
output of these pins is high after writing a 0 to MCR bit 0, or after a reset.

GND

Pwr

Signal and power ground

INTA, INTB

30, 29

Interrupt A and B (active high). These pins provide individual channel interrupts, INT A and B. INT A and B
are enabled when MCR bit 3 is set to a logic 1, interrupts are enabled in the interrupt enable register (IER),
and when an interrupt condition exists. Interrupt conditions include: receiver errors, available receiver buffer
data, transmit buffer empty, or when a modem status flag is detected. INTAB are in the high-impedance state
after reset.

IOR

Read input (active low strobe). A high to low transition on IOR will load the contents of an internal register
defined by address bits A0A2 onto the TL16C752B data bus (D0D7) for access by an external CPU.

TL16C752B

3.3-V DUAL UART WITH 64-BYTE FIFO

SLLS405 DECEMBER 1999

POST OFFICE BOX 655303

DALLAS, TEXAS 75265

Terminal Functions (Continued)

TERMINAL

I/O

DESCRIPTION

NAME

NO.

I/O

DESCRIPTION

IOW

Write input (active low strobe). A high to low transition on IOW will transfer the contents of the data bus (D0D7)
from the external CPU to an internal register that is defined by address bits A0A2 and CSA and CSB

OPA, OPB

32, 9

User defined outputs. This function is associated with individual channels A and B. The state at these pins is
defined by the user and through the software settings of the MCR register, bit 3. INTAB are set to active mode
and OP to a logic 0 when the MCR3 is set to a logic 1. INTAB are set to the 3-state mode and OP to a logic
1 when MCR-3 is set to a logic 0. See bit 3, Modem Control Register (MCR bit 3). The output of these two pins
is high after reset.

RESET

Reset. RESET will reset the internal registers and all the outputs. The UART transmitter output and the
receiver input will be disabled during reset time. See TL16C752B external reset conditions for initialization
details. RESET is an active -high input.

RIA, RIB

41, 21

Ring indicator (active low). These inputs are associated with individual UART channels A and B. A logic low
on these pins indicates the modem has received a ringing signal from the telephone line. A low to high transition
on these input pins generates a modem status interrupt, if enabled.

RTSA, RTSB

33, 22

Request to send (active low). These outputs are associated with individual UART channels A and B. A low on
the RTS pins indicates the transmitter has data ready and waiting to send. Writing a 1 in the modem control
register (MCR bit 1) sets these pins to low, indicating data is available. After a reset, these pins are set to high.
These pins only affects the transmit and receive operation when auto RTS function is enabled through the
enhanced feature register (EFR) bit 6, for hardware flow control operation.

RXA, RXB

5, 4

Receive data input. These inputs are associated with individual serial channel data to the 752B. During the
local loopback mode, these RX input pins are disabled and TX data is internally connected to the UART RX
input internally.

RXRDYA,
RXRDYB

31, 18

Receive ready (active low). RXRDY A and B goes low when the trigger level has been reached or a timeout
interrupt occurs. They go high when the RX FIFO is empty or there is an error in RX FIFO.

TXA, TXB

7, 8

Transmit data. These outputs are associated with individual serial transmit channel data from the 752B. During
the local loopback mode, the TX input pin is disabled and TX data is internally connected to the UART RX input.

TXRDYA,
TXRDYB

43, 6

Transmit ready (active low). TXRDY A and B go low when there trigger level numbers of spares available. They
go high when the TX buffer is full.

VCC

Power supply inputs.

XTAL1

Crystal or external clock input. XTAL1 functions as a crystal input or as an external clock input. A crystal can
be connected between XTAL1 and XTAL2 to form an internal oscillator circuit (see Figures 10 and 11).
Alternatively, an external clock can be connected to XTAL1 to provide custom data rates.

XTAL2

Output of the crystal oscillator or buffered clock. See also XTAL1. XTAL2 is used as a crystal oscillator output
or buffered a clock output.

TL16C752B
3.3-V DUAL UART WITH 64-BYTE FIFO

SLLS405 DECEMBER 1999

POST OFFICE BOX 655303

DALLAS, TEXAS 75265

functional block diagram

Control Signals

Modem Control Signals

Divisor

Bus

Interface

Control

and

Status Block

Status Signals

Control Signals

Status Signals

Baud-Rate

Generator

UART_CLK

Receiver Block

Logic

Receiver FIFO

64-Byte

Vote

Logic

Transmitter Block

Logic

Transmitter FIFO

64-Byte

NOTE: The vote logic determines whether the RX data is a logic 1 or 0. It takes three samples of the RX line, and uses a majority vote to determine

the logic level received. The vote logic operates on all bits received.

functional description

The TL16C752B UART is pin compatible with the ST16C2550 UART. It provides more enhanced features. All
additional features are provided through a special enhanced feature register.

The UART will perform serial-to-parallel conversion on data characters received from peripheral devices or
modems and parallel-to-parallel conversion on data characters transmitted by the processor. The complete
status of each channel of the TL16C752B UART can be read at any time during functional operation by the
processor.

The TL16C752B can be placed in an alternate mode (FIFO mode) relieving the processor of excessive software
overhead by buffering received/transmitted characters. Both the receiver and transmitter FIFOs can store up
to 64 bytes (including three additional bits of error status per byte for the receiver FIFO) and have selectable
or programmable trigger levels. Primary outputs RXRDY and TXRDY allow signalling of DMA transfers.

The TL16C752B has selectable hardware flow control and software flow control. Hardware flow control
significantly reduces software overhead and increases system efficiency by automatically controlling serial data
flow using the RTS output and CTS input signals. Software flow control automatically controls data flow by using
programmable Xon/Xoff characters.

The UART includes a programmable baud rate generator that can divide the timing reference clock input by a
divisor between 1 and (2

1).

TL16C752B

3.3-V DUAL UART WITH 64-BYTE FIFO

SLLS405 DECEMBER 1999

POST OFFICE BOX 655303

DALLAS, TEXAS 75265

functional description (continued)

trigger levels

The TL16C752B provides independent selectable and programmable trigger levels for both receiver and
transmitter DMA and interrupt generation. After reset, both transmitter and receiver FIFOs are disabled and so,
in effect, the trigger level is the default value of one byte. The selectable trigger levels are available via the FCR.
The programmable trigger levels are available via the TLR.

hardware flow control

Hardware flow control is composed on auto-CTS and auto-RTS. Auto-CTS and auto-RTS can be enabled/
disabled independently by programming EFR[7:6].

With auto-CTS, CTS must be active before the UART can transmit data.

Auto-RTS only activates the RTS output when there is enough room in the FIFO to receive data and deactivates
the RTS output when the RX FIFO is sufficiently full. The HALT and RESTORE trigger levels in the TCR
determine the levels at which RTS is activated/deactivated.

If both auto-CTS and auto-RTS are enabled, when RTS is connected to CTS, data transmission does not occur
unless the receiver FIFO has empty space. Thus, overrun errors are eliminated during hardware flow control.
If not enabled, overrun errors occur if the transmit data rate exceeds the receive FIFO servicing latency.

auto-RTS

Auto-RTS data flow control originates in the receiver block (see functional block diagram). Figure 1 shows RTS
functional timing. The receiver FIFO trigger levels used in Auto-RTS are stored in the TCR. RTS is active if the
RX FIFO level is below the HALT trigger level in TCR[3:0]. When the receiver FIFO HALT trigger level is reached,
RTS is deasserted. The sending device (e.g., another UART) may send an additional byte after the trigger level
is reached (assuming the sending UART has another byte to send) because it may not recognize the
deassertion of RTS until it has begun sending the additional byte. RTS is automatically reasserted once the
receiver FIFO reaches the RESUME trigger level programmed via TCR[7:4]. This reassertion allows the
sending device to resume transmission.

RTS

IOR

Start

Byte N

Stop

Start

Byte N+1

Stop

Start

N+1

NOTES:

1. N = receiver FIFO trigger level
2. The two blocks in dashed lines cover the case where an additional byte is sent as described in Auto-RTS.

Figure 1. RTS Functional Timing

Part Number TL16C752B