TL16C554, TL16C554I

ASYNCHRONOUS COMMUNICATIONS ELEMENT

SLLS165D JANUARY 1994 REVISED JULY 1998

POST OFFICE BOX 655303

DALLAS, TEXAS 75265

Integrated Asynchronous Communications
Element

Consists of Four Improved TL16C550 ACEs
Plus Steering Logic

In FIFO Mode, Each ACE Transmitter and
Receiver Is Buffered With 16-Byte FIFO to
Reduce the Number of Interrupts to CPU

In TL16C450 Mode, Hold and Shift
Registers Eliminate Need for Precise
Synchronization Between the CPU and
Serial Data

Up to 16-MHz Clock Rate for up to 1-Mbaud
Operation

Programmable Baud Rate Generators
Which Allow Division of Any Input
Reference Clock by 1 to (2

 1) and

Generate an Internal 16

Clock

Adds or Deletes Standard Asynchronous
Communication Bits (Start, Stop, and
Parity) to or From the Serial Data Stream

Independently Controlled Transmit,
Receive, Line Status, and Data Set
Interrupts

Fully Programmable Serial Interface
Characteristics:
5-, 6-, 7-, or 8-Bit Characters
Even-, Odd-, or No-Parity Bit
1-, 1 1/2-, or 2-Stop Bit Generation
Baud Generation (DC to 1-Mbit Per

Second)

False Start Bit Detection

Complete Status Reporting Capabilities

Line Break Generation and Detection

Internal Diagnostic Capabilities:
Loopback Controls for Communications

Link Fault Isolation

 Break, Parity, Overrun, Framing Error

Simulation

Fully Prioritized Interrupt System Controls

Modem Control Functions (CTS, RTS, DSR,
DTR, RI, and DCD)

3-State Outputs Provide TTL Drive
Capabilities for Bidirectional Data Bus and
Control Bus

description

The TL16C554 and the TL16C554I are enhanced quadruple versions of the TL16C550B asynchronous
communications element (ACE). Each channel performs serial-to-parallel conversion on data characters
received from peripheral devices or modems and parallel-to-serial conversion on data characters transmitted
by the CPU. The complete status of each channel of the quadruple ACE can be read at any time during functional
operation by the CPU. The information obtained includes the type and condition of the operation performed and
any error conditions encountered.

The TL16C554 and the TL16C554I quadruple ACE can be placed in an alternate FIFO mode, which activates
the internal FIFOs to allow 16 bytes (plus three bits of error data per byte in the receiver FIFO) to be stored in
both receive and transmit modes. To minimize system overhead and maximize system efficiency, all logic is on
the chip. Two terminal functions allow signaling of direct memory access (DMA) transfers. Each ACE includes
a programmable baud rate generator that can divide the timing reference clock input by a divisor between 1 and
(2

1).

The TL16C554 and the TL16C554I are available in a 68-pin plastic-leaded chip-carrier (PLCC) FN package and
in an 80-pin (TQFP) PN package.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.

1998, Texas Instruments Incorporated

TL16C554, TL16C554I

ASYNCHRONOUS COMMUNICATIONS ELEMENT

SLLS165D JANUARY 1994 REVISED JULY 1998

POST OFFICE BOX 655303

DALLAS, TEXAS 75265

NC
DSRB
CTSB
DTRB
GND
RTSB
INTB
CSB
TXB
IOW
NC
TXA
CSA
INTA
RTSA
V

DTRA
CTSA
DSRA
NC

DSRC

CTSC

DTRC

RTSC

INTC

CSC

TXC

IOR

TXD

CSD

INTD

RTSD

GND

DTRD

CTSD

DSRD

7 8

PN PACKAGE

(TOP VIEW)

AL1

59 58 57 56 55

RIC

RXC

GND

TXRDY

RXRDY

RESET

RID

RXD

INTN

52 51 50

9 10 11 12 13

49 48

47 46 45 44

14 15 16 17

GND

RXA

AL2

RXB

DCDC

RIA

DCDA

18 19 20

RIB

DCDB

43 42 41

DCDD

NC No internal connection

TL16C554, TL16C554I
ASYNCHRONOUS COMMUNICATIONS ELEMENT

SLLS165D JANUARY 1994 REVISED JULY 1998

POST OFFICE BOX 655303

DALLAS, TEXAS 75265

functional block diagram

TL16C550B

Circuitry

TL16C550B

Circuitry

TL16C550B

Circuitry

TL16C550B

Circuitry

Receive

Control

Logic

Transmit

Control

Logic

Modem

Control

Logic

Control

Logic

Data

Bus

Clock

Circuit

RXx

TXx

CTSx
RTSx
DSRx
DTRx
RIx
DCDx

D7 D0

A2 A0

CSx

IOR, IOW

RESET

XTAL1
XTAL2

INTx

TXRDY, RXRDY

Interrupt

Logic

For TL16C550 circuitry, refer to the TL16C550B data sheet.

Terminal Functions

TERMINAL

NAME

NO.

I/O

DESCRIPTION

A0
A1
A2

34
33
32

48
47
46

Register select terminals. A0, A1, and A2 are three inputs used during read and write operations to
select the ACE register to read or write.

CSA, CSB,
CSC, CSD

16, 20,

50, 54

28, 33,

68, 73

Chip select. Each chip select (CSx) enables read and write operations to its respective channel.

CTSA, CTSB,
CTSC, CTSD

11, 25,

45, 59

23, 38,

63, 78

Clear to send. CTSx is a modem status signal. Its condition can be checked by reading bit 4 (CTS)
of the modem status register. CTS has no affect on the transmit or receive operation.

D7 D0

66 68

1 5

1511,

I/O

Data bus. Eight data lines with 3-state outputs provide a bidirectional path for data, control, and status
information between the TL16C554 and the CPU. D0 is the least significant bit (LSB).

DCDA, DCDB,
DCDC, DCDD

9, 27,

43, 61

19,42,

59, 2

Data carrier detect. A low on DCDx indicates the carrier has been detected by the modem. The
condition of this signal is checked by reading bit 7 of the modem status register.

DSRA, DSRB,
DSRC, DSRD

10, 26,

44, 60

22, 39,

62, 79

Data set ready. DSRx is a modem status signal. Its condition can be checked by reading bit 5 (DSR)
of the modem status register. DSR has no affect on the transmit or receive operation.

DTRA, DTRB,
DTRC, DTRD

12, 24,

46, 58

24, 37,

64, 77

Data terminal ready. DTRx is an output that indicates to a modem or data set that the ACE is ready
to establish communications. It is placed in the active state by setting the DTR bit of the modem
control register. DTRx is placed in the inactive state (high) either as a result of the master reset during
loop mode operation or clearing bit 0 (DTR) of the modem control register.

GND

6, 23,

40, 57

16, 36,

56, 76

Signal and power ground

INTN

Interrupt normal. INTN operates in conjunction with bit 3 of the modem status register and affects
operation of the interrupts (INTA, INTB, INTC, and INTD) for the four universal asynchronous
receiver/transceivers (UARTs) per the following table.

INTN

OPERATION OF INTERRUPTS

Brought low or
allowed to float

Interrupts are enabled according to the state of OUT2 (MCR bit 3). When the MCR
bit 3 is cleared, the 3-state interrupt output of that UART is in the high-impedance
state. When the MCR bit 3 is set, the interrupt output of the UART is enabled.

Brought high

Interrupts are always enabled, overriding the OUT2 enables.

TL16C554, TL16C554I

ASYNCHRONOUS COMMUNICATIONS ELEMENT

SLLS165D JANUARY 1994 REVISED JULY 1998

POST OFFICE BOX 655303

DALLAS, TEXAS 75265

Terminal Functions (Continued)

TERMINAL

NAME

NO.

I/O

DESCRIPTION

INTA, INTB,
INTC, INTD

15, 21,

49, 55

27, 34,

67, 74

External interrupt output. The INTx outputs go high (when enabled by the interrupt register) and
inform the CPU that the ACE has an interrupt to be serviced. Four conditions that cause an interrupt
to be issued are: a receiver error, receiver data available or timeout (FIFO mode only), transmitter
holding register empty, and an enabled modem status interrupt. The interrupt is disabled when it is
serviced or as the result of a master reset.

IOR

Read strobe. A low level on IOR transfers the contents of the TL16C554 data bus to the external CPU
bus.

IOW

Write strobe. IOW allows the CPU to write into the selected address by the address register.

RESET

Master reset. When active, RESET clears most ACE registers and sets the state of various signals.
The transmitter output and the receiver input is disabled during reset time.

RIA, RIB,
RIC, RID

8, 28,

42, 62

18, 43,

58, 3

Ring detect indicator. A low on RIx indicates the modem has received a ring signal from the telephone
line. The condition of this signal can be checked by reading bit 6 of the modem status register.

RTSA, RTSB,
RTSC, RTSD

14, 22,

48, 56

26, 35,

66, 75

Request to send. When active, RTSx informs the modem or data set that the ACE is ready to receive
data. Writing a 1 in the modem control register sets this bit to a low state. After reset, this terminal
is set high. These terminals have no affect on the transmit or receive operation.

RXA, RXB
RXC, RXD

7, 29,

41, 63

17, 44,

57, 4

Serial input. RXx is a serial data input from a connected communications device. During loopback
mode, the RXx input is disabled from external connection and connected to the TXx output internally.

RXRDY

Receive ready. RXRDY goes low when the receive FIFO is full. It can be used as a single transfer
or multitransfer.

TXA, TXB
TXC, TXD

17, 19,

51, 53

29, 32,

69, 72

Transmit outputs. TXx is a composite serial data output that is connected to a communications
device. TXA, TXB, TXC, and TXD are set to the marking (high) state as a result of reset.

TXRDY

Transmit ready. TXRDY goes low when the transmit FIFO is full. It can be used as a single transfer
or multitransfer function.

VCC

13, 30,

47, 64

5, 25,

45, 65

Power supply

XTAL1

Crystal input 1 or external clock input. A crystal can be connected to XTAL1 and XTAL2 to utilize the
internal oscillator circuit. An external clock can be connected to drive the internal clock circuits.

XTAL2

Crystal output 2 or buffered clock output (see XTAL1).

absolute maximum ratings over free-air temperature range (unless otherwise noted)

Supply voltage range, V

(see Note 1)

0.5 V to 7 V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Input voltage range at any input, V

0.5 V to 7 V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Output voltage range, V

0.5 V to V

+ 3 V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Continuous total power dissipation at (or below) 70

C 500

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Operating free-air temperature range, T

: TL16C554 0

C to 70

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

TL16C554I 40

C to 85

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Storage temperature range, T

stg

C to 150

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and

functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTE 1: All voltage levels are with respect to GND.

Part Number TL16C554