THS1031
2.7 V 5.5 V, 10-BIT, 30 MSPS
CMOS ANALOG-TO-DIGITAL CONVERTER
SLAS242A NOVEMBER 1999 REVISED JANUARY 2000
1
POST OFFICE BOX 655303
·
DALLAS, TEXAS 75265
D
10-Bit Resolution 30 MSPS
Analog-to-Digital Converter:
D
Configurable Input Functions:
Single-Ended
Single-Ended With Analog Clamp
Single-Ended With Programmable Digital
Clamp
Differential
D
Built-in Programmable Gain Amplifier
(PGA)
D
Differential Nonlinearity:
±
0.3 LSB
D
Signal-to-Noise: 56 dB
D
Spurious Free Dynamic Range: 60 dB
D
Adjustable Internal Voltage Reference
D
Straight Binary/ 2s Complement Output
D
Out-of-Range Indicator
D
Power-Down Mode
description
The THS1031 is a CMOS, low power, 10-bit, 30 MSPS analog-to-digital converter (ADC) that can operate with
a supply range from 2.7 V to 3.3 V. The THS1031 has been designed to give circuit developers more flexibility.
The analog input to the THS1031 can be either single-ended or differential. This device has a built-in clamp
amplifier whose clamp input level can be selected from an external dc source or from an internal high-precision
10-bit digital clamp level programmable via an internal CLAMP register. A 3-bit PGA is included to maintain SNR
for small signal. The THS1031 provides a wide selection of voltage reference to match the user's design
requirements. For more design flexibility, the internal reference can be bypassed to use an external reference
to suit the dc accuracy and temperature drift requirements of the application. The out-of-range output is used
to monitor any out-of-range condition in THS1031's input range. The format of digital output can be coded in
either straight binary or 2s complement.
The speed, resolution, and single-supply operation of the THS1031 are suited for applications in set-top-box
(STB), video, multimedia, imaging, high-speed acquisition, and communications. The built-in clamp function
allows dc restoration of video signal and is suitable for video application. The speed and resolution ideally suit
charge-couple device (CCD) input systems such as color scanners, digital copiers, digital cameras, and
camcorders. A wide input voltage range between REFBS and REFTS allows the THS1031 to be applied in both
imaging and communications systems
The THS1031I is characterized for operation from 40
°
C to 85
°
C.
AVAILABLE OPTIONS
TA
PACKAGED DEVICES
TA
28-TSSOP (PW)
28-SOIC (DW)
0
°
C to 70
°
C
THS1031CPW
THS1031CDW
40
°
C to 85
°
C
THS1031IPW
THS1031IDW
Copyright
©
2000, Texas Instruments Incorporated
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
AGND
DV
DD
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
I/O8
I/O9
OVR
DGND
AV
DD
AIN
V
REF
REFBS
REFBF
MODE
REFTF
REFTS
CLAMPIN
CLAMP
REFSENSE
WR
OE
CLK
28-PIN TSSOP/SOIC PACKAGE
(TOP VIEW)
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
THS1031
2.7 V 5.5 V, 10-BIT, 30 MSPS
CMOS ANALOG-TO-DIGITAL CONVERTER
SLAS242A NOVEMBER 1999 REVISED JANUARY 2000
2
POST OFFICE BOX 655303
·
DALLAS, TEXAS 75265
functional block diagram
SHA
CLAMP
DAC
SW2
10
CTL
REG
Power
Down
Output
Buffers
BIN/2'S
Timing
Circuit
A/D
PGA
3
SW1
SW3
DC
REF
DAC
REF
VBG
REFSENSE
VREF
CLK
REFBF
REFTF
MODE
REFBS
REFTS
AIN
CLAMP
CLAMPIN
WR
I/O0
I/O9
OVR
OE
SW4
THS1031
2.7 V 5.5 V, 10-BIT, 30 MSPS
CMOS ANALOG-TO-DIGITAL CONVERTER
SLAS242A NOVEMBER 1999 REVISED JANUARY 2000
3
POST OFFICE BOX 655303
·
DALLAS, TEXAS 75265
Terminal Functions
TERMINAL
I/O
DESCRIPTION
NAME
NO.
I/O
DESCRIPTION
AGND
1
I
Analog ground
AIN
27
I
Analog input
AVDD
28
I
Analog supply
CLAMP
19
I
HI to enable CLAMP mode, LO to disable CLAMP mode
CLAMPIN
20
I
Connect to an external analog clamp reference input.
CLK
15
I
Clock input
DGND
14
I
Digital ground
DVDD
2
I
Digital driver supply
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
I/O8
I/O9
3
4
5
6
7
8
9
10
11
12
I/O
Digital I/O bit 0 (LSB)
Digital I/O bit 1
Digital I/O bit 2
Digital I/O bit 3
Digital I/O bit 4
Digital I/O bit 5
Digital I/O bit 6
Digital I/O bit 7
Digital I/O bit 8
Digital I/O bit 9 (MSB)
MODE
23
I
Mode input
OE
16
I
HI to the 3-state data bus, LO to enable the data bus
OVR
13
O
Out-of-range indicator
REFBS
25
I
Reference bottom sense
REFBF
24
I
Reference bottom decoupling
REFSENSE
18
I
Reference sense
REFTF
22
I
Reference top decoupling
REFTS
21
I
Reference top sense
VREF
26
I/O
Internal and external reference for ADC
WR
17
I
Write strobe goes HI to write data value D0:D9 to the internal registers.
THS1031
2.7 V 5.5 V, 10-BIT, 30 MSPS
CMOS ANALOG-TO-DIGITAL CONVERTER
SLAS242A NOVEMBER 1999 REVISED JANUARY 2000
4
POST OFFICE BOX 655303
·
DALLAS, TEXAS 75265
absolute maximum ratings over operating free-air temperature (unless otherwise noted)
Supply voltage: AV
DD
to AGND, DV
DD
to DGND
0.3 to 6.5 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
AGND to DGND
0.3 to 0.3 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
AV
DD
to DV
DD
6.5 to 6.5 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Mode input MODE to AGND
0.3 to AV
DD
+ 0.3 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Reference voltage input range REFTF, REFTB, REFTS, REFBS to AGND
0.3 to AV
DD
+ 0.3 V
. . . . . . . . .
Analog input voltage range AIN to AGND
0.3 to AV
DD
+ 0.3 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Reference input V
REF
to AGND
0.3 to AV
DD
+ 0.3 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Reference output V
REF
to AGND
0.3 to AV
DD
+ 0.3 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Clock input CLK to AGND
0.3 to AV
DD
+ 0.3 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Digital input to DGND
0.3 to DV
DD
+ 0.3 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Digital output to DGND
0.3 to DV
DD
+ 0.3 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating junction temperature range, T
J
0
°
C to 150
°
C
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, T
STG
65
°
C to 150
°
C
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Lead temperature 1,6 mm (1/16 in) from case for 10 seconds
300
°
C
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
recommended operating conditions
digital inputs
MIN
NOM
MAX
UNIT
High-level input voltage, VIH
2.4
V
Low-level input voltage, VIL
0.2 x DVDD
V
analog inputs
MIN
NOM
MAX
UNIT
Analog input voltage, VI(AIN)
REFBS
REFTS
V
Reference input voltage, VI(VREF)
1
2
V
Reference input voltage, VI(REFTS)
1
AVDD
V
Reference input voltage, VI(REFBS)
0
AVDD1
V
Clamp input voltage, VI(CLAMPIN)
REFBS
REFTS
V
power supply
MIN
NOM
MAX
UNIT
Supply voltage
Maximum sampling rate = 30 MSPS
AVDD
2.7
3
5.5
V
Supply voltage
Maximum sampling rate = 30 MSPS
DVDD
2.7
3
5.5
V
REFTS, REFBS reference voltages (MODE = AV
DD
)
PARAMETER
MIN
TYP
MAX
UNIT
REFTS
Reference input voltage (top)
1
AVDD
V
REFBS
Reference input voltage (bottom)
0
AVDD1
V
Differential input (REFTS REFBS)
1
2
V
Switched input capacitance on REFTS
0.6
pF
Switched input capacitance on REFBS
0.6
pF
sampling rate and resolution
PARAMETER
MIN
NOM
MAX
UNIT
Fs
5
30
MHz
Resolution
10
Bits
THS1031
2.7 V 5.5 V, 10-BIT, 30 MSPS
CMOS ANALOG-TO-DIGITAL CONVERTER
SLAS242A NOVEMBER 1999 REVISED JANUARY 2000
5
POST OFFICE BOX 655303
·
DALLAS, TEXAS 75265
electrical characteristics, AV
DD
= 3 V, DV
DD
= 3 V, Fs = 30 MSPS/50% duty cycle, MODE = AV
DD
, 2 V
input span from 0.5 V to 2.5 V, external reference, PGA = 1X, T
A
= 40
°
C to 85
°
C (unless otherwise
noted)
analog inputs
PARAMETER
MIN
TYP
MAX
UNIT
VI(AIN)
Analog input voltage
REFBS
REFTS
V
CI
Switched input capacitance
1.2
pF
FPBW
Full power BW (3 dB)
150
MHz
DC leakage current (input =
±
FS)
100
µ
A
REFTF, REFBF reference voltages
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Differential input (REFTF REFBF)
1
2
V
Input common mode (REFTF + REFBF)/2
AVDD = 3 V
1.3
1.5
1.7
V
Input common mode (REFTF + REFBF)/2
AVDD = 5 V
2
2.5
3
V
VREF = 1 V
AVDD = 3 V
2
V
REFTF (MODE = AVDD)
VREF = 1 V
AVDD = 5 V
3
V
REFTF (MODE = AVDD)
VREF = 2 V
AVDD = 3 V
2.5
V
VREF = 2 V
AVDD = 5 V
3.5
V
VREF = 1 V
AVDD = 3 V
1
V
REFBF (MODE = AVDD)
VREF = 1 V
AVDD = 5 V
0.5
V
REFBF (MODE = AVDD)
VREF = 2 V
AVDD = 3 V
2
V
VREF = 2 V
AVDD = 5 V
1.5
V
Input resistance between REFTF and REFBF
600
V
REF
reference voltages
PARAMETER
MIN
TYP
MAX
UNIT
Internal 1 V reference (REFSENSE = VREF)
0.95
1
1.05
V
Internal 2 V reference (REFSENSE = AVSS)
1.90
2
2.10
V
External reference (REFSENSE = AVDD)
1
2
V
Reference input resistance
18
k
dc accuracy
PARAMETER
MIN
TYP
MAX
UNIT
INL
Integral nonlinearity
±
1
±
2
LSB
DNL
Differential nonlinearity
±
0.3
±
1
LSB
Offset error
0.4
1.4
%FSR
Gain error
1.4
3.5
%FSR
Missing code
No missing code assured
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