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Part Number TFP201

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TFP201, TFP201A
TI PanelBus
DIGITAL RECEIVER
SLDS116A - MARCH 2000 ­ REVISED JUNE 2000
1
POST OFFICE BOX 655303
·
DALLAS, TEXAS 75265
D
Supports SXGA Resolution
(Output Pixel Rates Up to 112 MHz)
D
Digital Visual Interface (DVI) Specification
Compliant
1
D
True-Color, 24 Bit/Pixel, 16.7M Colors at 1
or 2-Pixels Per Clock
D
Laser Trimmed Internal Termination
Resistors for Optimum Fixed Impedance
Matching
D
Skew Tolerant Up to One Pixel Clock Cycle
D
4x Over-Sampling
D
Reduced Power Consumption ­ 1.8 V Core
Operation With 3.3 V I/Os and Supplies
2
D
Reduced Ground Bounce Using Time
Staggered Pixel Outputs
D
Lowest Noise and Best Power Dissipation
Using TI PowerPAD
Packaging
D
Advanced Technology Using TI 0.18-
µ
m
EPIC-5
CMOS Process
D
TFP201A Incorporates HSYNC Jitter
Immunity
3
description
The Texas Instruments TFP201 and TFP201A are TI PanelBus
flat panel display products, part of a
comprehensive family of end-to-end DVI 1.0 compliant solutions. Targeted primarily at desktop LCD monitors
and digital projectors, the TFP201/201A finds applications in any design requiring high-speed digital interface.
The TFP201/201A supports display resolutions up to SXGA in 24-bit true color pixel format. The TFP201/201A
offers design flexibility to drive one or two pixels per clock, supports TFT or DSTN panels, and provides an option
for time staggered pixel outputs for reduced ground bounce.
PowerPAD
advanced packaging technology results in best of class power dissipation, footprint, and ultra-low
ground inductance.
The TFP201/201A combines PanelBus
circuit innovation with TI's advanced 0.18-
µ
m EPIC-5
CMOS
process technology, along with TI PowerPAD
package technology to achieve a reliable, low-powered, low
noise, high-speed digital interface solution.
AVAILABLE OPTIONS
PACKAGED DEVICE
TA
100-TQFP
(PZP)
0
°
C to 70
°
C
TFP201PZP
0
°
C to 70
°
C
TFP201APZP
1.
The Digital Visual Interface Specification, DVI, is an industry standard developed by the Digital Display Working Group (DDWG) for
high-speed digital connection to digital displays The TFP201 and TFP201A are compliant to the DVI Specification Rev. 1.0.
2.
The TFP201/201A has an internal voltage regulator that provides the 1.8-V core power supply from the externally supplied 3.3-V
supplies.
3.
The TFP201A incorporates additional circuitry to create a stable HSYNC from DVI transmitters that introduce undesirable jitter on
the transmitted HSYNC signal.
Copyright
2000, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PanelBus, PowerPAD and EPIC-5 are trademarks of Texas Instruments.
I2C is a licensed bus protocol from Phillips Semiconductor, Inc.
TFP201, TFP201A
TI PanelBus
DIGITAL RECEIVER
SLDS116A - MARCH 2000 ­ REVISED JUNE 2000
2
POST OFFICE BOX 655303
·
DALLAS, TEXAS 75265
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
QO1
QO0
HSYNC
DE
ODCK
OVDD
CTL3
CTL2
CTL1
GND
DVDD
QE23
QE22
QE20
QE19
QE17
QE16
OVDD
OGND
QE15
QE14
OGND
OVDD
AGND
Rx2+
Rx2­
AVDD
AGND
AVDD
Rx1­
AGND
AGND
Rx0+
Rx0­
AGND
RxC+
RxC­
AVDD
EXT_RES
PGND
RSVD
OCK_INV
QO22
QO21
QO20
QO18
QO17
QO16
GND
DVDD
QO13
QO12
QO9
QO8
OGND
OVDD
QO7
QO6
QO5
QO4
QO3
QO2
DFO
PD
ST
PIXS
GND
DVDD
ST
AG
PDO
QE0
QE2
QE3
QE4
QE5
QE6
OVDD
OGND
QE9
QE1
1
QE12
QE13
QE7
100-PIN PACKAGE
(TOP VIEW)
QO23
AVDD
QO1
1
QO15
QO14
OGND
QE18
SCDT
QE8
QE1
QE10
QE21
VSYNC
QO10
QO19
Rx1+
PVDD
TFP201, TFP201A
TI PanelBus
DIGITAL RECEIVER
SLDS116A - MARCH 2000 ­ REVISED JUNE 2000
3
POST OFFICE BOX 655303
·
DALLAS, TEXAS 75265
functional block diagram
_
+
Latch
Channel 2
_
+
Latch
Channel 1
_
+
Latch
Channel 0
_
+
PLL
Data Recovery
and
Synchronization
TMDS
Decoder
CH2(0-9)
CH1(0-9)
CH0(0-9)
Panel
Interface
RED(0-7)
CTL3
CTL2
GRN(0-7)
CTL1
BLU(0-7)
VSYNC
HSYNC
QE(0-23)
QO(0-23)
ODCK
DE
SCDT
CTL3
CTL2
CTL1
VSYNC
HSYNC
1.8 V
Regulator
3.3 V
Internal 50-
Termination
3.3 V
3.3 V
Rx2+
Rx2-
Rx1+
Rx1-
Rx0+
Rx0-
RxC+
RxC-
Terminal Functions
TERMINAL
I/O
DESCRIPTION
NAME
NO.
I/O
DESCRIPTION
AGND
79,83,87,
89,92
GND
Analog Ground ­ Ground reference and current return for analog circuitry.
AVDD
82,84,88,
95
VDD
Analog VDD ­ Power supply for analog circuitry. Nominally 3.3 V
CTL[3:1]
42,41,40
DO
General-purpose control signals ­ Used for user defined control. CTL1 is not powered-down via PDO.
DE
46
DO
Output data enable ­ Used to indicate time of active video display versus non-active display or blank time.
During blank, only HSYNC, VSYNC, and CTL1-3 are transmitted. During times of active display, or non-blank,
only pixel data, QE[23:0] and QO[23:0], is transmitted.
High : Active display time
Low: Blank time
DFO
1
DI
Output clock data format ­ Controls the output clock (ODCK) format for either TFT or DSTN panel support. For
TFT support ODCK clock runs continuously. For DSTN support ODCK only clocks when DE is high, otherwise
ODCK is held low when DE is low.
High : DSTN support/ODCK held low when DE = low
Low: TFT support/ODCK runs continuously.
DGND
5,39,68
GND
Digital ground ­ Ground reference and current return for digital core
DVDD
6,38,67
VDD
Digital VDD ­ Power supply for digital core. Nominally 3.3 V
EXT_RES
96
AI
Internal impedance matching ­ The TFP201/201A is internally optimized for impedance matching at 50
. An
external resistor tied to this pin will have no effect on device performance.
HSYNC
48
DO
Horizontal sync output
RSVD
99
DI
Reserved. Must be tied high for normal operation.
OVDD
18,29,43,
57,78
VDD
Output driver VDD ­ Power supply for output drivers. Nominally 3.3 V
ODCK
44
DO
Output data clock - Pixel clock. All pixel outputs QE[23:0] and QO[23:0] (if in 2-pixel/clock mode) along with
DE, HSYNC, VSYNC and CTL[3:1] are synchronized to this clock.
TFP201, TFP201A
TI PanelBus
DIGITAL RECEIVER
SLDS116A - MARCH 2000 ­ REVISED JUNE 2000
4
POST OFFICE BOX 655303
·
DALLAS, TEXAS 75265
Terminal Functions (continued)
TERMINAL
I/O
DESCRIPTION
NAME
NO.
I/O
DESCRIPTION
OGND
19,28,45,
58,76
GND
Output driver ground ­ Ground reference and current return for digital output drivers
OCK_INV
100
DI
ODCK Polarity ­ Selects ODCK edge on which pixel data (QE[23:0] and QO[23:0]) and control signals
(HSYNC, VSYNC, DE, CTL1-3 ) are latched
Normal Mode:
High : Latches output data on rising ODCK edge
Low : Latches output data on falling ODCK edge
PD
2
DI
Power down ­ An active low signal that controls the TFP201/201A power-down state. During power down all
output buffers are switched to a high impedance state. All analog circuits are powered down and all inputs are
disabled, except for PD.
If PD is left unconnected an internal pullup will default the TFP201/201A to normal operation.
High : Normal operation
Low: Power down
PDO
9
DI
Output drive power down ­ An active low signal that controls the power-down state of the output drivers.
During output drive power down, the output drivers (except SCDT and CTL1) are driven to a high impedance
state. When PDO is left unconnected, an internal pullup defaults the TFP201/201A to normal operation.
High : Normal operation/output drivers on
Low: Output drive power down.
PGND
98
GND
PLL GND ­ Ground reference and current return for internal PLL
PIXS
4
DI
Pixel select ­ Selects between one or two pixels per clock output modes. During the 2-pixel/clock mode, both
even pixels, QE[23:0], and odd pixels, QO[23:0], are output in tandem on a given clock cycle. During
1-pixel/clock, even and odd pixels are output sequentially, one at a time, with the even pixel first, on the even
pixel bus, QE[23:0]. (The first pixel per line is pixel-0, the even pixel. The second pixel per line is pixel-1, the
odd pixel.)
High : 2-pixel/clock
Low: 1-pixel/clock
QE[0:7]
10-17
DO
Even blue pixel output ­ Output for even and odd blue pixels when in 1-pixel/clock mode. Output for even only
blue pixel when in 2-pixel per clock mode. Output data is synchronized to the output data clock, ODCK.
LSB: QE0/pin 10
MSB: QE7/pin 17
QE[8:15]
20-27
DO
Even green pixel output ­ Output for even and odd green pixels when in 1-pixel/clock mode. Output for even
only green pixel when in 2-pixel/clock mode. Output data is synchronized to the output data clock, ODCK.
LSB: QE8/pin 20
MSB: QE15/pin 27
QE[16:23]
30-37
DO
Even red pixel output ­ Output for even and odd red pixels when in 1-pixel/clock mode. Output for even only
red pixel when in 2-pixel/clock mode. Output data is synchronized to the output data clock, ODCK.
LSB: QE16/pin 30
MSB: QE23/pin 37
QO[0:7]
49-56
DO
Odd blue pixel output ­ Output for odd only blue pixel when in 2-pixel/clock mode. Not used, and held low,
when in 1-pixel/clock mode. Output data is synchronized to the output data clock, ODCK.
LSB: QO0/pin 49
MSB: QO7/pin 56
QO[8:15]
59-66
DO
Odd green pixel output ­ Output for odd only green pixel when in 2-pixel/clock mode. Not used, and held low,
when in 1-pixel/clock mode. Output data is synchronized to the output data clock, ODCK.
LSB: QO8/pin 59
MSB: QO15/pin 66
QO[16:23]
69-75,77
DO
Odd red pixel output ­ Output for odd only red pixel when in 2-pixel/clock mode. Not used, and held low, when
in 1-pixel/clock mode. Output data is synchronized to the output data clock, ODCK.
LSB: QO16/pin 69
MSB: QO23/pin 77
TFP201, TFP201A
TI PanelBus
DIGITAL RECEIVER
SLDS116A - MARCH 2000 ­ REVISED JUNE 2000
5
POST OFFICE BOX 655303
·
DALLAS, TEXAS 75265
Terminal Functions (continued)
TERMINAL
I/O
DESCRIPTION
NAME
NO.
I/O
DESCRIPTION
RxC+
93
AI
Clock positive receiver input ­ Positive side of reference clock. TMDS low voltage signal differential input pair
RxC­
94
AI
Clock negative receiver input ­ Negative side of reference clock. TMDS low voltage signal differential input
pair.
Rx0+
90
AI
Channel-0 positive receiver input ­ Positive side of channel-0. TMDS low voltage signal differential input pair.
Channel-0 receives blue pixel data in active display and HSYNC, VSYNC control signals in blank.
Rx0­
91
AI
Channel-0 negative receiver input ­ Negative side of channel-0. TMDS low voltage signal differential input
pair.
Rx1+
85
AI
Channel-1 positive receiver input ­ Positive side of channel-1 TMDS low voltage signal differential input pair.
Channel-1 receives green pixel data in active display and CTL1 control signals in blank.
Rx1­
86
AI
Channel-1 negative receiver input ­ Negative side of channel-1 TMDS low voltage signal differential input pair
Rx2+
80
AI
Channel-2 positive receiver input ­ Positive side of channel-2 TMDS low voltage signal differential input pair.
Channel-2 receives red pixel data in active display and CTL2, CTL3 control signals in blank.
Rx2­
81
AI
Channel-2 negative receiver input ­ Negative side of channel-2 TMDS low voltage signal differential input pair.
SCDT
8
DO
Sync detect ­ Output to signal when the link is active or inactive. The link is considered to be active when DE is
actively switching. The TFP201/201A monitors the state DE to determine link activity. SCDT can be tied
externally to PDO to power down the output drivers when the link is inactive.
High: Active link
Low: Inactive link
ST
3
DI
Output drive strength select ­ Selects output drive strength for high or low current drive. (See dc specifications
for IOH and IOL vs ST state.)
High : High drive strength
Low : Low drive strength
STAG
7
DI
Staggered pixel select ­ An active low signal used in the 2-pixel/clock pixel mode (PIXS = high). Time staggers
the even and odd pixel outputs to reduce ground bounce. Normal operation outputs the odd and even pixels
simultaneously.
High : Normal simultaneous even/odd pixel output
Low: Time staggered even/odd pixel output
VSYNC
47
DO
Vertical sync output
absolute maximum ratings over operating free-air temperature (unless otherwise noted)
Supply voltage range, DV
DD
, AV
DD
, OV
DD
, PV
DD
-0.3 V to 4 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range, logic/analog signals
-0.3 V to 4 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating ambient temperature range
0
°
C to 70
°
C
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range
-65
°
C to 150
°
C
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Case temperature for 10 seconds
260
°
C
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds
260
°
C
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package power dissipation/PowerPAD
: Soldered (see Note 1)
4.3 W
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Not soldered (see Note 2)
2.7 W
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ESD Protection, all pins
2.5 KV Human Body Model
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
JEDEC latchup (EIA/JESD78)
100 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES:
1. Specified with PowerPAD bond pad on the backside of the package soldered to a 2 oz. Cu plate PCB thermal plane. Specified at
maximum allowed operating temperature, 70
°
C.
2. PowerPAD
bond pad on the backside of the package is not soldered to a thermal plane. Specified at maximum allowed operating
temperature, 70
°
C.