SN54LVTH18512, SN54LVTH182512, SN74LVTH18512, SN74LVTH182512

3.3-V ABT SCAN TEST DEVICES

WITH 18-BIT UNIVERSAL BUS TRANSCEIVERS

SCBS671B AUGUST 1996 REVISED OCTOBER 1997

POST OFFICE BOX 655303

DALLAS, TEXAS 75265

Members of the Texas Instruments
SCOPE

Family of Testability Products

Members of the Texas Instruments
Widebus

Family

State-of-the-Art 3.3-V ABT Design Supports
Mixed-Mode Signal Operation (5-V Input
and Output Voltages With 3.3-V V

)

Support Unregulated Battery Operation
Down to 2.7 V

UBT

(Universal Bus Transceiver)

Combines D-Type Latches and D-Type
Flip-Flops for Operation in Transparent,
Latched, or Clocked Mode

Bus Hold on Data Inputs Eliminates the
Need for External Pullup/Pulldown
Resistors

B-Port Outputs of 'LVTH182512 Devices
Have Equivalent 25-

Series Resistors, So

No External Resistors Are Required

Compatible With the IEEE Std 1149.1-1990
(JTAG) Test Access Port and
Boundary-Scan Architecture

SCOPE

Instruction Set

 IEEE Std 1149.1-1990 Required

Instructions and Optional CLAMP and
HIGHZ

Parallel-Signature Analysis at Inputs
Pseudo-Random Pattern Generation

From Outputs

Sample Inputs/Toggle Outputs
Binary Count From Outputs
Device Identification
Even-Parity Opcodes

Package Options Include 64-Pin Plastic
Thin Shrink Small Outline (DGG) and 64-Pin
Ceramic Dual Flat (HKC) Packages Using
0.5-mm Center-to-Center Spacings

description

The 'LVTH18512 and 'LVTH182512 scan test devices with 18-bit universal bus transceivers are members of
the Texas Instruments SCOPE

testability integrated-circuit family. This family of devices supports IEEE Std

1149.1-1990 boundary scan to facilitate testing of complex circuit-board assemblies. Scan access to the test
circuitry is accomplished via the 4-wire test access port (TAP) interface.

Additionally, these devices are designed specifically for low-voltage (3.3-V) V

operation, but with the

capability to provide a TTL interface to a 5-V system environment.

1997, Texas Instruments Incorporated

UNLESS OTHERWISE NOTED this document contains PRODUCTION
DATA information current as of publication date. Products conform to
specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all
parameters.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

SCOPE, Widebus, and UBT are trademarks of Texas Instruments Incorporated.

1CLKAB

1LEAB

1OEAB

1A1
1A2

GND

1A3
1A4
1A5

1A6
1A7
1A8

GND

1A9
2A1
2A2
2A3

GND

2A4
2A5
2A6

2A7
2A8
2A9

GND

2OEAB

2LEAB

2CLKAB

TDO
TMS

1CLKBA
1LEBA
1OEBA
1B1
1B2
GND
1B3
1B4
1B5
V

1B6
1B7
1B8
GND
1B9
2B1
2B2
2B3
GND
2B4
2B5
2B6
V

2B7
2B8
2B9
GND
2OEBA
2LEBA
2CLKBA
TDI
TCK

SN54LVTH18512, SN54LVTH182512 . . . HKC PACKAGE

SN74LVTH18512, SN74LVTH182512 . . . DGG PACKAGE

(TOP VIEW)

SN54LVTH18512, SN54LVTH182512, SN74LVTH18512, SN74LVTH182512
3.3-V ABT SCAN TEST DEVICES
WITH 18-BIT UNIVERSAL BUS TRANSCEIVERS

SCBS671B AUGUST 1996 REVISED OCTOBER 1997

POST OFFICE BOX 655303

DALLAS, TEXAS 75265

description (continued)

In the normal mode, these devices are 18-bit universal bus transceivers that combine D-type latches and D-type
flip-flops to allow data flow in transparent, latched, or clocked modes. They can be used either as two 9-bit
transceivers or one 18-bit transceiver. The test circuitry can be activated by the TAP to take snapshot samples
of the data appearing at the device pins or to perform a self test on the boundary-test cells. Activating the TAP
in the normal mode does not affect the functional operation of the SCOPE

universal bus transceivers.

Data flow in each direction is controlled by output-enable (OEAB and OEBA), latch-enable (LEAB and LEBA),
and clock (CLKAB and CLKBA) inputs. For A-to-B data flow, the devices operate in the transparent mode when
LEAB is high. When LEAB is low, the A data is latched while CLKAB is held at a static low or high logic level.
Otherwise, if LEAB is low, A data is stored on a low-to-high transition of CLKAB. When OEAB is low, the B
outputs are active. When OEAB is high, the B outputs are in the high-impedance state. B-to-A data flow is similar
to A-to-B data flow but uses the OEBA, LEBA, and CLKBA inputs.

In the test mode, the normal operation of the SCOPE

universal bus transceivers is inhibited, and the test

circuitry is enabled to observe and control the I/O boundary of the device. When enabled, the test circuitry
performs boundary-scan test operations according to the protocol described in IEEE Std 1149.1-1990.

Four dedicated test pins are used to observe and control the operation of the test circuitry: test data input (TDI),
test data output (TDO), test mode select (TMS), and test clock (TCK). Additionally, the test circuitry performs
other testing functions such as parallel-signature analysis (PSA) on data inputs and pseudo-random pattern
generation (PRPG) from data outputs. All testing and scan operations are synchronized to the TAP interface.

Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.

The B-port outputs of 'LVTH182512, which are designed to source or sink up to 12 mA, include equivalent 25-

series resistors to reduce overshoot and undershoot.

The SN54LVTH18512 and SN54LVTH182512 are characterized for operation over the full military temperature
range of 55

C to 125

C. The SN74LVTH18512 and SN74LVTH182512 are characterized for operation from

C to 85

FUNCTION TABLE

(normal mode, each register)

INPUTS

OUTPUT

OEAB

LEAB

CLKAB

A-to-B data flow is shown. B-to-A data flow is similar

but uses OEBA, LEBA, and CLKBA.

Output level before the indicated steady-state input

conditions were established

SN54LVTH18512, SN54LVTH182512, SN74LVTH18512, SN74LVTH182512

3.3-V ABT SCAN TEST DEVICES

WITH 18-BIT UNIVERSAL BUS TRANSCEIVERS

SCBS671B AUGUST 1996 REVISED OCTOBER 1997

POST OFFICE BOX 655303

DALLAS, TEXAS 75265

functional block diagram

2A1

Boundary-Control

Register

Bypass Register

Identification

Register

Boundary-Scan Register

Instruction

Register

TAP

Controller

2LEBA

2CLKBA

2OEBA

TDI

TMS

TCK

2B1

TDO

2OEAB

2LEAB

2CLKAB

1A1

1LEBA

1CLKBA

1OEBA

1B1

1OEAB

1LEAB

1CLKAB

VCC

One of Nine Channels

VCC

SN54LVTH18512, SN54LVTH182512, SN74LVTH18512, SN74LVTH182512
3.3-V ABT SCAN TEST DEVICES
WITH 18-BIT UNIVERSAL BUS TRANSCEIVERS

SCBS671B AUGUST 1996 REVISED OCTOBER 1997

POST OFFICE BOX 655303

DALLAS, TEXAS 75265

Terminal Functions

TERMINAL NAME

DESCRIPTION

1A11A9,

2A12A9

Normal-function A-bus I/O ports. See function table for normal-mode logic.

1B11B9,

2B12B9

Normal-function B-bus I/O ports. See function table for normal-mode logic.

1CLKAB, 1CLKBA,

2CLKAB, 2CLKBA

Normal-function clock inputs. See function table for normal-mode logic.

GND

Ground

1LEAB, 1LEBA,

2LEAB, 2LEBA

Normal-function latch enables. See function table for normal-mode logic.

1OEAB, 1OEBA,

2OEAB, 2OEBA

Normal-function output enables. See function table for normal-mode logic. An internal pullup at each terminal forces the
terminal to a high level if left unconnected.

TCK

Test clock. One of four terminals required by IEEE Std 1149.1-1990. Test operations of the device are synchronous to
TCK. Data is captured on the rising edge of TCK and outputs change on the falling edge of TCK.

TDI

Test data input. One of four terminals required by IEEE Std 1149.1-1990. TDI is the serial input for shifting data through
the instruction register or selected data register. An internal pullup forces TDI to a high level if left unconnected.

TDO

Test data output. One of four terminals required by IEEE Std 1149.1-1990. TDO is the serial output for shifting data
through the instruction register or selected data register.

TMS

Test mode select. One of four terminals required by IEEE Std 1149.1-1990. TMS directs the device through its TAP
controller states. An internal pullup forces TMS to a high level if left unconnected.

VCC

Supply voltage

SN54LVTH18512, SN54LVTH182512, SN74LVTH18512, SN74LVTH182512

3.3-V ABT SCAN TEST DEVICES

WITH 18-BIT UNIVERSAL BUS TRANSCEIVERS

SCBS671B AUGUST 1996 REVISED OCTOBER 1997

POST OFFICE BOX 655303

DALLAS, TEXAS 75265

test architecture

Serial-test information is conveyed by means of a 4-wire test bus or TAP, that conforms to IEEE Std 1149.1-1990.
Test instructions, test data, and test control signals all are passed along this serial-test bus. The TAP controller
monitors two signals from the test bus, TCK and TMS. The TAP controller extracts the synchronization (TCK)
and state control (TMS) signals from the test bus and generates the appropriate on-chip control signals for the
test structures in the device. Figure 1 shows the TAP-controller state diagram.

The TAP controller is fully synchronous to the TCK signal. Input data is captured on the rising edge of TCK and
output data changes on the falling edge of TCK. This scheme ensures data to be captured is valid for fully
one-half of the TCK cycle.

The functional block diagram shows the IEEE Std 1149.1-1990 4-wire test bus and boundary-scan architecture
and the relationship among the test bus, the TAP controller, and the test registers. As shown, the device contains
an 8-bit instruction register and four test-data registers: a 48-bit boundary-scan register, a 3-bit
boundary-control register, a 1-bit bypass register, and a 32-bit device identification register.

Test-Logic-Reset

Run-Test/Idle

Select-DR-Scan

Capture-DR

Shift-DR

Exit1-DR

Pause-DR

Update-DR

TMS = L

TMS = H

TMS = L

TMS = H

TMS = L

TMS = H

TMS = L

TMS = H

TMS = L

Exit2-DR

Select-IR-Scan

Capture-IR

Shift-IR

Exit1-IR

Pause-IR

Update-IR

TMS = L

TMS = H

TMS = L

TMS = H

TMS = L

TMS = H

TMS = L

Exit2-IR

TMS = L

TMS = H

TMS = L

TMS = H

TMS = L

TMS = H

TMS = L

Figure 1. TAP-Controller State Diagram

Part Number SN74LVTH182512