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Part Number SN74BCT8373A

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SN54BCT8373A, SN74BCT8373A
SCAN TEST DEVICES
WITH OCTAL D-TYPE LATCHES
SCBS044F ­ JUNE 1990 ­ REVISED JULY 1996
1
POST OFFICE BOX 655303
·
DALLAS, TEXAS 75265
D
Members of the Texas Instruments
SCOPE
TM
Family of Testability Products
D
Octal Test-Integrated Circuits
D
Functionally Equivalent to 'F373 and
'BCT373 in the Normal-Function Mode
D
Compatible With the IEEE Standard
1149.1-1990 (JTAG) Test Access Port and
Boundary-Scan Architecture
D
Test Operation Synchronous to Test
Access Port (TAP)
D
Implement Optional Test Reset Signal by
Recognizing a Double-High-Level Voltage
(10 V ) on TMS Pin
D
SCOPE
TM
Instruction Set
­ IEEE Standard 1149.1-1990 Required
Instructions, Optional INTEST, CLAMP,
and HIGHZ
­ Parallel Signature Analysis at Inputs
­ Pseudo-Random Pattern Generation
From Outputs
­ Sample Inputs / Toggle Outputs
D
Package Options Include Plastic
Small-Outline (DW) Packages, Ceramic
Chip Carriers (FK), and Standard Plastic
and Ceramic 300-mil DIPs (JT, NT)
description
The 'BCT8373A scan test devices with octal
D-type latches are members of the Texas
Instruments SCOPE
TM
testability integrated-
circuit family. This family of devices supports IEEE
Standard 1149.1-1990 boundary scan to facilitate
testing of complex circuit board assemblies. Scan
access to the test circuitry is accomplished via the
4-wire test access port (TAP) interface.
In the normal mode, these devices are functionally equivalent to the 'F373 and 'BCT373 octal D-type latches.
The test circuitry can be activated by the TAP to take snapshot samples of the data appearing at the device
terminals or to perform a self test on the boundary test cells. Activating the TAP in normal mode does not affect
the functional operation of the SCOPE
TM
octal latches.
In the test mode, the normal operation of the SCOPE
TM
octal latches is inhibited and the test circuitry is enabled
to observe and control the I/O boundary of the device. When enabled, the test circuitry can perform boundary
scan test operations, as described in IEEE Standard 1149.1-1990.
Copyright
©
1996, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
SCOPE is a trademark of Texas Instruments Incorporated.
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
LE
1Q
2Q
3Q
4Q
GND
5Q
6Q
7Q
8Q
TDO
TMS
OE
1D
2D
3D
4D
5D
V
CC
6D
7D
8D
TDI
TCK
SN54BCT8373A . . . JT PACKAGE
SN74BCT8373A . . . DW OR NT PACKAGE
(TOP VIEW)
3 2 1 28 27
12 13
5
6
7
8
9
10
11
25
24
23
22
21
20
19
8D
TDI
TCK
NC
TMS
TDO
8Q
2D
1D
OE
NC
LE
1Q
2Q
4
26
14 15 16 17 18
3Q
4Q
GND
NC
5Q
6Q
7Q
3D
4D
5D
NC
V
6D
7D
SN54BCT8373A . . . FK PACKAGE
(TOP VIEW)
NC ­ No internal connection
CC
On products compliant to MIL-PRF-38535, all parameters are tested
unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
SN54BCT8373A, SN74BCT8373A
SCAN TEST DEVICES
WITH OCTAL D-TYPE LATCHES
SCBS044F ­ JUNE 1990 ­ REVISED JULY 1996
2
POST OFFICE BOX 655303
·
DALLAS, TEXAS 75265
description (continued)
Four dedicated test terminals are used to control the operation of the test circuitry: test data input (TDI), test
data output (TDO), test mode select (TMS), and test clock (TCK). Additionally, the test circuitry can perform
other testing functions such as parallel signature analysis (PSA) on data inputs and pseudo-random pattern
generation (PRPG) from data outputs. All testing and scan operations are synchronized to the TAP interface.
The SN54BCT8373A is characterized for operation over the full military temperature range of ­ 55
°
C to 125
°
C.
The SN74BCT8373A is characterized for operation from 0
°
C to 70
°
C.
FUNCTION TABLE
(normal mode, each latch)
INPUTS
OUTPUT
OE
LE
D
Q
L
H
H
H
L
H
L
L
L
L
X
Q0
H
X
X
Z
logic symbol
SCAN
'BCT8373A
1D
23
1D
1Q
2
TDI
14
TDI
TCK-IN
EN
24
22
2D
2Q
3
TMS
12
TMS
13
TCK
C1
1
LE
TCK-OUT
21
3D
3Q
4
20
4D
4Q
5
19
5D
5Q
7
17
6D
6Q
8
16
7D
7Q
9
15
8D
8Q
10
OE
TDO
11
TDO
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
Pin numbers shown are for the DW, JT, and NT packages.
SN54BCT8373A, SN74BCT8373A
SCAN TEST DEVICES
WITH OCTAL D-TYPE LATCHES
SCBS044F ­ JUNE 1990 ­ REVISED JULY 1996
3
POST OFFICE BOX 655303
·
DALLAS, TEXAS 75265
functional block diagram
Boundary- Control
Register
Bypass Register
Boundary-Scan Register
Instruction Register
TDI
TMS
TCK
TDO
TAP
Controller
VCC
VCC
OE
VCC
VCC
VCC
LE
1D
VCC
VCC
One of Eight Channels
1Q
C1
1D
24
1
23
14
12
13
2
11
Pin numbers shown are for the DW, JT, and NT packages.
SN54BCT8373A, SN74BCT8373A
SCAN TEST DEVICES
WITH OCTAL D-TYPE LATCHES
SCBS044F ­ JUNE 1990 ­ REVISED JULY 1996
4
POST OFFICE BOX 655303
·
DALLAS, TEXAS 75265
Terminal Functions
TERMINAL
NAME
DESCRIPTION
1D ­ 8D
Normal-function data inputs. See function table for normal-mode logic. Internal pullups force these inputs to a high level if
left unconnected.
GND
Ground
LE
Normal-function latch-enable input. See function table for normal-mode logic. An internal pullup forces LE to a high level if
left unconnected.
OE
Normal-function output-enable input. See function table for normal-mode logic. An internal pullup forces OE to a high level
if left unconnected.
1Q ­ 8Q
Normal-function data outputs. See function table for normal-mode logic.
TCK
Test clock. One of four terminals required by IEEE Standard 1149.1-1990. Test operations of the device are synchronous to
TCK. Data is captured on the rising edge of TCK and outputs change on the falling edge of TCK. An internal pullup forces
TCK to a high level if left unconnected.
TDI
Test data input. One of four terminals required by IEEE Standard 1149.1-1990. TDI is the serial input for shifting data through
the instruction register or selected data register. An internal pullup forces TDI to a high level if left unconnected.
TDO
Test data output. One of four terminals required by IEEE Standard 1149.1-1990. TDO is the serial output for shifting data
through the instruction register or selected data register. An internal pullup forces TDO to a high level when it is not active
and is not driven from an external source.
TMS
Test mode select. One of four terminals required by IEEE Standard 1149.1-1990. TMS directs the device through its TAP
controller states. An internal pullup forces TMS to a high level if left unconnected. The TMS pin also provides the optional
test reset signal of IEEE Standard 1149.1-1990. This is implemented by recognizing a third logic level, double-high (VIHH),
at TMS.
VCC
Supply voltage
SN54BCT8373A, SN74BCT8373A
SCAN TEST DEVICES
WITH OCTAL D-TYPE LATCHES
SCBS044F ­ JUNE 1990 ­ REVISED JULY 1996
5
POST OFFICE BOX 655303
·
DALLAS, TEXAS 75265
test architecture
Serial test information is conveyed by means of a 4-wire test bus, or TAP, that conforms to IEEE Standard
1149.1-1990. Test instructions, test data, and test control signals all are passed along this serial test bus. The
TAP controller monitors two signals from the test bus, TCK and TMS. The TAP controller extracts the
synchronization (TCK) and state control (TMS) signals from the test bus and generates the appropriate on-chip
control signals for the test structures in the device. Figure 1 shows the TAP-controller state diagram.
The TAP controller is fully synchronous to the TCK signal. Input data is captured on the rising edge of TCK, and
output data changes on the falling edge of TCK. This scheme ensures that data to be captured is valid for fully
one-half of the TCK cycle.
The functional block diagram shows the IEEE Standard 1149.1-1990 4-wire test bus and boundary-scan
architecture and the relationship between the test bus, the TAP controller, and the test registers. As shown, the
device contains an 8-bit instruction register and three test data registers: an 18-bit boundary-scan register, a
2-bit boundary-control register, and a 1-bit bypass register.
Test-Logic-Reset
Run-Test/Idle
Select-DR-Scan
Capture-DR
Shift-DR
Exit1-DR
Pause-DR
Update-DR
TMS = L
TMS = L
TMS = H
TMS = L
TMS = H
TMS = H
TMS = L
TMS = H
TMS = L
TMS = L
TMS = H
TMS = L
Exit2-DR
Select-IR-Scan
Capture-IR
Shift-IR
Exit1-IR
Pause-IR
Update-IR
TMS = L
TMS = L
TMS = H
TMS = L
TMS = H
TMS = H
TMS = L
TMS = H
TMS = L
Exit2-IR
TMS = L
TMS = H
TMS = H
TMS = H
TMS = L
TMS = H
TMS = L
TMS = H
TMS = H
TMS = H
TMS = L
Figure 1. TAP-Controller State Diagram