SN65LVDS2
HIGH-SPEED DIFFERENTIAL LINE RECEIVER
SLLS406 DECEMBER 1999
1
POST OFFICE BOX 655303
·
DALLAS, TEXAS 75265
D
Meets or Exceeds ANSI TIA/EIA-644
Standard
D
Designed for Signaling Rates up to
400 Mbps
D
Operates From a 2.4-V to 3.6-V Supply
D
Available in the SOT-23 Package
D
Differential Input Voltage Threshold Less
Than 100 mV
D
Propagation Delay Times, 2.5 ns Typical
D
Power Dissipation at 200 MHz Is Typically
60 mW
D
Bus-Pin ESD Protection Exceeds 15 kV
D
Open-Circuit Fail Safe
D
Output is High Impedance With V
CC
< 1.5 V
description
The SN65LVDS2 is a single low-voltage differen-
tial line receiver in a small-outline transistor
package. The inputs comply with the TIA/EIA-644
standard and provide a maximum differential input
threshold of 100 mV over an input common-mode
voltage range of 0 V to 2.4 V.
When used with a low-voltage differential
signaling (LVDS) driver (such as the SN65LVDS1)
in a point-to-point or multidrop configuration; data
or clocking signals can be transmitted over printed-circuit board traces or cables at very high rates with very
low electromagnetic emissions and power consumption.
The high-speed switching of LVDS signals requires the use of a line impedance matching resistor at the
receiving-end of the cable or transmission media. TI offers you both the SN65LVDS2, which requires this
external resistor, or its companion the SN65LVDT2, which eliminates the need by integrating it with the receiver.
The packaging, low power, low EMI, high ESD tolerance, and wide supply voltage range make these devices
ideal for battery-powered applications.
The SN65LVDS2 is characterized for operation from 40
°
C to 85
°
C.
Copyright
©
1999, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
3
2
4
5
(TOP VIEW)
1
VCC
GND
A
R
B
SN65LVDS2
DBV PACKAGE
logic diagram
INPUTS
OUTPUT
R
H
?
L
Function Table
A
B
3
4
R
5
VID = VA VB
VID
100 mV
100 mV < VID < 100 mV
VID
100 mV
Open
H
H = high level, L = low level , ? = indeterminate
SN65LVDS2
HIGH-SPEED DIFFERENTIAL LINE RECEIVER
SLLS406 DECEMBER 1999
2
POST OFFICE BOX 655303
·
DALLAS, TEXAS 75265
equivalent input and output schematic diagrams
7 V
VCC
7 V
R Output
VCC
5
B Input
A Input
300 k
300 k
7 V
absolute maximum ratings over operating free-air temperature (unless otherwise noted)
Supply voltage range, V
CC
(see Note 1)
0.5 V to 4 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Voltage range (A, B, or R)
0.5 V to V
CC
+ 0.5 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Electrostatic discharge: A, B , and GND (see Note 2)
CLass 3, A:15 kV, B:600 V
. . . . . . . . . . . . . . . . . . . . . . .
R (see Note 2)
CLass 3, A:7 kV, B:500 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous total power dissipation
See dissipation rating table
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range
65
°
C to 150
°
C
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds
250
°
C
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES:
1. All voltage values, except differential I/O bus voltages are with respect to network ground terminal.
2. Tested in accordance with MIL-STD-883C Method 3015.7.
DISSIPATION RATING TABLE
PACKAGE
TA
25
°
C
POWER RATING
DERATING FACTOR
ABOVE TA = 25
°
C
TA = 85
°
C
POWER RATING
DBV
385 mW
3.1 mW/
°
C
200 mW
This is the inverse of the junction-to-ambient thermal resistance when board-mounted (low-K) and with
no air flow.
recommended operating conditions
MIN
NOM
MAX
UNIT
Supply voltage, VCC
2.4
3.3
3.6
V
Magnitude of differential input voltage,
VID
0.1
0.6
V
Commonmode input voltage, VIC (see Figure 6)
0
2.4
*
V
ID
2
V
Common mode in ut voltage, VIC (see Figure 6)
VCC0.8
V
Operating freeair temperature, TA
40
85
°
C
SN65LVDS2
HIGH-SPEED DIFFERENTIAL LINE RECEIVER
SLLS406 DECEMBER 1999
3
POST OFFICE BOX 655303
·
DALLAS, TEXAS 75265
|VID| Differential Input Voltage V
COMMON-MODE INPUT VOLTAGE
vs
DIFFERENTIAL INPUT VOLTAGE
1
0
0.1
0.3
2
1.5
0.5
0.2
0.4
0.6
2.5
0
0.5
VCC = 2.4 V
Common-Mode Input V
oltage V
V
IC
MIN
VCC = 2.7 V
VCC = 3.6 V
3
0.8
0.7
Figure 1. V
IC
vs V
ID
and V
CC
electrical characteristics over recommended operating conditions, V
CC
= 2.4 to 3 V (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VITH+
Positive-going differential input voltage threshold
See Figure 2 and Table 1
100
mV
VITH
Negative-going differential input voltage threshold
See Figure 2 and Table 1
100
mV
VOH
High-level output voltage
IOH = 8 mA
1.9
2.4
V
VOL
Low-level output voltage
IOL = 8 mA
0.25
0.4
V
ICC
Supply current
No load,
Steady state
4
7
mA
I
Input current (A or B inputs)
VI = 0 V
±
20
A
II
Input current (A or B inputs)
VI = 2.4 V or VCC 0.8
1.2
µ
A
IID
Differential input current (IIA IIB)
VIA = 0 V, VIB = 0.1 V
VIA = 2.4 V VIB = 2.3 V,
±
2
µ
A
II(OFF)
Power-off input current (A or B inputs)
VCC = 0 V, VI = 2.4 V
±
20
µ
A
All typical values are at 25
°
C and with a 2.7-V supply.
receiver switching characteristics over recommended operating conditions, V
CC
= 2.4 to 2.7 V
(unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
tPLH
Propagation delay time, low-to-high-level output
1.4
2.6
3.6
ns
tPHL
Propagation delay time, high-to-low-level output
C
10 F
1.4
2.5
3.6
ns
tsk(p)
Pulse skew (|tpHL tpLH|)
CL = 10 pF,
See Figure 3
0.1
0.6
ns
tr
Output signal rise time
See Figure 3
0.8
1.4
ns
tf
Output signal fall time
0.8
1.4
ns
All typical values are at 25
°
C and with a 2.7-V.
tsk(p) is the magnitude of the time difference between the high-to-low and low-to-high propagation delay times at an output.
SN65LVDS2
HIGH-SPEED DIFFERENTIAL LINE RECEIVER
SLLS406 DECEMBER 1999
4
POST OFFICE BOX 655303
·
DALLAS, TEXAS 75265
electrical characteristics over recommended operating conditions, V
CC
= 3 V to 3.6 V (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VITH+
Positive-going differential input voltage threshold
See Figure 2 and Table 1
100
mV
VITH
Negative-going differential input voltage threshold
See Figure 2 and Table 1
100
mV
VOH
High-level output voltage
IOH = 8 mA
2.4
3
V
VOL
Low-level output voltage
IOL = 8 mA
0.25
0.4
V
ICC
Supply current
No load,
Steady state
5
8
mA
I
Input current (A or B inputs)
VI = 0 V
±
20
µ
A
II
Input current (A or B inputs)
VI = 2.4 V
1.2
µ
A
IID
Differential input current (IIA IIB)
VIA = 0 V, VIB = 0.1 V
VIA = 2.4 V VIB = 2.3 V,
±
2
µ
A
II(OFF)
Power-off input current (A or B inputs)
VCC = 0 V, VI = 2.4 V
20
µ
A
All typical values are at 25
°
C and with a 3.3-V supply.
receiver switching characteristics over recommended operating conditions, V
CC
= 3 V to 3.6 V
(unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
tPLH
Propagation delay time, low-to-high-level output
1.4
2.6
3.1
ns
tPHL
Propagation delay time, high-to-low-level output
C
10 F
1.4
2.5
3.1
ns
tsk(p)
Pulse skew (|tpHL tpLH|)
CL = 10 pF,
See Figure 3
0.1
0.5
ns
tr
Output signal rise time
See Figure 3
0.7
1.1
ns
tf
Output signal fall time
0.7
1.1
ns
All typical values are at 25
°
C and with a 3.3-V.
tsk(p) is the magnitude of the time difference between the high-to-low and low-to-high propagation delay times at an output.
SN65LVDS2
HIGH-SPEED DIFFERENTIAL LINE RECEIVER
SLLS406 DECEMBER 1999
5
POST OFFICE BOX 655303
·
DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
VIB
VID
VIA
VIC
VO
A
B
R
V
IA
)
V
IB
2
Figure 2. Receiver Voltage Definitions
Table 1. Receiver Minimum and Maximum Input Threshold Test Voltages
APPLIED VOLTAGES
(V)
RESULTING DIFFERENTIAL
INPUT VOLTAGE
(mV)
RESULTING COMMON-
MODE INPUT VOLTAGE
(V)
VIA
VIB
VID
VIC
1.25
1.15
100
1.2
1.15
1.25
100
1.2
2.4
2.3
100
2.35
2.3
2.4
100
2.35
0.1
0
100
0.05
0
0.1
100
0.05
1.5
0.9
600
1.2
0.9
1.5
600
1.2
2.4
1.8
600
2.1
1.8
2.4
600
2.1
0.6
0
600
0.3
0
0.6
600
0.3
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