SN54ACT8997, SN74ACT8997
SCAN-PATH LINKERS WITH 4-BIT IDENTIFICATION BUSES
SCAN-CONTROLLED IEEE STD 1149.1 (JTAG) TAP CONCATENATORS
SCAS157D APRIL 1990 REVISED DECEMBER 1996
1
POST OFFICE BOX 655303
·
DALLAS, TEXAS 75265
D
Members of the Texas Instruments
SCOPE
TM
Family of Testability Products
D
Compatible With the IEEE Standard
1149.1-1990 (JTAG) Serial Test Bus
D
Allow Partitioning of System Scan Paths
D
Can Be Cascaded Horizontally or Vertically
D
Select Up to Four Secondary Scan Paths to
Be Included in a Primary Scan Path
D
Include 8-Bit Programmable Binary Counter
to Count or Initiate Interrupt Signals
D
Include 4-Bit Identification Bus for
Scan-Path Identification
D
Inputs Are TTL Compatible
D
EPIC
TM
(Enhanced-Performance Implanted
CMOS) 1-
µ
m Process
D
Package Options Include Plastic
Small-Outline (DW) Packages, Ceramic
Chip Carriers (FK), and Standard Plastic
(NT) and Ceramic (JT) 300-mil DIPs
description
The 'ACT8997 are members of the Texas
Instruments SCOPE
TM
testability integrated-
circuit family. This family of components facilitates
testing of complex circuit-board assemblies.
The 'ACT8997 enhance the scan capability of TI's
SCOPE
TM
family by allowing augmentation of a
system's primary scan path with secondary scan
paths (SSPs), which can be individually selected
by the 'ACT8997 for inclusion in the primary scan
path. These devices also provide buffering of test
signals to reduce the need for external logic.
By loading the proper values into the instruction
register and data registers, the user can select up
to four SSPs to be included in a primary scan path. Any combination of the SSPs can be selected at a time. Any
of the device's six data registers or the instruction register can be placed in the device's scan path, i.e., placed
between test data input (TDI) and test data output (TDO) for subsequent shift and scan operations.
All operations of the device except counting are synchronous to the test clock pin (TCK). The 8-bit
programmable up/down counter can be used to count transitions on the device condition input (DCI) pin and
output interrupt signals via the device condition output (DCO) pin. The device can be configured to count on
either the rising or falling edge of DCI.
The test access port (TAP) controller is a finite-state machine compatible with IEEE Standard 1149.1.
The SN54ACT8997 is characterized for operation over the full military temperature range of 55
°
C to 125
°
C.
The SN74ACT8997 is characterized for operation from 0
°
C to 70
°
C.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
DCO
MCO
DTDO1
DTDO2
DTDO3
DTDO4
GND
DTMS1
DTMS2
DTMS3
DTMS4
DTCK
TDO
TMS
DCI
MCI
TRST
ID1
ID2
ID3
ID4
V
CC
DTDI1
DTDI2
DTDI3
DTDI4
TDI
TCK
SN54ACT8997 . . . JT PACKAGE
SN74ACT8997 . . . DW OR NT PACKAGE
(TOP VIEW)
3
2 1
13 14
5
6
7
8
9
10
11
DTDI3
DTDI4
TDI
TCK
TMS
TDO
DTCK
TRST
MCI
DCI
DCO
MCO
DTDO1
DTDO2
4
15 16 17 18
DTDO4
GND
DTMS1
DTMS2
DTMS3
DTMS4
ID1
ID2
ID3
ID4
SN54ACT8997 . . . FK PACKAGE
(TOP VIEW)
28 27 26
25
24
23
22
21
20
19
12
DTDO3
V
DTDI1
DTDI2
CC
Copyright
©
1996, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
SCOPE and EPIC are trademarks of Texas Instruments Incorporated.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
On products compliant to MIL-PRF-38535, all parameters are tested
unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.
SN54ACT8997, SN74ACT8997
SCAN-PATH LINKERS WITH 4-BIT IDENTIFICATION BUSES
SCAN-CONTROLLED IEEE STD 1149.1 (JTAG) TAP CONCATENATORS
SCAS157D APRIL 1990 REVISED DECEMBER 1996
2
POST OFFICE BOX 655303
·
DALLAS, TEXAS 75265
functional block diagram
DTDO1
DTDO2
DTDO3
TDO
DTCK
TMS
ID(1 4)
MCI
DCI
DTDI1
TDI
TRST
DTDO4
MCO
DCO
DTMS1
DTMS2
DTMS3
DTMS4
DTDI2
DTDI3
DTDI4
TCK
VCC
Scan-Path
Configuration
Data
Registers
Instruction
Register
Test Port
(3 state or
open drain)
VCC
VCC
VCC
VCC
VCC
VCC
16
20
19
18
17
28
27
2225
14
15
26
3
4
5
6
2
1
8
9
10
11
13
12
Pin numbers shown are for the DW, JT, and NT packages.
SN54ACT8997, SN74ACT8997
SCAN-PATH LINKERS WITH 4-BIT IDENTIFICATION BUSES
SCAN-CONTROLLED IEEE STD 1149.1 (JTAG) TAP CONCATENATORS
SCAS157D APRIL 1990 REVISED DECEMBER 1996
3
POST OFFICE BOX 655303
·
DALLAS, TEXAS 75265
functional block description
The 'ACT8997 is intended to link secondary scan paths for inclusion in a primary scan path. Any combination
of the four secondary scan paths can be linked, or the device can be bypassed entirely.
The least-significant bit (LSB) of any value scanned into any register of the device is the first bit shifted in
(nearest to TDO). The most-significant bit (MSB) is the last bit shifted in (nearest to TDI).
The 'ACT8997 is divided into functional blocks as detailed below.
test port
The test port decodes the signals on TCK, TMS, and TRST to control the operation of the circuit. The test port
includes a TAP controller that issues the proper control instructions to the data registers according to the
IEEE Standard 1149.1 protocol. The TAP controller state diagram is shown in Figure 1.
instruction register
The instruction register (IR) is an 8-bit-wide serial-shift register that issues commands to the device. Data is
input to the instruction register via TDI (or one of the DTDI pins) and shifted out via TDO. All device operations
are initiated by loading the proper instruction or sequence of instructions into the IR.
data registers
Six parallel data registers are included in the 'ACT8997: bypass, control, counter, boundary-scan, ID-bus, and
select. The ID bus register is a part of the boundary-scan register. Each data register is serially loaded via TDI
or DTDI and outputs data via TDO. Table 1 summarizes the registers in the 'ACT8997.
scan-path-configuration circuit
This circuit decodes bits in the select and control registers to determine which, if any, of the secondary scan
paths are to be included in the primary scan path.
Table 1. Register Summary
REGISTER
NAME
LENGTH
(BITS)
FUNCTION
Instruction
8
Issue command information to the device
Control
10
Configuration and enable control
Counter
8
Count events on DCI, output interrupts via DCO
Select
8
Select one or more secondary scan paths
Boundary Scan
10
Capture and force test data at device periphery
ID Bus
4
Provide subsystem identification code
Bypass
1
Remove the 'ACT8997 from the scan path
SN54ACT8997, SN74ACT8997
SCAN-PATH LINKERS WITH 4-BIT IDENTIFICATION BUSES
SCAN-CONTROLLED IEEE STD 1149.1 (JTAG) TAP CONCATENATORS
SCAS157D APRIL 1990 REVISED DECEMBER 1996
4
POST OFFICE BOX 655303
·
DALLAS, TEXAS 75265
Terminal Functions
TERMINAL
NAME
I/O
DESCRIPTION
DCI
I
Device condition input. DCI receives interrupt and protocol signals from the secondary scan path(s). When the
counter register is instructed to count up or down, DCI is configured as the counter clock.
DCO
O
Device condition output. DCO is configured by the control register to output protocol and interrupt signals and can
be configured by the control register to output an error signal if the instruction register is loaded with an invalid value.
DCO is further configured by the control register as:
Active high or active low (reset condition = active low)
Open drain or 3 state (reset condition = open drain)
DTCK
O
Device test clock. DTCK outputs the buffered test clock TCK to the secondary scan path(s).
DTDI1
DTDI2
DTDI3
DTDI4
I
Device test data input 14. DTDI1DTDI4 receive the serial test data output(s) of the selected secondary scan
path(s). An internal pullup forces DTDI1DTDI4 to a high logic level if it is left unconnected.
DTDO1
DTDO2
DTDO3
DTDO4
O
Device test data output 14. These outputs send serial test data to the TDI input(s) of the secondary scan path(s).
DTMS1
DTMS2
DTMS3
DTMS4
O
Device test mode select 14. Any combination of these four outputs can be selected to follow TMS to direct the
secondary scan path(s) through the TAP controller states in Figure 1. The unselected DTMS outputs can be set
independently to a high or low logic level. The TMS circuit monitors input from the select register to determine the
configuration of the DTMS outputs.
GND
Ground
IDI
ID2
ID3
ID4
I
Identification 14. This 4-bit data bus can be hardwired to provide identification of the subsystem under test. The
value present on the bus can be scanned out through the boundary scan or ID bus registers.
MCI
I
Master condition input. MCI receives interrupt and protocol signals from a primary bus controller (PBC). The level
on MCI is buffered and output on MCO.
MCO
O
Master condition output. MCO transmits interrupt and protocol signals to the secondary scan path(s).
TCK
I
Test clock. One of four terminals required by IEEE Standard 1149.1. All operations of the 'ACT8997 except for the
count function are synchronous to TCK. Data on the device inputs is captured on the rising edge of TCK, and outputs
change on the falling edge of TCK.
TDI
I
Test data input. One of four terminals required by IEEE Standard 1149.1. TDI is the serial input for shifting information
into the instruction register or selected data register. TDI is typically driven by the TDO of the PBC. An internal pullup
forces TDI to a high level if left unconnected.
TDO
O
Test data output. One of four terminals required by IEEE Standard 1149.1. TDO is the serial output for shifting
information out of the instruction register or selected data register. TDO is typically connected to the TDI of the next
scannable device in the primary scan path.
TMS
I
Test mode select. One of four terminals required by IEEE Standard 1149.1. The level of TMS at the rising edge of
TCK directs the 'ACT8997 through its TAP controller states. An internal pullup forces TMS to a high level if left
unconnected.
TRST
I
Test reset. This active-low input implements the optional reset terminal of IEEE Standard 1149.1. When asserted,
TRST causes the 'ACT8997 to go to the Test-Logic-Reset state and configure the instruction register and data
registers to their power-up values. An internal pullup forces TRST to a high level if left unconnected.
VCC
Supply voltage
SN54ACT8997, SN74ACT8997
SCAN-PATH LINKERS WITH 4-BIT IDENTIFICATION BUSES
SCAN-CONTROLLED IEEE STD 1149.1 (JTAG) TAP CONCATENATORS
SCAS157D APRIL 1990 REVISED DECEMBER 1996
5
POST OFFICE BOX 655303
·
DALLAS, TEXAS 75265
state diagram description
The TAP proceeds through the states in Figure 1 according to IEEE Standard 1149.1. There are six stable states
(indicated by a looping arrow) and ten unstable states in the diagram. A stable state is a state the TAP can retain
for consecutive TCK cycles. Any state that does not meet this criterion is an unstable state.
There are two main paths through the state diagram: one to manipulate a data register and one to manipulate
the instruction register. No more than one register can be manipulated at a time.
Run-Test /Idle
TMS = L
Test-Logic-Reset
Select-DR-Scan
Select-IR-Scan
Capture-DR
Shift-DR
Exit1-DR
Pause-DR
Exit2-DR
Update-DR
Capture-IR
Shift-IR
Exit1-IR
Pause-IR
Exit2-IR
Update-IR
TMS = H
TMS = L
TMS = H
TMS = H
TMS = L
TMS = L
TMS = L
TMS = L
TMS = H
TMS = H
TMS = L
TMS = L
TMS = H
TMS = H
TMS = H
TMS = H
TMS = H
TMS = H
TMS = L
TMS = L
TMS = H
TMS = H
TMS = H
TMS = L
TMS = L
TMS = H
TMS = H
TMS = L
TMS = L
TMS = L
TMS = L
Figure 1. TAP-Controller State Diagram
SN54ACT8997, SN74ACT8997
SCAN-PATH LINKERS WITH 4-BIT IDENTIFICATION BUSES
SCAN-CONTROLLED IEEE STD 1149.1 (JTAG) TAP CONCATENATORS
SCAS157D APRIL 1990 REVISED DECEMBER 1996
6
POST OFFICE BOX 655303
·
DALLAS, TEXAS 75265
Test-Logic-Reset
In this state, the test logic is inactive and an internal reset signal is applied to all registers in the device. During
device operation, the TAP returns to this state in no more than five TCK cycles if the test mode select (TMS)
input is high. The TMS pin has an internal pullup that forces it to a high level if it is left unconnected or if a board
defect causes it to be open circuited. The device powers up in the Test-Logic-Reset state.
Run-Test /Idle
The TAP must pass through this state before executing any test operations. The TAP may retain this state
indefinitely, and no registers are modified while in Run-Test /Idle. The 8-bit programmable up/down counter can
be operated in this state.
Select-DR-Scan, Select-IR-Scan
No specific function is performed in these states; the TAP exits either of them on the next TCK cycle.
Capture-DR
The selected data register is placed in the scan path (i.e., between TDI and TDO). Depending on the current
instruction, data may or may not be loaded or captured by that register on the rising edge of TCK, causing the
TAP state to change.
Shift-DR
In this state, data is serially shifted through the selected data register from TDI to TDO on each TCK cycle. The
first shift does not occur until the first TCK cycle after entering this state (i.e., no shifting occurs during the TCK
cycle in which the TAP changes from Capture-DR to Shift-DR or from Exit2-DR to Shift-DR). On the falling edge
of TCK in Shift-DR, TDO goes from the high-impedance state to the active state. TDO enables to the value
present in the least-significant bit of the selected data register.
Exit1-DR, Exit2-DR
These are temporary states that end the shifting process. It is possible to return to the Shift-DR state from either
Exit1-DR or Exit2-DR without recapturing the data register. The last shift occurs on the TCK cycle in which the
TAP state changes from Shift-DR to Exit-DR. TDO changes from the active state to the high-impedance state
on the falling edge of TCK in Exit1-DR.
Pause-DR
The TAP can remain in this state indefinitely. The Pause-DR state suspends and resumes shift operations
without loss of data.
Update-DR
If the current instruction calls for the latches in the selected data register to be updated with current data, the
latches are updated only during this state.
Capture-IR
The instruction register is preloaded with the IR status word (see Table 4) and placed in the scan path.
Shift-IR
In this state, data is serially shifted through the instruction register from TDI to TDO on each TCK cycle. The
first shift does not occur until the first TCK cycle after entering this state (i.e., no shifting occurs during the TCK
cycle in which the TAP changes from Capture-IR to Shift-IR or from Exit2-IR to Shift-IR). On the falling edge of
TCK in Shift-IR, TDO goes from the high-impedance state to the active state, and will enable to a high level.
SN54ACT8997, SN74ACT8997
SCAN-PATH LINKERS WITH 4-BIT IDENTIFICATION BUSES
SCAN-CONTROLLED IEEE STD 1149.1 (JTAG) TAP CONCATENATORS
SCAS157D APRIL 1990 REVISED DECEMBER 1996
7
POST OFFICE BOX 655303
·
DALLAS, TEXAS 75265
Exit1-IR, Exit2-IR
These are temporary states that end the shifting process. It is possible to return to the Shift-IR state from either
Exit1-IR or Exit2-IR without recapturing the instruction register. The last shift occurs on the TCK cycle in which
the TAP state changes from Shift-IR to Exit1-IR. TDO changes from the active state to the high-impedance state
on the falling edge of TCK in Exit1-IR.
Pause-IR
The TAP can remain in this state indefinitely. The Pause-IR state suspends and resumes shift operations without
loss of data.
Update-IR
In this state, the latches shadowing the instruction register are updated with the new instruction.
instruction-register description
The instruction register (IR) is an 8-bit serial register that outputs control signals to the device. Table 2 lists the
instructions implemented in the 'ACT8997 and the data register selected by each instruction. The MSB of the
IR is an even-parity bit. If the value scanned into the IR during Shift-IR does not contain even parity, an error
signal (IRERR) is generated internally as shown in Table 3. The 'ACT8997 can be configured to output IRERR
via DCO if the TAP enters the Pause-IR state.
During the Capture-IR state, the IR status word is loaded.The IR status word contains information about the
most recently loaded value of the instruction register and the logic level present at the DCI input. The IR status
word is encoded as shown in Table 4. Figure 2 shows the order of scan for the IR.
TDO
Bit 7
(MSB)
TDI or DTDI
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
(LSB)
Figure 2. Instruction-Register Bits and Order of Scan
SN54ACT8997, SN74ACT8997
SCAN-PATH LINKERS WITH 4-BIT IDENTIFICATION BUSES
SCAN-CONTROLLED IEEE STD 1149.1 (JTAG) TAP CONCATENATORS
SCAS157D APRIL 1990 REVISED DECEMBER 1996
8
POST OFFICE BOX 655303
·
DALLAS, TEXAS 75265
Table 2. Instruction-Register Opcodes
BINARY CODE
BIT 7
BIT 0
MSB
LSB
HEX
VALUE
SCOPE OPCODE
DESCRIPTION
SELECTED DATA
REGISTER
MODE
00000000
00
EXTEST
Boundary scan
Boundary scan
Test
10000001
81
BYPASS
Bypass scan
Bypass
Normal
10000010
82
SAMPLE/PRELOAD
Sample boundary
Boundary scan
Normal
00000011
03
INTEST
Boundary scan
Boundary scan
Test
10000100
84
BYPASS
Bypass scan
Bypass
Normal
00000101
05
BYPASS
Bypass scan
Bypass
Normal
00000110
06
BYPASS
Bypass scan
Bypass
Normal
10000111
87
BYPASS
Bypass scan
Bypass
Normal
10001000
88
COUNT
Count
Bypass
Normal
00001001
09
COUNT
Count
Bypass
Normal
00001010
0A
BYPASS
Bypass scan
Bypass
Normal
10001011
8B
BYPASS
Bypass scan
Bypass
Normal
00001100
0C
BYPASS
Bypass scan
Bypass
Normal
10001101
8D
BYPASS
Bypass scan
Bypass
Normal
10001110
8E
SCANCN
Control register scan
Control
Normal
00001111
0F
SCANCN
Control register scan
Control
Normal
11111010
FA
SCANCNT
Counter scan
Counter
Normal
01111011
7B
READCNT
Counter read
Counter
Normal
11111100
FC
SCANIDB
ID bus register scan
ID bus
Normal
01111101
7D
READIDB
ID bus register read
ID bus
Normal
01111110
7E
SCANSEL
Select register scan
Select
Normal
All others
BYPASS
Bypass scan
Bypass
Normal
A SCOPE opcode exists but is not supported by the 'ACT8997.
Table 3. IRERR Function Table
NO. OF INSTRUCTION
REGISTER BITS = 1
IRERR
0, 2, 4, 6, 8
1
1, 3, 5, 7
0
Table 4. Instruction-Register Status Word
IR BIT
VALUE
7
IRERR (see Table 3)
6
0
5
0
4
0
3
DCI (1 = active, 0 = inactive)
2
0
1
0
0
1
This value is loaded in the instruction
register during the Capture-IR TAP state.
SN54ACT8997, SN74ACT8997
SCAN-PATH LINKERS WITH 4-BIT IDENTIFICATION BUSES
SCAN-CONTROLLED IEEE STD 1149.1 (JTAG) TAP CONCATENATORS
SCAS157D APRIL 1990 REVISED DECEMBER 1996
9
POST OFFICE BOX 655303
·
DALLAS, TEXAS 75265
instruction-register opcode description
The operation of the 'ACT8997 is dependent on the instruction loaded into the IR. Each instruction selects one
of the data registers to be placed between TDI or DTDI and TDO during the Shift-DR TAP state. All the required
instructions of IEEE Standard 1149.1 are implemented in the 'ACT8997.
boundary scan
This instruction implements the required EXTEST and optional INTEST operations of IEEE Standard 1149.1.
The boundary-scan register (which includes the ID-bus register) is placed in the scan path. Data appearing at
input pins included in the boundary-scan register is captured. Data previously loaded into the output pins
included in the boundary-scan register is forced through the outputs.
bypass scan
This instruction implements the required BYPASS operation of IEEE Standard 1149.1. The bypass register is
placed in the scan path and preloads with a logic 0 during Capture-DR.
sample boundary
This instruction implements the required SAMPLE/PRELOAD operation of IEEE Standard 1149.1. The
boundary-scan register is placed in the scan path, and data appearing at the inputs and outputs included in the
boundary-scan register is sampled on the rising edge of TCK in Capture-DR.
count
The counter register begins counting on each DCI transition. The count begins from the value present in the
register before the count instruction was loaded. The counter can be configured by the control register to count
up or down on either the low-to-high or high-to-low transition of DCI. Counting occurs only while in the
Run-Test /Idle TAP state.
control-register scan
The control register is placed in the scan path for a subsequent shift operation. The register is not preloaded
during Capture-DR.
counter-register scan
The counter register is placed in the scan path. During Capture-DR, the current value of the counter is loaded
in the counter register. At Update-DR, the newly shifted value is preloaded to the counter.
counter-register read
The counter register is placed in the scan path. During Capture-DR, the prior preload value of the counter is
loaded into the counter register. At Update-DR, the newly shifted value is preloaded to the counter.
ID-bus-register scan
The ID-bus register (a subset of the boundary-scan register) is placed in the scan path for a subsequent shift
operation. The data appearing on the ID bus is loaded into the ID-bus register on the rising edge of TCK in
Capture-DR.
ID-bus-register read
The ID-bus register is placed in the scan path for a subsequent shift operation. The register is not preloaded
during Capture-DR.
select-register scan
The select register is placed in the scan path for a subsequent shift operation. The register is not preloaded
during Capture-DR.
SN54ACT8997, SN74ACT8997
SCAN-PATH LINKERS WITH 4-BIT IDENTIFICATION BUSES
SCAN-CONTROLLED IEEE STD 1149.1 (JTAG) TAP CONCATENATORS
SCAS157D APRIL 1990 REVISED DECEMBER 1996
10
POST OFFICE BOX 655303
·
DALLAS, TEXAS 75265
control register description
The control register (CTLR) is a 10-bit serial register that controls the enable and select functions of the
'ACT8997. A reset operation forces all bits to a low logic level. The contents of the CTLR are latched and
decoded during the Update-DR TAP state. The specific function of each bit is listed in Table 5. The enable and
select functions of the CTLR bits are mapped as follows:
Table 5. Control-Register Bit Mapping
BIT
VALUE
FUNCTION
9
0
Configure counter to count up
9
1
Configure counter to count down
8
0
Do not stop counting when the count reaches 00000000
8
1
Stop counting when the count reaches 00000000 (count down only)
7
0
Configure DCO as an active-low output
7
1
Configure DCO as an active-high output
00
DCO = Inactive (level depends on CTLR bit 7)
6 5
01
DCO = IRERR
6, 5
10
DCO = CE, an internal logic 0 generated when the count is 00000000 (count down) or 11111111 (count up)
11
DCO = DCI
4
0
Do not mask IRERR from DCO
4
1
Mask IRERR from DCO
3
0
Configure DCO as an open-drain output
3
1
Configure DCO as a 3-state output
2
0
Disable DCO
2
1
Enable DCO
1
0
Configure DCI as an active-low input
1
1
Configure DCI as an active-high input
0
0
Enable DTCK, DTDO(14), and DTMS(14) [outputs DTDO(14) depend on select register (see Table 7)]
0
1
Disable DTCK, DTDO(14), and DTMS(14)
Bit 9 Up/Down
This bit sets the count mode of the counter register (reset condition = count up).
Bit 8 Latch on Zero
The counter register can be configured to stop counting when its value is 00000000 and ignore subsequent
transitions on the counter clock, DCI. The latch-on-zero option is valid only in the count-down mode
(reset condition = do not latch on zero). The value of this bit has no effect on the operation of the counter if
CTLR bit 9 = 0.
Bit 7 DCO Polarity Select
DCO can be configured as an active-low or active-high output (reset condition = active low).
Bit 6/Bit 5 DCO Source Select 1/DCO Source Select 0
DCO can be used to output the IRERR signal generated by the 'ACT8997 (see Table 3). Bits 6 and 5 can be
set to output IRERR via DCO on the falling edge of TCK in the Pause-IR state. DCO can also be configured
to become active when the value of the counter is 00000000, to follow DCI, or be set to a static high or low level
(reset condition = static high level).
SN54ACT8997, SN74ACT8997
SCAN-PATH LINKERS WITH 4-BIT IDENTIFICATION BUSES
SCAN-CONTROLLED IEEE STD 1149.1 (JTAG) TAP CONCATENATORS
SCAS157D APRIL 1990 REVISED DECEMBER 1996
11
POST OFFICE BOX 655303
·
DALLAS, TEXAS 75265
Bit 4 Parity Mask
The signal IRERR can be masked from appearing on DCO even if bits 6 and 5 are set such that it is output in
the Pause-IR state (reset condition = do not mask IRERR).
Bit DCO Drive Select
DCO can be configured as either an open-drain or 3-state output (reset condition = open drain). The open-drain
configuration allows multiple DCO outputs to be used in a wired-OR or wired-AND application. The 3-state
configuration allows the DCO output to be connected to a bus.
Bit 2 DCO Enable
When configured as a 3-state output, DCO can be placed in the high-impedance state
(reset condition = disabled). If configured as an open-drain output and disabled, DCO outputs a high level.
Bit 1 DCI Polarity Select
DCI can be configured as an active-low or active-high input (reset condition = active low).
Bit 0 Device Test Pins Output Enable (active low)
DTCK, DTDO14, and DTMS14 pins can be placed in the high-impedance state (disabled) with this bit
(reset condition = not disabled). If DTDO14 pins are not disabled using this control bit, then their drive state
is dependent on the value of the select register (see Table 7).
Several CTLR bits affect the functionality of the DCO output. The DCO function table is given in Table 6. Figure 3
illustrates the order of scan for the CTLR.
Bit 9
(MSB)
TDI or DTDI
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
(LSB)
TDO
Figure 3. Control-Register Bits and Order of Scan
SN54ACT8997, SN74ACT8997
SCAN-PATH LINKERS WITH 4-BIT IDENTIFICATION BUSES
SCAN-CONTROLLED IEEE STD 1149.1 (JTAG) TAP CONCATENATORS
SCAS157D APRIL 1990 REVISED DECEMBER 1996
12
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·
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Table 6. DCO Function Table
DCI
INTERNAL
SIGNALS
CONTROL-REGISTER BITS
DCO
IRERR
CE
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
X
X
X
X
X
X
X
0
0
X
H
X
X
X
X
X
X
X
1
0
X
Z
X
X
X
0
0
0
X
X
1
X
H
X
X
X
1
0
0
X
X
1
X
L
X
X
X
0
0
1
1
X
1
X
H
X
X
X
1
0
1
1
X
1
X
L
X
0
X
0
0
1
0
X
1
X
L in Pause-IR§, H otherwise
X
1
X
0
0
1
0
X
1
X
H
X
0
X
1
0
1
0
X
1
X
H in Pause-IR§, L otherwise
X
1
X
1
0
1
0
X
1
X
L
X
X
0
0
1
0
X
X
1
X
L
X
X
0
1
1
0
X
X
1
X
H
X
X
1
0
1
0
X
X
1
X
H
X
X
1
1
1
0
X
X
1
X
L
L
X
X
1
1
1
X
X
1
0
H
L
X
X
1
1
1
X
X
1
1
L
L
X
X
0
1
1
X
X
1
0
L
L
X
X
0
1
1
X
X
1
1
H
H
X
X
1
1
1
X
X
1
0
L
H
X
X
1
1
1
X
X
1
1
H
H
X
X
0
1
1
X
X
1
0
H
H
X
X
0
1
1
X
X
1
1
L
These signals are generated as described elsewhere in this data sheet.
The control register must contain these values after the TAP has passed through its most recent Update-DR state.
§ DCO becomes active on the falling edge of TCK as the TAP enters the Pause-IR state and becomes inactive on the
falling edge of TCK as the TAP enters Exit2-IR.
SN54ACT8997, SN74ACT8997
SCAN-PATH LINKERS WITH 4-BIT IDENTIFICATION BUSES
SCAN-CONTROLLED IEEE STD 1149.1 (JTAG) TAP CONCATENATORS
SCAS157D APRIL 1990 REVISED DECEMBER 1996
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select register description
The select register (SR) is an 8-bit serial register that determines which, if any, of the secondary scan paths
(SSPs) will be included in the primary scan path. A reset operation forces all bits to a logic 0. The register is
divided into four 2-bit sections, each of which controls one SSP. Figure 4 shows the mapping of the bits to the
SSPs and the order of scan. For each SSP, the higher-order bit is the MSB and the lower-order bit is the LSB
(e.g., bit 3 is the MSB of SSP2 and bit 2 is the LSB of SSP2).
TDO
Bit 7
(MSB)
TDI or DTDI
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
(LSB)
SSP4
SSP3
SSP2
SSP1
Figure 4. Select Register Bits and Order of Scan
When a new 8-bit value is loaded into the SR, the configuration of one or more DTMS pins may change. If the
new value of the SR configures a DTMS pin to a static (high or low) level, it assumes that level on the falling
edge of TCK in the Update-DR TAP state. This condition is independent of any previous SR configurations. If
the new value of the SR forces a DTMS pin to follow TMS (i.e., select the secondary scan path) and one or more
DTMS pins are currently in the TMS-follow mode, the transfer of DTMS lines occurs on the falling edge of TCK
in the Update-DR TAP state. If, however, the new configuration forces a DTMS pin to follow TMS while no other
DTMS pin is selected, the DTMS pin is forced low and does not begin following TMS until the falling edge of
TCK in the Run-Test/Idle TAP state; therefore, when an SSP is initially selected, the TAP state should travel from
Update-DR to Run-Test /Idle, not from Update-DR to Select-DR-Scan.
Although any combination of SSPs can be selected, the order of scan for each combination is fixed (see data
flow description for details). The SR bit decoding is shown in Table 7.
Table 7. Select Register-Bit Decoding
MSB
LSB
DTMS
SOURCE
DTDO
STATUS
0
0
H
Z
0
1
L
Z
1
X
TMS
Active
The DTDO14 outputs are active only in
the Shift-IR and Shift-DR TAP states.
SN54ACT8997, SN74ACT8997
SCAN-PATH LINKERS WITH 4-BIT IDENTIFICATION BUSES
SCAN-CONTROLLED IEEE STD 1149.1 (JTAG) TAP CONCATENATORS
SCAS157D APRIL 1990 REVISED DECEMBER 1996
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boundary-scan register/ID-bus register description
The boundary-scan register (BSR) is a 10-bit serial register that can be used to capture data appearing at
selected device inputs, force data through device outputs, and apply data to the device's internal logic. The BSR
is made up of boundary-scan cells (BSCs). Table 8 lists the device signal for each of the 10 BSCs that comprise
the BSR. A reset operation does not affect the contents of the BSR.
Table 8. Boundary-Scan Register Bit Mapping
BIT
TERMINAL
NAME
SIGNAL DESCRIPTION
9
MCI
Master condition in
8
MCO
Master condition out
7
DCI
Device condition in
6
DCOTS
Enable control for DCO in 3-state configuration (active low)
5
DCOOD
Enable control for DCO in open-drain configuration (active low)
4
DCO
Device condition out
3
ID4
Identification bus bit 4
2
ID3
Identification bus bit 3
1
ID2
Identification bus bit 2
0
ID1
Identification bus bit 1
This internal signal cannot be observed from the I/O terminals of the device.
The four BSCs connected to the ID(1 4) terminals form a subset of the BSR called the ID-bus register (IDBR).
The IDBR can be scanned without accessing the remaining BSCs of the BSR. Figure 5 shows the order of scan
for the BSR and IDBR.
Bit 9
(MSB)
TDI or DTDI
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
(LSB)
TDO
TDI or DTDI
IDBR
BSR
Figure 5. Boundary-Scan Register Bits and Order of Scan
bypass register description
The bypass register (BR) is a 1-bit serial register. The BR provides a means of effectively removing the
'ACT8997 from the primary scan path when it is not needed for the current test operation. Any selected
secondary scan paths remain active in the primary scan path as described in the data flow description. At power
up, the BR is placed in the scan path. During Capture-DR, the BR is preloaded with a low logic level. Figure 6
shows the order of scan for the bypass register.
TDO
TDI or DTDI
Bit 0
Figure 6. Bypass-Register Bit and Order of Scan
SN54ACT8997, SN74ACT8997
SCAN-PATH LINKERS WITH 4-BIT IDENTIFICATION BUSES
SCAN-CONTROLLED IEEE STD 1149.1 (JTAG) TAP CONCATENATORS
SCAS157D APRIL 1990 REVISED DECEMBER 1996
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counter register description
The counter register (CNTR) is an 8-bit serial register and an associated 8-bit parallel-load up/down counter.
A reset operation forces all bits of the shift register to a logic 0 but does not affect the counter. The counter can
be preloaded with an initial value before counting begins, and the current value of the counter scanned out via
the shift register. The CNTR can be used to count events occurring on the secondary scan path(s) using the
DCI pin as a counter clock and can output interrupt signals via DCO when the count has reached its end value.
An internal signal, CE, is generated as a logic 0 when the count reaches its end value (i.e., 00000000 for count
down, 11111111 for count up). For any other count value, CE is a logic 1. Many of the features of the CNTR are
configured by a bit in the CTLR including:
Count direction up or down (control register bit 9; reset condition = count up).
Stop counting upon counting down to 00000000 (control register bit 8; reset condition = do not latch on zero).
Output CE signals at DCO (control register bits 5 and 6; reset condition = do not output CE at DCO).
Edge of DCI on which to trigger (control register bit 1; reset condition = positive edge).
Figure 7 shows the order of scan for the CNTR.
TDO
Bit 7
(MSB)
TDI or DTDI
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
(LSB)
Figure 7. Counter-Register Bits and Order of Scan
SN54ACT8997, SN74ACT8997
SCAN-PATH LINKERS WITH 4-BIT IDENTIFICATION BUSES
SCAN-CONTROLLED IEEE STD 1149.1 (JTAG) TAP CONCATENATORS
SCAS157D APRIL 1990 REVISED DECEMBER 1996
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DALLAS, TEXAS 75265
data flow description
The direction of serial-data flow in the 'ACT8997 is dependent on the current instruction and value of the SR.
Figure 8 shows the data flow when one or more SSPs have been selected. When more than one SSP has been
selected, the order of scan is determined by which SSPs have been selected as shown in Table 9. The 'ACT8997
add one bit of delay from TDI or DTDI to DTDO.
TDI
DTDOn
TDI
TDO
DTDIn
TDO
(1-bit delay)
SSPn
TDI
TDO
IR or
Selected DR
Selected Scan Path
NO SECONDARY SCAN PATH SELECTED
ONE SECONDARY SCAN PATH SELECTED
TDI
DTDOx
TDI
TDO
DTDIm
TDO
(1-bit delay)
SSPx
IR or
Selected DR
Selected Scan Path
MULTIPLE SECONDARY SCAN PATHS SELECTED
DTDIx
DTDOn
(1-bit delay)
TDI
TDO
SSPn
Selected Scan Path
DTDIn
DTDOm
(1-bit delay)
TDI
TDO
SSPm
Selected Scan Path
'ACT8997
'ACT8997
'ACT8997
'ACT8997
'ACT8997
'ACT8997
'ACT8997
IR or
Selected DR
Figure 8. Data Flow in the 'ACT8997
SN54ACT8997, SN74ACT8997
SCAN-PATH LINKERS WITH 4-BIT IDENTIFICATION BUSES
SCAN-CONTROLLED IEEE STD 1149.1 (JTAG) TAP CONCATENATORS
SCAS157D APRIL 1990 REVISED DECEMBER 1996
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DALLAS, TEXAS 75265
Table 9. Scan-Path Configurations
SR BIT
SSP CONFIGURATION
SCAN PATH CONFIGURATION
7
5
3
1
SSP4
SSP3
SSP2
SSP1
SCAN-PATH CONFIGURATION
0
0
0
0
Inactive
Inactive
Inactive
Inactive
TDISPLTDO
0
0
0
1
Inactive
Inactive
Inactive
Active
TDI(1)SSP1SPLTDO
0
0
1
0
Inactive
Inactive
Active
Inactive
TDI(1)SSP2SPLTDO
0
0
1
1
Inactive
Inactive
Active
Active
TDI(1)SSP1(1)SSP2SPLTDO
0
1
0
0
Inactive
Active
Inactive
Inactive
TDI(1)SSP3SPLTDO
0
1
0
1
Inactive
Active
Inactive
Active
TDI(1)SSP1(1)SSP3SPLTDO
0
1
1
0
Inactive
Active
Active
Inactive
TDI(1)SSP2(1)SSP3SPLTDO
0
1
1
1
Inactive
Active
Active
Active
TDI(1)SSP1(1)SSP2(1)SSP3SPLTDO
1
0
0
0
Active
Inactive
Inactive
Inactive
TDI(1)SSP4SPLTDO
1
0
0
1
Active
Inactive
Inactive
Active
TDI(1)SSP1(1)SSP4SPLTDO
1
0
1
0
Active
Inactive
Active
Inactive
TDI(1)SSP2(1)SSP4SPLTDO
1
0
1
1
Active
Inactive
Active
Active
TDI(1)SSP1(1)SSP2(1)SSP4SPLTDO
1
1
0
0
Active
Active
Inactive
Inactive
TDI(1)SSP3(1)SSP4SPLTDO
1
1
0
1
Active
Active
Inactive
Active
TDI(1)SSP1(1)SSP3(1)SSP4SPLTDO
1
1
1
0
Active
Active
Active
Inactive
TDI(1)SSP2(1)SSP3(1)SSP4SPLTDO
1
1
1
1
Active
Active
Active
Active
TDI(1)SSP1(1)SSP2(1)SSP3(1)SSP4SPLTDO
The scan-path configuration is the order of scan, beginning with the TDI of the 'ACT8997 and ending with the TDO of the 'ACT8997.
A (1) indicates one bit of delay through the 'ACT8997. SPL indicates the selected scan register within the 'ACT8997.
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
§
Supply voltage range, V
CC
0.5 V to 7 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range, V
I
(see Note 1)
0.5 V to V
CC
+ 0.5 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output voltage range, V
O
(see Note 1)
0.5 V to V
CC
+ 0.5 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input clamp current, I
IK
(V
I
< 0 or V
I
> V
CC
)
±
20 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output clamp current, I
OK
(V
I
< 0 or V
I
> V
CC
)
±
20 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous output current, I
O
(V
O
= 0 to V
CC
)
±
25 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Maximum power dissipation at T
A
= 55
°
C (in still air) (see Note 2): DW package
1.7 W
. . . . . . . . . . . . . . . . . .
NT package
1.3 W
. . . . . . . . . . . . . . . . . . .
Storage temperature range, T
stg
65
°
C to 150
°
C
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
§ Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES:
1. The input and output voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. The maximum package power dissipation is calculated using a junction temperature of 150
°
C and a board trace length of 750 mils,
except for the NT package, which has trace length of zero. For more information, refer to the
Package Thermal Considerations
application note in the
ABT Advanced BiCMOS Technology Data Book, literature number SCBD002.
SN54ACT8997, SN74ACT8997
SCAN-PATH LINKERS WITH 4-BIT IDENTIFICATION BUSES
SCAN-CONTROLLED IEEE STD 1149.1 (JTAG) TAP CONCATENATORS
SCAS157D APRIL 1990 REVISED DECEMBER 1996
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DALLAS, TEXAS 75265
recommended operating conditions
SN54ACT8997
SN74ACT8997
UNIT
MIN
MAX
MIN
MAX
UNIT
VCC
Supply voltage
4.5
5.5
4.5
5.5
V
VIH
High-level input voltage
2
2
V
VIL
Low-level input voltage
0.8
0.8
V
VI
Input voltage
0
VCC
0
VCC
V
VO
Output voltage
0
VCC
0
VCC
V
IOH
High level output current
TDO, DTDO(14), MCO
7
10
mA
IOH
High-level output current
DTMS(14), DCO (3 state), DTCK
11
16
mA
TDO, DTDO(14), MCO
7
10
IOL
Low level output current
DCO (open drain or 3 state)
11
16
mA
IOL
Low-level output current
DTMS(14)
16
24
mA
DTCK
32
48
TA
Operating free-air temperature
55
125
0
70
°
C
SN54ACT8997, SN74ACT8997
SCAN-PATH LINKERS WITH 4-BIT IDENTIFICATION BUSES
SCAN-CONTROLLED IEEE STD 1149.1 (JTAG) TAP CONCATENATORS
SCAS157D APRIL 1990 REVISED DECEMBER 1996
19
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DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
SN54ACT8997
SN74ACT8997
UNIT
PARAMETER
TEST CONDITIONS
MIN
MAX
MIN
TYP
MAX
UNIT
TDO DTDO(1 4) MCO
VCC = 4 5 V
IOH = 7 mA
3.6
VOH
TDO, DTDO(14), MCO
VCC = 4.5 V
IOH = 10 mA
3.7
V
VOH
DTMS(14), DCO (3 state),
VCC = 4 5 V
IOH = 11 mA
3.6
V
(
),
(
),
DTCK
VCC = 4.5 V
IOH = 16 mA
3.7
TDO DTDO(1 4) MCO
VCC = 4 5 V
IOL = 7 mA
0.5
TDO, DTDO(14), MCO
VCC = 4.5 V
IOL = 10 mA
0.5
DCO (open drain or 3 state)
VCC = 4 5 V
IOL = 11 mA
0.5
VOL
DCO (open drain or 3 state)
VCC = 4.5 V
IOL = 16 mA
0.5
V
VOL
DTMS(1 4)
VCC = 4 5 V
IOL = 16 mA
0.5
V
DTMS(14)
VCC = 4.5 V
IOL = 24 mA
0.5
DTCK
VCC = 4 5 V
IOL = 32 mA
0.5
DTCK
VCC = 4.5 V
IOL = 48 mA
0.5
IOZ
DTDO(14), DTMS(14),
DCO, DTCK
VCC = 5.5 V,
VO = VCC or GND
±
10
±
5
µ
A
IOH
DCO (open drain)
VCC = 5.5 V,
VO = VCC
20
10
µ
A
MCI, DCI, TCK, ID(14)
VCC = 5.5 V,
VI = VCC or GND
±
1
±
1
II
TDI, DTDI(14),
VCC = 5 5 V
VI = VCC
±
1
±
1
µ
A
,
(
),
TMS, TRST
VCC = 5.5 V
VI = GND
0.1
20
0.1
20
ICC
VCC = 5.5 V,
VI = VCC or GND, IO = 0
100
100
µ
A
ICC§
VCC = 5.5 V, One input at VI = 3.4 V,
Other inputs at VCC or GND
1
1
mA
Ci
VI = VCC or GND
6
pF
Co
DCO
VO = VCC or GND
15
pF
Co
All other outputs
VO = VCC or GND
10
pF
Typical values are at VCC = 5 V.
For I/O pins, the parameter IOZ includes the input-leakage current. For the DCO pin, the parameter IOZ includes the open-drain output-leakage
current.
§ This is the increase in supply current for each input being driven at TTL levels rather than VCC or GND.
SN54ACT8997, SN74ACT8997
SCAN-PATH LINKERS WITH 4-BIT IDENTIFICATION BUSES
SCAN-CONTROLLED IEEE STD 1149.1 (JTAG) TAP CONCATENATORS
SCAS157D APRIL 1990 REVISED DECEMBER 1996
20
POST OFFICE BOX 655303
·
DALLAS, TEXAS 75265
timing requirements over recommended ranges of supply voltage and operating free-air
temperature
SN54ACT8997
SN74ACT8997
UNIT
MIN
MAX
MIN
MAX
UNIT
f l k
Clock frequency
TCK
0
20
0
20
MHz
fclock
Clock frequency
DCI (count mode)
0
20
0
20
MHz
TCK high or low
12
12
tw
Pulse duration
DCI high or low (count mode)
7
7
ns
TRST low
7
7
TMS before TCK
8
8
TDI before TCK
9
9
t
Setup time
Any DTDI before TCK
7
7
ns
tsu
Setup time
MCI before TCK
3
3
ns
DCI before TCK
3
2
Any ID before TCK
2
2
TMS after TCK
2
2
TDI after TCK
2
2
th
Hold time
Any DTDI after TCK
2
2
ns
th
Hold time
MCI after TCK
4
4
ns
DCI after TCK
4
4
Any ID after TCK
4
4
td
Delay time
Power up to TCK
100*
100
ns
* On products compliant to MIL-PRF-38535, this parameter is not production tested.
SN54ACT8997, SN74ACT8997
SCAN-PATH LINKERS WITH 4-BIT IDENTIFICATION BUSES
SCAN-CONTROLLED IEEE STD 1149.1 (JTAG) TAP CONCATENATORS
SCAS157D APRIL 1990 REVISED DECEMBER 1996
21
POST OFFICE BOX 655303
·
DALLAS, TEXAS 75265
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature (see Figure 9)
PARAMETER
FROM
TO
SN54ACT8997
SN74ACT8997
UNIT
PARAMETER
(INPUT)
(OUTPUT)
MIN
MAX
MIN
MAX
UNIT
f
TCK
20
20
MHz
fmax
DCI (count mode)
20
20
MHz
tPLH
TCK
DTCK
2
14
3
12
ns
tPHL
TCK
DTCK
2
16
3
14
ns
tPLH
TCK
TDO
7
28
9
25
ns
tPHL
TCK
TDO
7
26
9
24
ns
tPLH
TCK
Any DTDO
7
27
9
25
ns
tPHL
TCK
Any DTDO
7
26
9
24
ns
tPLH
TCK
Any DTMS
9
31
11
29
ns
tPHL
TCK
Any DTMS
9
31
12
29
ns
tPLH
TCK
DCO (open drain)
9
33
12
31
tPLH
TCK
DCO (3 state)
9
32
12
30
ns
tPHL
TCK
DCO (open drain)
9
34
12
32
ns
tPHL
TCK
DCO (3 state)
9
31
12
29
tPLH
TMS
Any DTMS
4
21
6
19
ns
tPHL
TMS
Any DTMS
5
23
7
21
ns
tPLH
MCI
MCO
5
23
7
20
ns
tPHL
MCI
MCO
5
22
7
20
ns
tPLH
DCI
DCO (open drain)
9
30
11
27
tPLH
DCI
DCO (3 state)
6
29
10
26
ns
tPHL
DCI
DCO (open drain)
7
29
10
25
ns
tPHL
DCI
DCO (3 state)
6
26
9
23
tPHZ
TCK
TDO
3
17
5
15
ns
tPLZ
TCK
TDO
3
16
4
14
ns
tPHZ
TCK
Any DTDO
5
19
5
17
ns
tPLZ
TCK
Any DTDO
5
20
7
18
ns
tPHZ
TCK
Any DTMS
6
23
7
21
ns
tPLZ
TCK
Any DTMS
6
28
9
26
ns
tPHZ
TCK
DCO
6
23
9
21
ns
tPLZ
TCK
DCO
6
24
9
22
ns
tPZH
TCK
TDO
8
30
10
27
ns
tPZL
TCK
TDO
8
31
10
28
ns
tPZH
TCK
Any DTDO
9
31
11
28
ns
tPZL
TCK
Any DTDO
9
33
11
30
ns
tPZH
TCK
Any DTMS
8
31
11
29
ns
tPZL
TCK
Any DTMS
10
35
13
33
ns
tPZH
TCK
DCO
9
37
14
35
ns
tPZL
TCK
DCO
8
35
13
32
ns
SN54ACT8997, SN74ACT8997
SCAN-PATH LINKERS WITH 4-BIT IDENTIFICATION BUSES
SCAN-CONTROLLED IEEE STD 1149.1 (JTAG) TAP CONCATENATORS
SCAS157D APRIL 1990 REVISED DECEMBER 1996
22
POST OFFICE BOX 655303
·
DALLAS, TEXAS 75265
APPLICATION INFORMATION
TDI
TDO
TCK
TMS
SSP4
TDI
TDO
TCK
TMS
SSP3
TDI
TDO
TCK
TMS
SSP2
TDI
TDO
TCK
TMS
SSP1
4
4
4
VCC or GND
VCC or GND
VCC or GND
VCC or GND
DCI
MCO
ID1
ID2
ID3
ID4
TDI
DTDO
DCO
TRST
TMS
TCK
MCI
TDO
DTMS(14)
DTCK
DTDI(14)
Subsystem
To Remainder
of Primary
Scan Path
TDO
INT1
RSTOUT
TMSOUT
TCKOUT
INT2
TDI
PBC
'ACT8997
(14)
SN54ACT8997, SN74ACT8997
SCAN-PATH LINKERS WITH 4-BIT IDENTIFICATION BUSES
SCAN-CONTROLLED IEEE STD 1149.1 (JTAG) TAP CONCATENATORS
SCAS157D APRIL 1990 REVISED DECEMBER 1996
23
POST OFFICE BOX 655303
·
DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
50% VCC
1.5 V
1.5 V
1.5 V
3 V
3 V
0 V
0 V
th
tsu
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
Data Input
tPLH
tPHL
tPHL
tPLH
VOH
VOH
VOL
VOL
1.5 V
1.5 V
3 V
0 V
50% VCC
50% VCC
Input
Out-of-Phase
Output
In-Phase
Output
Timing Input
50% VCC
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
From Output
Under Test
CL = 50 pF
(see Note A)
LOAD CIRCUIT
S1
2
×
VCC
500
500
Output
Control
(low-level
enabling)
Output
Waveform 1
S1 at 2
×
VCC
(see Note B)
Output
Waveform 2
S1 at GND
(see Note B)
VOL
VOH
tPZL
tPZH
tPLZ
tPHZ
1.5 V
1.5 V
[
VCC
0 V
50% VCC
20% VCC
50% VCC
80% VCC
[
0 V
3 V
GND
Open
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open
2
×
VCC
GND
TEST
S1
3 V
0 V
1.5 V
1.5 V
tw
VOLTAGE WAVEFORMS
PULSE DURATION
Input
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. Input pulses are supplied by generators having the following characteristics: PRR
10 MHz, ZO = 50
, tr = 3 ns, tf = 3 ns.
For testing pulse duration: tr = 1 to 3 ns, tf = 1 to 3 ns. Pulse polarity may be either high-to-low-to-high or a low-to-high-to-low.
D. The outputs are measured one at a time with one transition per measurement.
Figure 9. Load Circuit and Voltage Waveforms
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package
Type
Package
Drawing
Pins Package
Qty
Eco Plan
(2)
Lead/Ball Finish
MSL Peak Temp
(3)
5962-9323901Q3A
ACTIVE
LCCC
FK
28
1
TBD
Call TI
Level-NC-NC-NC
5962-9323901QXA
ACTIVE
CDIP
JT
28
1
TBD
Call TI
Level-NC-NC-NC
SN74ACT8997DW
ACTIVE
SOIC
DW
28
20
Pb-Free
(RoHS)
CU NIPDAU
Level-1-260C-UNLIM
SN74ACT8997DWR
ACTIVE
SOIC
DW
28
1000
Pb-Free
(RoHS)
CU NIPDAU
Level-1-260C-UNLIM
SN74ACT8997NT
OBSOLETE
PDIP
NT
28
TBD
Call TI
Call TI
SNJ54ACT8997FK
ACTIVE
LCCC
FK
28
1
TBD
Call TI
Level-NC-NC-NC
SNJ54ACT8997JT
ACTIVE
CDIP
JT
28
1
TBD
Call TI
Level-NC-NC-NC
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco
Plan
-
The
planned
eco-friendly
classification:
Pb-Free
(RoHS)
or
Green
(RoHS
&
no
Sb/Br)
-
please
check
http://www.ti.com/productcontent
for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
PACKAGE OPTION ADDENDUM
www.ti.com
26-Sep-2005
Addendum-Page 1
MECHANICAL DATA
MCER004A JANUARY 1995 REVISED JANUARY 1997
POST OFFICE BOX 655303
·
DALLAS, TEXAS 75265
JT (R-GDIP-T**)
CERAMIC DUAL-IN-LINE
24 LEADS SHOWN
4040110/C 08/96
B
0.200 (5,08) MAX
0.320 (8,13)
0.290 (7,37)
0.130 (3,30) MIN
0.008 (0,20)
0.014 (0,36)
Seating Plane
13
12
0.030 (0,76)
0.070 (1,78)
0.015 (0,38) MIN
A
24
1
0.100 (2,54) MAX
0.023 (0,58)
0.015 (0,38)
0.100 (2,54)
0
°
15
°
1.440
(37,08)
1.460
0.285
(7,39)
0.291
(36,58)
(7,24)
28
PINS **
1.280
1.240
0.300
0.245
(7,62)
DIM
B MAX
A MAX
A MIN
B MIN
(6,22)
24
(32,51)
(31,50)
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. This package can be hermetically sealed with a ceramic lid using glass frit.
D. Index point is provided on cap for terminal identification.
E. Falls within MIL STD 1835 GDIP3-T24, GDIP4-T28, and JEDEC MO-058 AA, MO-058 AB
MECHANICAL DATA
MLCC006B OCTOBER 1996
POST OFFICE BOX 655303
·
DALLAS, TEXAS 75265
FK (S-CQCC-N**)
LEADLESS CERAMIC CHIP CARRIER
4040140 / D 10/96
28 TERMINAL SHOWN
B
0.358
(9,09)
MAX
(11,63)
0.560
(14,22)
0.560
0.458
0.858
(21,8)
1.063
(27,0)
(14,22)
A
NO. OF
MIN
MAX
0.358
0.660
0.761
0.458
0.342
(8,69)
MIN
(11,23)
(16,26)
0.640
0.739
0.442
(9,09)
(11,63)
(16,76)
0.962
1.165
(23,83)
0.938
(28,99)
1.141
(24,43)
(29,59)
(19,32)
(18,78)
**
20
28
52
44
68
84
0.020 (0,51)
TERMINALS
0.080 (2,03)
0.064 (1,63)
(7,80)
0.307
(10,31)
0.406
(12,58)
0.495
(12,58)
0.495
(21,6)
0.850
(26,6)
1.047
0.045 (1,14)
0.045 (1,14)
0.035 (0,89)
0.035 (0,89)
0.010 (0,25)
12
13
14
15
16
18
17
11
10
8
9
7
5
4
3
2
0.020 (0,51)
0.010 (0,25)
6
1
28
26
27
19
21
B SQ
A SQ
22
23
24
25
20
0.055 (1,40)
0.045 (1,14)
0.028 (0,71)
0.022 (0,54)
0.050 (1,27)
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. This package can be hermetically sealed with a metal lid.
D. The terminals are gold plated.
E. Falls within JEDEC MS-004
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