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FEATURES

APPLICATIONS

DESCRIPTION

DAC5686

SLWS147B APRIL 2003 REVISED AUGUST 2004

16-BIT, 500-MSPS, 2

16

INTERPOLATING DUAL-CHANNEL DIGITAL-TO-ANALOG

CONVERTER

On-Chip 1.2-V Reference

500 MSPS Maximum Update Rate DAC

1.8-V Digital and 3.3-V Analog Supplies

WCDMA ACPR

1.8-V/3.3-V CMOS Compatible Interface

 1 Carrier: 76 dB Centered at 30.72-MHz IF,

Power Dissipation: 950 mW at Full Maximum

245.76 MSPS

Operating Conditions

 1 Carrier: 73 dB Centered at 61.44-MHz IF,

Package: 100-Pin HTQFP

245.76 MSPS

 2 Carrier: 72 dB Centered at 30.72-MHz IF,

245.76 MSPS

Cellular Base Transceiver Station Transmit
Channel

 4 Carrier: 64 dB Centered at 92.16-MHz IF,

 CDMA: W-CDMA, CDMA2000, IS-95

491.52 MSPS

 TDMA: GSM, IS-136, EDGE/UWC-136

Selectable 2

, 4

, 8

, and 16

Interpolation

Baseband I and Q Transmit

 Linear Phase

Input Interface: Quadrature Modulation for

 0.05-dB Pass-Band Ripple

Interfacing With Baseband Complex Mixing

 80-dB Stop-Band Attenuation

ASICs

 Stop-Band Transition 0.40.6 f

DATA

Single-Sideband Up-Conversion

32-Bit Programmable NCO

Diversity Transmit

On-Chip 2

16

PLL Clock Multiplier With

Cable Modem Termination System

Bypass Mode

Differential Scalable Current Outputs: 2 mA to
20 mA

The DAC5686 is a dual-channel 16-bit high-speed digital-to-analog converter (DAC) with integrated 2

, 4

, 8

and 16

interpolation filters, a numerically controlled oscillator (NCO), onboard clock multiplier, and on-chip

voltage reference. The DAC5686 has been specifically designed to allow for low input data rates between the
DAC and ASIC, or FPGA, and high output transmit intermediate frequencies (IF). Target applications include
high-speed digital data transmission in wired and wireless communication systems and high-frequency
direct-digital synthesis DDS.

The DAC5686 provides three modes of operation: dual-channel, single-sideband, and quadrature modulation. In
dual-channel mode, interpolation filtering increases the DAC update rate, which reduces sinx/x rolloff and
enables the use of relaxed analog post-filtering.

Single-sideband mode provides an alternative interface to the analog quadrature modulators. Channel carrier
selection is performed at baseband by mixing in the ASIC/FPGA. Baseband I and Q from the ASIC/FPGA are
input to the DAC5686, which in turn performs a complex mix resulting in Hilbert transform pairs at the outputs of
the DAC5686's two DACs. An external RF quadrature modulator then performs the final single-sideband
up-conversion. The DAC5686's complex mixing frequencies are flexibly chosen with the 32-bit programmable
NCO.

Unmatched gains and offsets at the RF quadrature modulator result in unwanted sideband and local oscillator
feedthrough. Each DAC in the DAC5686 has an 11-bit offset adjustment and 12-bit gain adjustment, which
compensate for quadrature modulator input imbalances, thus reducing RF filtering requirements.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PowerPAD is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.

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DAC5686

SLWS147B APRIL 2003 REVISED AUGUST 2004

In quadrature modulation mode, on-chip mixing provides baseband-to-IF up-conversion. Mixing frequencies are
flexibly chosen with a 32-bit programmable NCO. Channel carrier selection is performed at baseband by complex
mixing in the ASIC/FPGA. Baseband I and Q from the ASIC/FPGA are input to the DAC5686, which interpolates
the low data-rate signal to higher data rates. The single DAC output from the DAC5686 is the final IF
single-sideband spectrum presented to RF.

The 2

, 4

, 8

, and 16

interpolation filters are implemented as a cascade of half-band 2

interpolation filters.

Unused filters for interpolation rates of less than 16

are shut off to reduce power consumption. The DAC5686

provides a full bypass mode, which enables the user to bypass all the interpolation and mixing.

The DAC5686 PLL clock multiplier controls all internal clocks for the digital filters and the DAC cores. The
differential clock input and internal clock circuitry provides for optimum jitter performance. Sine wave clock input
signal is supported. The PLL can be bypassed by an external clock running at the DAC core update rate. The
clock divider of the PLL ensures that the digital filters operate at the correct clock frequencies.

The DAC5686 operates with an analog supply voltage of 3.3 V and a digital supply voltage of 1.8 V. Digital I/Os
are 1.8-V and 3.3-V CMOS compatible. Power dissipation is 950 mW at maximum operating conditions. The
DAC5686 provides a nominal full-scale differential current output of 20 mA, supporting both single-ended and
differential applications. The output current can be directly fed to the load with no additional external output buffer
required. The device has been specifically designed for a differential transformer-coupled output with a 50-

doubly terminated load. For a 20-mA full-scale output current, both a 4:1 impedance ratio (resulting in an output
power of 4 dBm) and 1:1 impedance ratio transformer (2-dBm output power) are supported.

The DAC5686 operational modes are configured by programming registers through a serial interface. The serial
interface can be configured to either a 3- or 4-pin interface allowing it to communicate with many
industry-standard microprocessors and microcontrollers. Data (I and Q) can be input to the DAC5686 as
separate parallel streams on two data buses, or as a single interleaved data stream on one data bus.

An accurate on-chip 1.2-V temperature-compensated band-gap reference and control amplifier allows the user to
adjust the full-scale output current from 20 mA down to 2 mA. This provides 20-dB gain range control
capabilities. Alternatively, an external reference voltage can be applied for maximum flexibility. The device
features a SLEEP mode, which reduces the standby power to approximately 10 mW, thereby minimizing the
system power consumption.

The DAC5686 is available in a 100-pin HTQFP package. The device is characterized for operation over the
industrial temperature range of 40

C to 85

ORDERING INFORMATION

PACKAGE DEVICES

100 HTQFP

(1)

(PZP) PowerPADTM Plastic Quad Flatpack

C to 85

DAC5686IPZP

(1)

Thermal pad size: 6 mm

6 mm

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FUNCTIONAL BLOCK DIAGRAM

CLK1

CLK1C

LPF

PLLLOCK

CLKVDD

CLKGND

DVDD

DGND

PLLVDD

PLLGND

SLEEP

FIR1

FIR2

sin

IOVDD

IOGND

AVDD

AGND

PHSTR

NCO

cos

RESETB

100-Pin HTQFP

EXTIO

EXTLO

1.2 V

Reference

BIASJ

IOUTA1

IOUTA2

16-Bit

FIR5

IOUTB1

IOUTB2

FIR3

sin(x)

TxENABLE

DA[15:0]

DB[15:0]

DEMUX

FIR4

CLK2

CLK2C

SIF

SCLK

SDENB

SDO

SDIO

DAC

16-Bit

DAC

2 16

data

Internal Clock Generation

 16

PLL Clock Multiplier

sin(x)

data

A Gain

B Gain

Offset

DAC5686

SLWS147B APRIL 2003 REVISED AUGUST 2004

Block Diagram of the DAC5686

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PIN ASSIGNMENTS FOR THE DAC5686

100

DAC5686

Top View 100 HTQFP

DVDD

DGND

QFLAG

TESTMODE

SLEEP

RESETB

PHSTR

DGND

DB15 (MSB)

DB14

DB13

DVDD

DGND

DB12

DB1

DB10

DB9

DB8

DVDD

DGND

IOVDD

IOGND

DB7

DB6

DB5

DVDD

DGND

SDENB

SCLK

SDIO

SDO

TxENABLE

DA15 (MSB)

DA14

DA13

DVDD

DGND

DA12

DA1

DA10

DA9

DA8

DVDD

DGND

IOVDD

IOGND

DA7

DA6

DA5

AVDD

AGND

IOUTA1

IOUTA2

AGND

AVDD

AGND

AVDD

EXTLO

AGND

BIASJ

AGND

EXTIO

AVDD

AGND

AVDD

AGND

IOUTB2

IOUTB1

AGND

AVDD

AGND

DA4

DA3

DA2

DA1

DA0 (LSB)

DVDD

DGND

CLKGND

CLK1

CLK1C

CLKVDD

CLK2

CLK2C

CLKGND

PLLGND

LPF

PLLVDD

DVDD

DGND

PLLLOCK

DB0 (LSB)

DB1

DB2

DB3

DB4

DVDD

DEVICE INFORMATION

DAC5686

SLWS147B APRIL 2003 REVISED AUGUST 2004

Terminal Functions

TERMINAL

I/O

DESCRIPTION

NAME

NO.

AGND

1, 4, 7, 9,

Analog ground return

12, 17, 19,
22, 25

AVDD

2, 3, 8, 10,

Analog supply voltage

14, 16, 18,
23, 24

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DAC5686

SLWS147B APRIL 2003 REVISED AUGUST 2004

DEVICE INFORMATION (continued)

Terminal Functions (continued)

TERMINAL

I/O

DESCRIPTION

NAME

NO.

BIASJ

I/O

Full-scale output current bias

CLK1

External clock input; data clock input

CLK1C

Complementary external clock input; data clock input

CLK2

External clock input; sample clock for the DAC (optional if PLL disabled)

CLK2C

Complementary external clock input; sample clock for the DAC (optional if PLL disabled)

CLKGND

58, 64

Ground return for internal clock buffer

CLKVDD

Internal clock buffer supply voltage

DA[15:0]

3436,

A-channel data bits 0 through 15

3943,

DA15 is most significant data bit (MSB).

4855

DA0 is least significant data bit (LSB).

DB[0:15]

7178,

B-channel data bits 0 through 15

8387,

DB15 is most significant data bit (MSB).

9092

DB0 is least significant data bit (LSB).
Note: The order of the B data bus can be reversed by register rev_bbus.

DGND

27, 38, 45,

Digital ground return

57, 69, 81,
88, 93, 99

DVDD

26, 32, 37,

Digital supply voltage

44, 56, 68,
82, 89, 100

EXTIO

Used as external reference input when internal reference is disabled (i.e., EXTLO connected to AVDD).
Used as internal reference output when EXTLO = AGND, requires a 0.1-

F decoupling capacitor to

AGND when used as reference output

EXTLO

Internal reference ground. Connect to AVDD to disable the internal reference

IOUTA1

A-channel DAC current output. Full scale when all input bits are set to 1

IOUTA2

A-channel DAC complementary current output. Full scale when all input bits are set to 0

IOUTB1

B-channel DAC current output. Full scale when all input bits are set to 1

IOUTB2

B-channel DAC complementary current output. Full scale when all input bits are set to 0

IOGND

47, 79

Digital I/O ground return

IOVDD

46, 80

Digital I/O supply voltage

LPF

I/O

PLL loop filter connection. Can be left open or connected to GND if PLL is not used (PLLVDD = 0 V).

PHSTR

The PHSTR pin has two functions. When the sync_phstr register is 0, a high on the PHSTR pin resets
the NCO phase accumulator. When the sync_phstr register is 1, a PHSTR pin low-to-high transition
sets the divided clock phase in external clock mode, and a high on the PHSTR pin resets the NCO
phase accumulator.

PLLGND

Ground return for internal PLL

PLLVDD

PLL supply voltage. When PLLVDD is 0 V, the PLL is disabled.

PLLLOCK

PLL lock status bit. In PLL clock mode, PLLLOCK is high when PLL is locked to the input clock. In
external clock mode, PLLLOCK outputs the input rate clock.

QFLAG

Used in the interleaved data input mode: When the qflag register bit is 1, the QFLAG pin is used as an
output to identify the interleaved data sequence. QFLAG high identifies the data as channel B. Pin can
be left open when not used.

RESETB

Resets the chip when low

SCLK

Serial interface clock

SDENB

Active-low serial data enable, always an input to the DAC5686

SDIO

I/O

Bidirectional serial-port data in the three-pin serial interface mode. Input-only serial data in the four-pin
serial interface mode.

SDO

High-impedance state (the pin is not used) in the three-pin serial interface mode. Serial-port output data
in the four-pin serial interface mode.

SLEEP

Asynchronous hardware power-down input. Active high. Internal pulldown

TESTMODE

TESTMODE is DGND for the user.

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ABSOLUTE MAXIMUM RATINGS

ELECTRICAL CHARACTERISTICS (DC SPECIFICATIONS)

(1)

DAC5686

SLWS147B APRIL 2003 REVISED AUGUST 2004

DEVICE INFORMATION (continued)

Terminal Functions (continued)

TERMINAL

I/O

DESCRIPTION

NAME

NO.

TxENABLE

TxENABLE is used in interleaved mode. The rising edge of TxENABLE synchronizes the data of
channels A and B. The first data after the rising edge of TxENABLE is treated as A data, while the next
data is treated as B data and so on. In any mode, TxENABLE being low sets DAC outputs to midscale.
Internal pulldown

over operating free-air temperature range (unless otherwise noted)

(1)

UNIT

AVDD

(2)

0.5 V to 4 V

DVDD

(3)

0.5 V to 2.3 V

Supply voltage range

CLKVDD

(2)

0.5 V to 4 V

IOVDD

(2)

0.5 V to 4 V

PLLVDD

(2)

0.5 V to 4 V

Voltage between AGND, DGND, CLKGND, PLLGND, and IOGND

0.5 V to 0.5 V

AVDD to DVDD

0.5 V to 2.6 V

DA[15:0]

(3)

0.5 V to IOVDD + 0.5 V

DB[15:0]

(3)

0.5 V to IOVDD + 0.5 V

SLEEP

(3)

0.5 V to IOVDD + 0.5 V

CLK1, CLK2, CLK1C, CLK2C

(3)

0.5 V to CLKVDD + 0.5 V

Supply voltage range

RESETB

(3)

0.5 V to IOVDD + 0.5 V

LPF

(3)

0.5 V to PLLVDD + 0.5 V

IOUT1, IOUT2

(2)

1 V to AVDD + 0.5 V

EXTIO, BIASJ

(2)

0.5 V to AVDD + 0.5 V

EXTLO

(2)

0.5 V to IOVDD + 0.5 V

Peak input current (any input)

20 mA

Operating free-air temperature range, T

: DAC5686I

C to 85

Storage temperature range

C to 150

Lead temperature 1,6 mm (1/16 inch) from the case for 10 seconds

260

(1)

Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2)

Measured with respect to AGND

(3)

Measured with respect to DGND

over operating free-air temperature range, AVDD = 3.3 V, CLKVDD = 3.3 V, PLLVDD = 3.3 V, IOVDD = 3.3 V,
DVDD = 1.8 V, IOUT

= 20 mA (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Resolution

DC Accuracy

(2)

INL

Integral nonlinearity

1 LSB = IOUT

/216, T

MIN

to T

MAX

LSB

1.84e4

IOUT

DNL

Differential nonlinearity

LSB

1.37e4

IOUT

(1)

Specifications subject to change without notice.

(2)

Measured differential across IOUTA1 and IOUTA2 or IOUTB1 and IOUTB2 with 25

each to AVDD

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DAC5686

SLWS147B APRIL 2003 REVISED AUGUST 2004

ELECTRICAL CHARACTERISTICS (DC SPECIFICATIONS) (continued)

over operating free-air temperature range, AVDD = 3.3 V, CLKVDD = 3.3 V, PLLVDD = 3.3 V, IOVDD = 3.3 V,
DVDD = 1.8 V, IOUT

= 20 mA (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Analog Output

Coarse gain linearity (INL)

LSB = 1/10

of full scale

0.016

LSB

Fine gain linearity (INL)

LSB

Offset error

Mid-code offset

0.003

%FSR

Without internal reference

0.7

Gain error

%FSR

With internal reference

0.7

Gain mismatch

With internal reference, dual DAC,

%FSR

SSB mode

Full-scale output current

(3)

Output compliance range

(4)

IOUT

= 20 mA

AVDD 0.5

AVDD + 0.5

Output resistance

300

Output capacitance

Reference Output

Reference voltage

1.14

1.2

1.26

Reference output current

(5)

100

Reference Input

EXTIO

Input voltage range

0.1

1.25

Input resistance

Small-signal bandwidth

2.5

kHz

Input capacitance

100

Temperature Coefficients

ppm of

Offset drift

FSR/

Without internal reference

ppm of

Gain drift

FSR/

With internal reference

Reference voltage drift

ppm/

Power Supply

AVDD

Analog supply voltage

3.3

3.6

DVDD

Digital supply voltage

1.65

1.8

1.95

CLKVDD

Clock supply voltage

3.3

3.6

IOVDD

I/O supply voltage

1.65

3.6

PLLVDD

PLL supply voltage

3.3

3.6

Single (quad) DAC mode;
including output current through

load resistor, mode 7

AVDD

Analog supply current

Dual DAC mode; including output
current through load resistor,

mode 11

DVDD

Digital supply current

242

CLKVDD

Clock supply current

DATA

= 125 MSPS, SSB mode,

update

= 500 MSPS, 40-MHz IF

PLLVDD

PLL supply current

IOVDD

IO supply current

< 3

(3)

Nominal full-scale current, IOUT

, equals 16

the IBIAS current.

(4)

The upper limit of the output compliance is determined by the CMOS process. Exceeding this limit may result in transistor breakdown,
resulting in reduced reliability of the DAC5686 device. The lower limit of the output compliance is determined by the load resistors and
full-scale output current. Exceeding the upper limit adversely affects distortion performance and integral nonlinearity.

(5)

Use an external buffer amplifier with high-impedance input to drive any external load.

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ELECTRICAL CHARACTERISTICS (AC SPECIFICATIONS)

(1)

DAC5686

SLWS147B APRIL 2003 REVISED AUGUST 2004

ELECTRICAL CHARACTERISTICS (DC SPECIFICATIONS) (continued)

over operating free-air temperature range, AVDD = 3.3 V, CLKVDD = 3.3 V, PLLVDD = 3.3 V, IOVDD = 3.3 V,
DVDD = 1.8 V, IOUT

= 20 mA (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

AVDD

Sleep mode, AVDD supply current

DVDD

Sleep mode, DVDD supply current

CLKVDD

Sleep mode, CLKVDD supply

current

Sleep mode

PLLVDD

Sleep mode, PLLVDD supply

0.5

current

IOVDD

Sleep mode, IOVDD supply current

0.25

Mode 1

(6)

AVDD = 3.3 V,

215

DVDD = 1.8 V

Mode 2

(7)

AVDD = 3.3 V,

495

DVDD = 1.8 V

Mode 5

(8)

AVDD = 3.3 V,

445

DVDD = 1.8 V

Power dissipation

Mode 7

(9)

AVDD = 3.3 V,

754

DVDD = 1.8 V

Mode 9

(10)

AVDD = 3.3 V,

547

DVDD = 1.8 V

Mode 11

(11)

AVDD = 3.3 V,

855

950

DVDD = 1.8 V

APSRR

Power supply rejection ratio

0.2

%FSR/V

DPSRR

Power supply rejection ratio

0.2

%FSR/V

(6)

Mode 1: Dual DAC mode, fully bypassed, F

DAC

= 160 MSPS, f

OUT

= 20 MHz

(7)

Mode 2: Dual DAC mode, 2

interpolation, F

DAC

= 320 MSPS, f

OUT

= 20 MHz

(8)

Mode 5: Quadrature modulation mode, 4

interpolation, fs/4 mixing, F

DAC

= 320 MSPS, f

OUT

= 100 MHz

(9)

Mode 7: Quadrature modulation mode, 4

interpolation, NCO running at 320 MHz, F

DAC

= 320 MSPS, f

OUT

= 100 MHz

(10) Mode 9: SSB modulation mode, 4

interpolation, fs/4 mixing, F

DAC

= 320 MSPS, f

OUT

= 100 MHz

(11) Mode 11: SSB modulation mode, 4

interpolation, NCO running at 320 MHz, f

OUT

= 100 MHz, maximum operating condition

over operating free-air temperature range, AVDD = 3.3 V, CLKVDD = 3.3 V, PLLVDD = 0 V, IOVDD = 3.3 V, DVDD = 1.8 V,
IOUT

= 20 mA, external clock mode, differential transformer-coupled output, 50-

doubly terminated load (unless otherwise

noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Analog Output

CLK

Maximum output update rate

500

MSPS

s(DAC)

Output settling time to 0.1%

Mid-scale transition

Output propagation delay

2.5

r(IOUT)

(2)

Output rise time 10% to 90%

2.5

f(IOUT)

(2)

Output fall time 90% to 10%

2.5

AC Performance--1:1 Impedance-Ratio Transformer

First Nyquist zone < f

DATA

/2, 4

interpolation, dual DAC mode,

DATA

= 52 MSPS, f

OUT

= 14 MHz, T

= 25

First Nyquist zone < f

DATA

/2, 4

interpolation, dual DAC mode,

DATA

= 160 MSPS, f

OUT

= 20 MHz, full bypass,T

= T

MIN

MAX

for MIN, 25

C for TYP, IOVDD = 1.8 V for TYP

SFDR

Spurious free dynamic range

dBc

interpolation, dual DAC mode, f

DATA

= 160 MSPS, f

OUT

41 MHz, T

= 25

C, IOVDD = 1.8 V

interpolation, dual DAC mode, f

DATA

= 160 MSPS, f

OUT

61 MHz, T

= 25

C, IOVDD = 1.8 V

(1)

Specifications subject to change without notice

(2)

Measured single-ended into 50-

load

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ELECTRICAL CHARACTERISTICS (DIGITAL SPECIFICATIONS)

(1)

DAC5686

SLWS147B APRIL 2003 REVISED AUGUST 2004

ELECTRICAL CHARACTERISTICS (AC SPECIFICATIONS) (continued)

over operating free-air temperature range, AVDD = 3.3 V, CLKVDD = 3.3 V, PLLVDD = 0 V, IOVDD = 3.3 V, DVDD = 1.8 V,
IOUT

= 20 mA, external clock mode, differential transformer-coupled output, 50-

doubly terminated load (unless otherwise

noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

First Nyquist zone < f

DATA

/2, f

DATA

= 100 MSPS,

OUT

= 5 MHz, IOVDD = 1.8 V, f

DAC

= 400 MSPS

SNR

Signal-to-noise ratio

First Nyquist zone < f

DATA

/2, f

DATA

= 78 MSPS,

OUT

= 15.6 MHz, 15.8 MHz, 16.2 MHz, 16.4 MHz,

IOVDD = 1.8 V, f

DAC

= 314 MSPS

Single carrier W-CDMA with 3.84-MHz BW, 5-MHz spacing,
centered at IF, TESTMODEL 1, 10 ms, f

DATA

= 122.88 MSPS,

baseband, dual DAC, 2

interpolation,

OUT

= 245 MSPS

Single carrier W-CDMA with 3.84-MHz BW, 5-MHz spacing,
centered at IF, TESTMODEL 1, 10 ms, f

DATA

= 76.8 MSPS, IF

= 19.2 MHz, dual DAC, 2

interpolation,

OUT

= 153.6 MSPS

Single carrier W-CDMA with 3.84-MHz BW, 5-MHz spacing,
centered at IF, TESTMODEL 1, 10 ms, f

DATA

= 122.88 MSPS,

IF = 30.72 MHz, dual DAC, 2

interpolation, f

DAC

= 245 MSPS

ACLR

Adjacent channel power ratio

Single carrier W-CDMA with 3.84-MHz BW, 5-MHz spacing,
centered at IF, TESTMODEL 1, 10 ms, f

DATA

= 61.44 MSPS,

IF = 61.44 MHz, quad mode, fs/4, 4

interpolation, f

DAC

= 245 MSPS

Two-carrier W-CDMA with 3.84-MHz BW, 5-MHz spacing,
centered at IF, TESTMODEL 1, 10 ms, f

DATA

= 122.88 MSPS,

IF = 30.72 MHz, dual DAC, 2

interpolation, f

DAC

= 245 MSPS

Four-carrier W-CDMA with 3.84-MHz BW, 5-MHz spacing,
centered at IF, TESTMODEL 1, 10 ms, f

DATA

= 121.88 MSPS,

complex IF - 30.72 MHz, quad mode, fs/4, 4

interpolation, IF

= 92.16 MHz

DATA

= 160 MSPS, f

OUT

= 60.1 and 61.1 MHz, 2

interp-

olation,

320 MSPS, IOVDD = 1.8 V, each tone at 6 dBFS

Third-order two-tone

IMD3

dBc

intermodulation

DATA

= 100 MSPS, f

OUT

= 15.1 and 16.1 MHz, 2

interp-

olation,

200 MSPS, IOVDD = 1.8 V, each tone at 6 dBFS

DATA

= 100 MSPS, f

OUT

= 15.6 MHz, 15.8 MHz, 16.2 MHz,

IMD

Four-tone intermodulation

16.4 MHz, 4

interpolation, 400 MSPS, IOVDD = 1.8 V, each

dBc

tone at 12 dBFS

over operating free-air temperature range, AVDD = 3.3 V, CLKVDD = 3.3 V, PLLVDD = 3.3 V, IOVDD = 3.3 V, DVDD = 1.8
V, IOUT

= 20 mA (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

CMOS Interface

High-level input voltage

Low-level input voltage

0.8

High-level input current

µA

Low-level input current

µA

Input capacitance

= 100 µA

IOVDD 0.2

High-level output voltage,

PLLLOCK, SDO, SDIO (I/O)

= 8 mA

0.8

IOVDD

(1)

Specifications subject to change without notice.

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DAC5686

SLWS147B APRIL 2003 REVISED AUGUST 2004

ELECTRICAL CHARACTERISTICS (DIGITAL SPECIFICATIONS) (continued)

over operating free-air temperature range, AVDD = 3.3 V, CLKVDD = 3.3 V, PLLVDD = 3.3 V, IOVDD = 3.3 V, DVDD = 1.8
V, IOUT

= 20 mA (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

= 100 µA

0.2

Low-level output voltage,

PLLLOCK, SDO, SDIO (I/O)

= 8 mA

0.22

IOVDD

PLL

Input data rate supported

160

MSPS

At 600-kHz offset, measured at
DAC output, 25-MHz 0-dBFS tone,

128

DATA

= 125 MSPS, 4

interpolation

Phase noise

dBc/Hz

At 6-MHz offset, measured at DAC
output, 25-MHz 0-dBFS tone, f

DATA

151

= 125 MSPS, 4

interpolation

VCO minimum frequency

PLL_rng = 00 (nominal)

120

MHz

VCO maximum frequency

PLL_rng = 00 (nominal)

500

MHz

NCO

NCO clock (DAC update rate)

320

MHz

Serial Port Timing

Setup time, SDENB to rising edge

su(SDENB)

of SCLK

Setup time, SDIO valid to rising

su(SDIO)

edge of SCLK

Hold time, SDIO valid to rising

h(SDIO)

edge of SCLK

SCLK

Period of SCLK

100

SCLKH

High time of SCLK

SCLKL

Low time of SCLK

Data output delay after falling

d(Data)

edge of SCLK

Parallel Data Input Timing (PLL Mode, CLK1 Input)

Setup time, data valid to rising

su(DATA)

0.3

0.4

edge of CLK1

Hold time, data valid after rising

h(DATA)

1.2

0.6

edge of CLK1

Parallel Data Input Timing (Dual Clock Mode, CLK1 and CLK2 Input)

Setup time, data valid to rising

su(DATA)

0.4

edge of CLK1

Hold time, data valid after rising

h(DATA)

0.6

edge of CLK1

Timing Parallel Data Input (External Clock Mode, CLK2 Input)

High-impedance load on PLLLOCK.

Setup time, DATA valid to rising

su(DATA)

Note that t

increases with a

4.6

edge of PLLLOCK

lower-impedance load.

High-impedance load on PLLLOCK.

Hold time, DATA valid after rising

Note that t

decreases (becomes

h(DATA)

0.8

2.4

edge of PLLLOCK

more negative) with a
lower-impedance load.

High-impedance load on PLLLOCK.

Delay from CLK2 rising edge to

Note that PLLLOCK delay in-

d(PLLLock)

2.5

4.2

6.5

PLLLOCK rising edge

creases with a lower-impedance
load.

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f Frequency MHz

-90

-80

-70

-60

-50

-40

-30

-20

-10

100

150

200

250

data

= 125 MSPS

= 20 MHz

Dual DAC Mode
4

Interpolation

Power dBm

 Output Frequency MHz

data

= 125 MSPS

Dual DAC Mode
4

Interpolation

In-band = 062.5 MHz

SFDR In-Band Spurious-Free Dynamic Range dBc

0 dBf

12 dBf

6 dBf

 Output Frequency MHz

data

= 125 MSPS

Dual DAC Mode
4

Interpolation

Out-of-Band = 62.5 MHz250 MHz

SFDR Out-of-Band Spurious-Free Dynamic Range dBc

0 dBf

12 dBf

6 dBf

f Frequency MHz

-90

-80

-70

-60

-50

-40

-30

-20

-10

100

125

150

data

= 75 MSPS

= None

NCO On
f

OUT

= 100 MHz

Quad Mode
4

Interpolation

Power dBm

DAC5686

SLWS147B APRIL 2003 REVISED AUGUST 2004

TYPICAL CHARACTERISTICS (continued)

IN-BAND SPURIOUS-FREE DYNAMIC RANGE

SINGLE-TONE SPECTRUM

OUTPUT FREQUENCY

Figure 3.

Figure 4.

OUT-OF-BAND SPURIOUS-FREE DYNAMIC RANGE

OUTPUT FREQUENCY

SINGLE-TONE SPECTRUM

Figure 5.

Figure 6.

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 Output Frequency MHz

wo-T

one IMD3 dBc

0.5 MHz

2 MHz

data

= 150 MSPS

Dual DAC Mode
2

Interpolation

f Frequency MHz

-100

-90

-80

-70

-60

-50

-40

-30

-20

-10

Power dBm

data

= 150 MSPS

1 = 19.5 MHz

2 = 20.5 MHz

Dual DAC Mode
2

Interpolation

 Output Frequency MHz

110

130

150

data

= 80 MSPS

NCO On
Quad Mode
4

Interpolation

wo-T

one IMD3 dBc

0.5 MHz

2 MHz

f Frequency MHz

-100

-90

-80

-70

-60

-50

-40

-30

-20

-10

data

= 80 MSPS

1 = 0.5 MHz

2 = 0.5 MHz

NCO = 70 MHz
Quad Mode
4

Interpolation

Power dBm

DAC5686

SLWS147B APRIL 2003 REVISED AUGUST 2004

TYPICAL CHARACTERISTICS (continued)

TWO-TONE IMD3

OUTPUT FREQUENCY

TWO-TONE IMD PERFORMANCE

Figure 7.

Figure 8.

TWO-TONE IMD3

OUTPUT FREQUENCY

TWO-TONE IMD PERFORMANCE

Figure 9.

Figure 10.

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f Frequency MHz

-100

-90

-80

-70

-60

-50

-40

-30

-20

-10

140

145

150

155

160

data

= 80 MSPS

1 = 0.5 MHz

2 = 0.5 MHz

NCO = 150 MHz
Quad Mode
4

Interpolation

Power dBm

f Frequency MHz

-130

-120

-110

-100

-90

-80

-70

-60

-50

-40

-30

-20

Power dBm

data

= 122.88 MSPS

= 30.72 MHz

ACLR = 78.6 dB
4

Interpolation

Dual DAC Mode

f Frequency MHz

-130

-120

-110

-100

-90

-80

-70

-60

-50

-40

-30

-20

Power dBm

data

= 122.88 MSPS

= 30.72 MHz

ACLR = 71.69 dB
4

Interpolation

Dual DAC Mode

f Frequency MHz

-120

-110

-100

-90

-80

-70

-60

-50

-40

-30

-20

Power dBm

data

= 122.88 MSPS

= Baseband Complex

ACLR = 69.08 dB
2

Interpolation

Quad Mode

DAC5686

SLWS147B APRIL 2003 REVISED AUGUST 2004

TYPICAL CHARACTERISTICS (continued)

TWO-TONE IMD PERFORMANCE

WCDMA TEST MODEL 1: SINGLE CARRIER

Figure 11.

Figure 12.

WCDMA TEST MODEL 1: DUAL CARRIER

Figure 13.

Figure 14.

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f Frequency MHz

-110

-100

-90

-80

-70

-60

-50

-40

-30

-20

-10

102

107

112

Power dBm

data

= 122.88 MSPS

= 30.72 MHz Complex

ACLR = 63.29 dB
4

Interpolation

Quad Mode

f Frequency MHz

-110

-90

-70

-50

-30

-10

138

143

148

153

158

163

168

Power dBm

data

= 122.88 MSPS

= 30.72 MHz Complex

ACLR = 58.58 dB
4

Interpolation

Quad Mode

VCO

 VCO Frequency MHz

100

200

300

400

500

600

100

200

300

400

500

600

700

 VCO Gain MHz/V

Boost for 45%

Boost for 15%

Boost for 30%

Boost for 0%

DAC5686

SLWS147B APRIL 2003 REVISED AUGUST 2004

TYPICAL CHARACTERISTICS (continued)

WCDMA TEST MODEL 1: FOUR CARRIER

WCDMA TEST MODEL 1: DUAL CARRIER

Figure 15.

Figure 16.

VCO GAIN

VCO FREQUENCY

Figure 17.

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DETAILED DESCRIPTION

Dual-Channel Mode

FIR1

FIR2

FIR3

FIR4

IOUTB1

IOUTB2

IOUTA1

IOUTA2

16-Bit

DAC

FIR5

sin(x)

DA[15:0]

DB[15:0]

data

2 16

data

16F

data

A Gain

Offset

FIR1

FIR2

FIR3

FIR4

16-Bit

DAC

FIR5

sin(x)

data

16F

data

Offset

B Gain

DEMUX

Single-Sideband Mode

DAC5686

SLWS147B APRIL 2003 REVISED AUGUST 2004

In dual-channel mode, interpolation filtering increases the DAC update rate, thereby reducing sinx/x rolloff and
enabling relaxed analog post-filtering, and is useful for baseband I and Q modulation or two-channel low-IF
signals. The dual-channel mode is set by mode[1:0] = 00 in the config_lsb register. Figure 18 shows the data
path architecture in dual-channel mode. The A- and B-data paths, which are independent, consist of four
cascaded half-band interpolation filters, followed by an optional inverse sinc filter. Interpolation filtering is
selected as 2

, 4

, 8

, or 16

by sel[1:0] in the config_lsb register. Magnitude spectral responses of each filter

are presented following in the section on digital filtering. Full bypass of all the interpolation filters is selected by
fbypass in the config_lsb register. The inverse sinc filter is intended for use in single-sideband and quadrature
modulation modes and is of limited benefit in dual-channel mode.

Figure 18. Data Path in Dual-Channel Mode

Single-sideband (SSB) mode provides optimum interfacing to analog quadrature modulators. The SSB mode is
selected by mode[1:0] = 01 in the config_lsb register. Figure 19 shows the data path architecture in
single-sideband mode. Complex baseband I and Q are input to the DAC5686, which in turn performs a complex
mix, resulting in Hilbert transform pairs at the outputs of the DAC5686's two DACs. NCO mixing frequencies are
programmed through 32-bit freq (4 registers); 16-bit phase adjustments are programmed through phase (2
registers). The NCO operates at the DAC update rate; thus, increased amounts of interpolation allow for higher
IFs. More details for the NCO are provided as follows. For mixing to F

dac

/4, DAC5686 provides a specific

architecture that exploits the {

...

1 0 1 0

...

} resultant streams from sin and cos; the NCO is shut off in this mode

to conserve power. F

dac

/4 mix mode is implemented by deasserting nco in register config_msb while in

single-sideband or quadrature modulation mode.

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IOUTA1

IOUTA2

16-Bit

DAC

DA[15:0]

DB[15:0]

2 16

data

2 

A Gain

Offset

FIR5

sin(x)

cos

sin

2 

+/-

IOUTB1

IOUTB2

16-Bit

DAC

B Gain

Offset

sin(x)

sin

cos

DEMUX

DAC5686

SLWS147B APRIL 2003 REVISED AUGUST 2004

DETAILED DESCRIPTION (continued)

Figure 19. Data Path in SSB Mode

Figure 20 shows the DAC5686 interfaced to an RF quadrature modulator. The outputs of the complex mixer
stage can be expressed as:

A(t) = I(t)cos(

t) Q(t)sin(

t) = m(t)

B(t) = I(t)sin(

t) + Q(t)cos(

t) = m

(t)

where m(t) and m

(t) connote a Hilbert transform pair. Upper single-sideband up-conversion is achieved at the

output of the analog quadrature modulator, whose output is expressed as:

IF(t) = A(t)cos(

)t B(t)sin(

Flexibility is provided to the user by allowing for the selection of B(t) out, which results in lower-sideband
up-conversion. This option is selected by ssb in the config_msb register. Figure 21 depicts the magnitude
spectrum along the signal path during single-sideband up-conversion for real input. Further flexibility is provided
to the user by allowing for the inverse of sin to be used in the complex mixer by programming rspect in the
config_usb register. The four combinations of rspect and ssb allow the user to select one of four complex
spectral bands to input to a quadrature modulator (see Figure 22).

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DAC

Quadrature

Modulator

DAC5686

cos(

sin(

cos(

A(t) = I(t)cos(

t) Q(t)sin(

B(t) = I(t)sin(

t) Q(t)cos(

cos(

sin(

IF(t) = I(t)cos(

 Q(t)sin(

Real Input

Spectrum

to DAC5686

Complex Input

Spectrum

to Quadrature Modulator

Output Spectrum

to Quadrature Modulator

DAC5686

SLWS147B APRIL 2003 REVISED AUGUST 2004

DETAILED DESCRIPTION (continued)

Figure 20. DAC5686 in SSB Mode With Quadrature Modulator

Figure 21. Spectrum After First and Second Up-Converson for Real Input

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Complex Input

Spectrums

to Quadrature

Modulator

rspect = 0

ssb = 0

rspect = 1

ssb = 0

rspect = 1

ssb = 1

rspect = 0

ssb = 1

Complex Input

Spectrum

to DAC5686

DAC Gain and Offset Control

Quadrature Modulation Mode

DAC5686

SLWS147B APRIL 2003 REVISED AUGUST 2004

DETAILED DESCRIPTION (continued)

Figure 22. Spectrum After First and Second Up-Converson for Complex Input

To compensate for the sinx/x rolloff of the zero-order hold of the DACs, the DAC5686 provides an inverse sinc
FIR, which provides high-frequency boost. The magnitude spectral response of this filter is presented in the
Digital Filters section.

Unmatched gains and offsets at the RF quadrature modulator result in unwanted sideband and local-oscillator
feedthrough. Gain and offset imbalances between the two DACs are compensated for by programming
daca_gain, dacb_gain, daca_offset, and dacb_offset in registers 0x0A through 0x0F (see the following
register descriptions). The DAC gain value controls the full-scale output current. The DAC offset value adds a
digital offset to the digital data before digital-to-analog conversion. Care must be taken when using the offset by
restricting the dynamic range of the digital signal to prevent saturation when the offset value is added to the
digital signal.

In quadrature modulation mode, on-chip mixing of complex I and Q inputs provides the final baseband-to-IF
up-conversion. Quadrature modulation mode is selected by mode[1:0] = 10 in the config_lsb register. Figure 23
shows the data path architecture in quadrature modulation mode. Complex baseband I and Q from the
ASIC/FPGA are input to the DAC5686, which in turn quadrature modulates I and Q to produce the final IF
single-sideband spectrum. DAC A is held constant, while DAC B presents the DAC5686 quadrature modulator
mode output.

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FIR1

FIR2

FIR3

FIR4

IOUTB1

IOUTB2

16-Bit

DAC

DA[15:0]

DB[15:0]

2 16

data

B Gain

Offset

FIR1

FIR2

FIR3

FIR4

FIR5

sin(x)

+/-

cos

sin

cos

DEMUX

Serial Interface

DAC5686

SLWS147B APRIL 2003 REVISED AUGUST 2004

DETAILED DESCRIPTION (continued)

NCO mixing frequencies are programmed through 32-bit freq (4 registers); 16-bit phase adjustments are
programmed through phase (2 registers). The NCO operates at the DAC update rate; thus, increased amounts
of interpolation allow for higher IFs. More details for the NCO are provided in the NCO section. For mixing to
F

dac

/4, the DAC5686 provides a specific architecture that exploits the {

...

1 0 1 0

...

} resultant streams from sin

and cos; the NCO is shut off in this mode to conserve power. F

dac

/4 mix mode is implemented by deasserting

nco in register config_msb while in single-sideband or quadrature modulation mode.

Figure 23. Data Path in Quadrature Modulation Mode

In quadrature modulation mode, only one output from the complex mixer stage is routed to the B DAC. The
output can be expressed as:

B(t) = I(t)sin(

t) + Q(t)cos(

B(t) = I(t)cos(

t) Q(t)sin(

Single-sideband up-conversion is achieved when I and Q are Hilbert transform pairs. Upper- or lower-sideband
up-conversion is selected by ssb in the config_msb register, which selects the output from the mixer stage that
is routed out.

The offset and gain features for the B DAC, as previously described, are functional in the quadrature mode.

The serial port of the DAC5686 is a flexible serial interface that communicates with industry-standard
microprocessors and microcontrollers. The interface provides read/write access to all registers used to define the
operating modes of the DAC5686. It is compatible with most synchronous transfer formats and can be configured
as a 3- or 4-pin interface by sif4 in register config_msb. In both configurations, SCLK is the serial-interface
input clock and SDENB is the serial-interface enable. For the 3-pin configuration, SDIO is a bidirectional pin for
both data-in and data-out. For the 4-pin configuration, SDIO is data-in only and SDO is data-out only.

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Serial-Port Timing Diagrams

DAC5686

SLWS147B APRIL 2003 REVISED AUGUST 2004

DETAILED DESCRIPTION (continued)

Each read/write operation is framed by signal SDENB (serial data enable bar) asserted low for 2 to 5 bytes,
depending on the data length to be transferred (14 bytes). The first frame byte is the instruction cycle, which
identifies the following data transfer cycle as read or write, how many bytes to transfer, and the address to/from
which to transfer the data. Table 1 indicates the function of each bit in the instruction cycle and is followed by a
detailed description of each bit. Frame bytes 2 through 5 comprise the data to be transferred.

Table 1. Instruction Byte of the Serial Interface

MSB

LSB

Bit

Description

R/W

R/W: Identifies the following data transfer cycle as a read or write operation. A high indicates a read operation
from the DAC5686 and a low indicates a write operation to the DAC5686.

N[1:0]: Identifies the number of data bytes to be transferred per Table 2. Data is transferred MSB-first.

Table 2. Number of Transferred Bytes Within One

Communication Frame

DESCRIPTION

Transfer 1 byte

Transfer 2 bytes

Transfer 3 bytes

Transfer 4 bytes

A4: Unused

A[3:0]: Identifies the address of the register to be accessed during the read or write operation. For multibyte
transfers, this address is the starting address and the address decrements. Note that the address is written to the
DAC5686 MSB-first.

Figure 24 shows the serial-interface timing diagram for a DAC5686 write operation. SCLK is the serial-interface
clock input to the DAC5686. Serial data enable SDENB is an active-low input to the DAC5686. SDIO is serial
data-in. Input data to the DAC5686 is clocked on the rising edges of SCLK.

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R/W

SCLKL

SDENB

SCLK

SDIO

N1 N0

A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0

SDENB

SCLK

SDIO

Instruction Cycle

Data Transfer Cycle(s)

s(SDENB)

SCLK

h(SDIO)

s(SDIO)

SCLKH

R/W

SDENB

SCLK

SDIO

N1 N0

A3 A2 A1 A0

D6 D5 D4 D3 D2

D0 0

Instruction Cycle

Data Transfer Cycle(s)

SDO

D7 D6 D5 D4 D3 D2 D1 D0 0

3-Pin Configuration

Output

4-Pin Configuration

Output

SDENB

SCLK

SDIO

Data n

Data n-1

SDO

d(Data)

DAC5686

SLWS147B APRIL 2003 REVISED AUGUST 2004

Figure 24. Serial-Interface Write Timing Diagram

Figure 25 shows the serial-interface timing diagram for a DAC5686 read operation. SCLK is the serial-interface
clock input to the DAC5686. Serial data enable SDENB is an active-low input to the DAC5686. SDIO is serial
data-in during the instruction cycle. In the 3-pin configuration, SDIO is data-out from the DAC5686 during the
data transfer cycle(s), while SDO is in a high-impedance state. In the 4-pin configuration, SDO is data-out from
the DAC5686 during the data transfer cycle(s). SDO is never placed in the high-impedance state in the four-pin
configuration.

Figure 25. Serial-Interface Read Timing Diagram

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Clock Generation

_align

CLK2

0.5 ns

DAC5686

SLWS147B APRIL 2003 REVISED AUGUST 2004

In the DAC5686, the internal clocks (1

, 2

, 4

, 8

, and 16

, as needed) for the logic, FIR interpolation filters,

and DAC are derived from a clock at either the input data rate using an internal PLL (PLL clock mode) or the
DAC output sample rate (external clock mode). Power for the internal PLL blocks (PLLVDD and PLLGND) is
separate from power for the other clock generation blocks (CLKVDD and CLKGND), thus minimizing phase noise
within the PLL.

The DAC5686 has three clock modes for generating the internal clocks (1

, 2

, 4

, 8

, and 16

, as needed) for

the logic, FIR interpolation filters, and DACs. The clock mode is set using the PLLVDD pin and dual_clk in
register config_usb. A block diagram for the clock generation circuit is shown in Figure 27.

1. PLLVDD = 0V and dual_clk = 0: EXTERNAL CLOCK MODE

In EXTERNAL CLOCK MODE, the user provides a clock signal at the DAC output sample rate through
CLK2/CLK2C. CLK1/CLK1C and the internal PLL are not used, so the LPF circuit is not applicable. The input
data rate clock and interpolation rate are selected by the registers sel[1:0], and are output through the
PLLLOCK pin. It is common to use the PLLLOCK clock to drive the chip that sends the data to the DAC;
otherwise, there is phase ambiguity regarding how the DAC divides down to the input sample rate clock and
an external clock divider divides down. (For a divide by N, there are N possible phases.) The phase
ambiguity can also be solved by using PHSTR pin with a synchronization signal.

2. PLLVDD = 3.3V (dual_clk can be 0 or 1 and is ignored): PLL CLOCK MODE

Power for the internal PLL blocks (PLLVDD and PLLGND) is separate from power for the other clock
generation blocks (CLKVDD and CLKGND), thus minimizing PLL phase noise.

In PLL CLOCK MODE, the DAC is driven at the input sample rate (unless the data is multiplexed) through
CLK1/CLK1C. CLK2/CLK2C is not used. In this case, there is no phase ambiguity on the clock. The DAC
generates the higher speed DAC sample rate clock using an internal PLL/VCO. In PLL clock mode, the user
provides a differential external reference clock on CLK1/CLK1C.

A type-4 phase-frequency detector (PFD) in the internal PLL compares this reference clock to a feedback
clock and drives the PLL to maintain synchronization between the two clocks. The feedback clock is
generated by dividing the VCO output by 1

, 2

, 4

, or 8

as selected by the prescaler (div[1:0]). The output

of the prescaler is the DAC sample rate clock and is divided down to generate clocks at

8, and

16.

The feedback clock is selected by the registers sel[1:0], an then is fed back to the PFD for synchronization
to the input clock. The feedback clock is also used for the data input rate, so the ratio of DAC output clock to
feedback clock sets the interpolation rate of the DAC5686. The PLLLOCK pin is an output that indicates
when the PLL has achieved lock. An external RC low-pass PLL filter is provided by the user at pin LPF. See
the low-pass filter section for filter setting calculations. This is the only mode where the LPF filter applies.

3. PLLVDD = 0V and dual_clk = 1: DUAL CLOCK MODE

In DUAL CLOCK MODE, the DAC is driven at the DAC sample rate through CLK2/CLK2C and at the input
data rate through CLK1/CLK1C. The DUAL CLOCK MODE has the advantage of a clean external clock for
the DAC sampling without the phase ambiguity. The edges of CLK1 and CLK2 must be aligned to within

_align

(See Figure 26), defined as

where F

CLK2

is the clock frequency of CLK2. For example, t

_align

= 0.5 ns at F

CLK2

= 500 MHz and 1.5 ns at

CLK2

= 250 MHz.

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CLK2

CLK1

D[0:15]

< t

align

T0002-01

PLLVDD

PLLGND

CLKGND

CLKVDD

pfd

Charge

Pump

vco

/1
/2
/4
/8

clk_16x
DAC
Sample
Clock

D[15:0]

DIV[1:0]

PLLVDD

SEL[1:0]

PLLVDD

PLLLOCK

LPF

Data

clk_2x

clk_1x

clk_4x

clk_8x

CLK1

CLK1C

Clk Buffer

CLK2

CLK2C

Clk Buffer

DAC5686

SLWS147B APRIL 2003 REVISED AUGUST 2004

Figure 26. DAC and Data Clock Mode

The CDC7005 from Texas Instruments is recommended for providing phase-aligned clocks at different
frequencies for this application.

Table 3 provides a summary of the clock configurations with corresponding data rate ranges.

Figure 27. Clock-Generation Architecture

Table 3. Clock-Mode Configuration

CLOCK MODE

PLLVDD

DIV[1:0]

SEL[1:0]

DATA RATE (MSPS)

PLLLOCK PIN FUNCTION

Non-interleaved input data; internal PLL off; DA[15:0] data rate matches DB[15:0] data rate.

External 2

0 V

DC to 160

External clk2/clk2c clock

External 4

0 V

DC to 125

External clk2/clk2c clock

External 8

0 V

DC to 62.5

External clk2/clk2c clock

External 16

0 V

DC to 31.25

External clk2/clk2c clock

External dual clock 2

0 V

DC to 160

None - held low

External dual clock 4

0 V

DC to 125

None - held low

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DAC5686

SLWS147B APRIL 2003 REVISED AUGUST 2004

Table 3. Clock-Mode Configuration (continued)

CLOCK MODE

PLLVDD

DIV[1:0]

SEL[1:0]

DATA RATE (MSPS)

PLLLOCK PIN FUNCTION

External dual clock 8

0 V

DC to 62.5

None - held low

External dual clock 16

0 V

DC to 31.25

None - held low

Interleaved input data on the DA[15:0] input pins; internal PLL off

External 2

0 V

DC to 80

External clk2/clk2c clock

External 4

0 V

DC to 80

External clk2/clk2c clock

External 8

0 V

DC to 62.5

External clk2/clk2c clock

External 16

0 V

DC to 31.25

External clk2/clk2c clock

External dual clock 2

0 V

DC to 80

None - held low

External dual clock 4

0 V

DC to 62.5

None - held low

External dual clock 8

0 V

DC to 31.25

None - held low

External dual clock 16

0 V

DC to 15.625

None - held low

Non-interleaved input data; internal PLL on; DA[15:0] data rate matches DB[15:0] data rate.

Internal 2

3.3 V

125 to 160

Internal PLL lock indicator

Internal 2

3.3 V

62.5 to 125

Internal PLL lock indicator

Internal 2

3.3 V

31.25 to 62.5

Internal PLL lock indicator

Internal 2

3.3 V

15.63 to 31.25

Internal PLL lock indicator

Internal 4

3.3 V

62.5 to 125

Internal PLL lock indicator

Internal 4

3.3 V

31.25 to 62.5

Internal PLL lock indicator

Internal 4

3.3 V

15.63 to 31.25

Internal PLL lock indicator

Internal 4

3.3 V

7.8125 to 15.625

Internal PLL lock indicator

Internal 8

3.3 V

31.25 to 62.5

Internal PLL lock indicator

Internal 8

3.3 V

15.63 to 31.25

Internal PLL lock indicator

Internal 8

3.3 V

7.8125 to 15.625

Internal PLL lock indicator

Internal 8

3.3 V

3.9 to 7.8125

Internal PLL lock indicator

Internal 16

3.3 V

15.625 to 31.25

Internal PLL lock indicator

Internal 16

3.3 V

7.8125 to 15.625

Internal PLL lock indicator

Internal 16

3.3 V

3.9062 to 7.8125

Internal PLL lock indicator

Interleaved input data on the DA[15:0] input pins; internal PLL on

Internal 2

3.3 V

Not recommended

Internal PLL lock indicator

Internal 2

3.3 V

62.5 to 80

Internal PLL lock indicator

Internal 2

3.3 V

31.25 to 62.5

Internal PLL lock indicator

Internal 2

3.3 V

15.625 to 31.25

Internal PLL lock indicator

Internal 4

3.3 V

62.5 to 80

Internal PLL lock indicator

Internal 4

3.3 V

31.25 to 62.5

Internal PLL lock indicator

Internal 4

3.3 V

15.625 to 31.25

Internal PLL lock indicator

Internal 4

3.3 V

7.8125 to 15.625

Internal PLL lock indicator

Internal 8

3.3 V

31.25 to 62.5

Internal PLL lock indicator

Internal 8

3.3 V

15.625 to 31.25

Internal PLL lock indicator

Internal 8

3.3 V

7.8125 to 15.625

Internal PLL lock indicator

Internal 8

3.3 V

3.9062 to 7.8125

Internal PLL lock indicator

Internal 16

3.3 V

15.625 to 31.25

Internal PLL lock indicator

Internal 16

3.3 V

7.8125 to 15.625

Internal PLL lock indicator

Internal 16

3.3 V

3.9062 to 7.8125

Internal PLL lock indicator

Internal 16

3.3 V

1.9531 to 3.9062

Internal PLL lock indicator

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Dual-Bus Mode

IOUTB1

IOUTB2

IOUTA1

IOUTA2

16-Bit

DAC

DA[15:0]

DB[15:0]

data

2 16

data

16-Bit

DAC

data

FIR1

Edge Triggered

Input Latches

· ·

DEMUX

CLK1

DA[15:0]

DB[15:0]

s(DATA)

h(DATA)

N+1

CLK2

DA[15:0]

DB[15:0]

s(DATA)

h(DATA)

N+1

PLLLOCK

d(PLLLOCK)

DAC5686

SLWS147B APRIL 2003 REVISED AUGUST 2004

In dual-bus mode, two separate parallel data streams (I and Q) are input to the DAC5686 on data bus DA and
data bus DB. Dual-bus mode is selected by setting INTERL to 0 in the config_msb register. Figure 28 shows
the DAC5686 data path in dual-bus mode. The dual-bus mode timing diagram is shown in Figure 29 for the PLL
clock mode and in Figure 30 for the external clock mode.

Figure 28. Dual-Bus Mode Data Path

Figure 29. Dual-Bus Mode Timing Diagram (PLL Mode)

Figure 30. Dual-Bus Mode Timing Diagram (External Clock Mode)

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Interleave Bus Mode

IOUTB1

IOUTB2

IOUTA1

IOUTA2

16-Bit

DAC

data

2 16

data

16-Bit

DAC

data

FIR1

Edge Triggered

Input Latches

· ·

DA[15:0]

DEMUX

DA[15:0]

s(DATA)

h(DATA)

TxENABLE

s(TxENABLE)

CLK1 or

PLLLOCK

DAC5686

SLWS147B APRIL 2003 REVISED AUGUST 2004

In interleave bus mode, one parallel data stream with interleaved data (I and Q) is input to the DAC5686 on data
bus DA. Interleave bus mode is selected by setting INTERL to 1 in the config_msb register. Figure 31 shows
the DAC5686 data path in interleave bus mode. The interleave bus mode timing diagram is shown in Figure 32.

Figure 31. Interleave Bus Mode Data Path

Figure 32. Interleave Bus Mode Timing Diagram Using TxENABLE

Interleaved user data on data bus DA is alternately multiplexed to internal data channels A and B. Data channels
A and B can be synchronized using either the QFLAG pin or the TxENABLE pin. When qflag in register
config_usb is 0, transitions on TxENABLE identify the interleaved data sequence. The first data after the rising
edge of TxENABLE is latched with the rising edge of CLK as channel-A data. Data is then alternately distributed
to B and A channels with successive rising edges of CLK. When qflag is 1, the QFLAG pin is used as an output
to identify the interleaved data sequence. QFLAG high identifies data as channel B (see Figure 33).

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DA[15:0]

s(DATA)

h(DATA)

QFLAG

CLK1 or

PLLLOCK

T0001-01

Clock Synchronization Using the PHSTR Pin in External Clock Mode

CLK2

PLLLOCK

CLK2C

T0003-01

DAC5686

SLWS147B APRIL 2003 REVISED AUGUST 2004

Figure 33. Interleave Bus Mode Timing Diagram Using QFLAG

The dual-clock mode is selected by setting dualclk high in the config_usb register. In this mode, the DAC5686
uses both clock inputs; CLK1/CLK1C is the input data clock, and CLK2/CLK2C is the external clock. The edges
of the two input clocks must be phase-aligned within

500 ps to function properly.

In external clock mode, the DAC5686 is clocked at the DAC output sample frequency (CLK2 and CLK2C). For an
interpolation rate N, there are N possible phases for the DAC input clock on the PLLLOCK pin (see Figure 34 for
N = 4).

Figure 34. Four Possible PLLLOCK Phases for N = 4 in External Clock Mode

To synchronize PLLLOCK input clocks across multiple DAC5686 chips, a sync signal on the PHSTR pin is used.
During configuration of the DAC5686 chips, address sync_phstr in config_msb is set high to enable the
PHSTR input pin as a sync input to the clock dividers generating the input clock. A simultaneous low-to-high
transition on the PHSTR pin for each DAC5686 then forces the input clock on PLLLOCK to start in phase on
each DAC. See Figure 35.

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PHSTR

D[0:15]

PLLLOCK

DAC1

CLK2

CLK2C

h_PHSTR

1/F

PLLLOCK

= N/F

CLK2

s_PHSTR

d_CLK

T0004-01

Digital Filters

DAC5686

SLWS147B APRIL 2003 REVISED AUGUST 2004

Figure 35. Using PHSTR to Synchronize PLLLOCK Input Clock for Multiple DACs in External Clock Mode

The PHSTR transition has a setup and hold time relative to the DAC output sample clock (t

s_PHSTR

and t

h_PHSTR

)

equal to 50% of the DAC output sample clock period up to a maximum of 1 ns. At 500 MHz, the setup and hold
times are therefore 0.5 ns. The PHSTR signal can remain high after synchronization, or can return low. A new
low-to-high transition resynchronizes the input clock. Note that the PHSTR transition also resets the NCO
accumulator.

Figure 36 through Figure 39 show magnitude spectrum responses for 2

, 4

, 8

, and 16

FIR interpolation

filtering. The transition band is from 0.4 to 0.6 f

DATA

with < 0.002-dB pass-band ripple and > 80-dB stop-band

attenuation for all four configurations. The filters are linear phase. The sel field in register config_lsb selects the
interpolation filtering rate as 2

, 4

, 8

, or 16

; interpolation filtering can be completely bypassed by setting

fullbypass in register config_lsb.

Figure 40 shows the spectral correction of the DAC sinx/x rolloff achieved with use of inverse sinc filtering.
Pass-band ripple from 0 to 0.4 f

DATA

is < 0.03 dB. Inverse sinc filtering is enabled by sinc in register

config_msb.

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f/F

Data

-160

-140

-120

-100

-80

-60

-40

-20

0.0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1.0

Magnitude dB

f/F

Data

-160

-140

-120

-100

-80

-60

-40

-20

0.0

0.2

0.4

0.6

0.8

1.0

1.2

1.4

1.6

1.8

2.0

Magnitude dB

f/F

Data

-160

-140

-120

-100

-80

-60

-40

-20

0.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

Magnitude dB

f/F

Data

-160

-140

-120

-100

-80

-60

-40

-20

Magnitude dB

DAC5686

SLWS147B APRIL 2003 REVISED AUGUST 2004

MAGNITUDE

FREQUENCY

Figure 36. Magnitude Spectrum for

Figure 37. Magnitude Spectrum for

Interpolation (dB)

MAGNITUDE

FREQUENCY

Figure 38. Magnitude Spectrum for

Figure 39. Magnitude Spectrum for

Interpolation (dB)

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f/F

DAC

-5

-4

-3

-2

-1

0.0

0.1

0.2

0.3

0.4

0.5

Magnitude dB

Rolloff

FIR

Corrected

DAC5686

SLWS147B APRIL 2003 REVISED AUGUST 2004

MAGNITUDE

FREQUENCY

Figure 40. Magnitude Spectrum for Inverse Sinc Filtering

The filter taps for interpolation filters FIR1 - FIR4 and inverse sinc filter FIR5 are listed in Table 4.

Table 4. Filter Taps for FIR1FIR5

FIR1

FIR2

FIR3

FIR4

FIR5 (INVSINC)

-33

219

289

512

214

1212

289

400

2048

120

638

1212

221

2521

219

4096

380

2521

619

638

-971

214

1490

2288

3649

6628

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NCO

Frequency

Register

Accumulator

RESET

CLK

PHSTR

Phase

Register

Look-Up

Table

sin

cos

DAC

DAC5686

SLWS147B APRIL 2003 REVISED AUGUST 2004

Table 4. Filter Taps for FIR1FIR5 (continued)

FIR1

FIR2

FIR3

FIR4

FIR5 (INVSINC)

20750

32768

20750

6628

3649

2288

1490

971

619

380

221

120

The DAC5686 uses a numerically controlled oscillator (NCO) with a 32-bit frequency register and a 16-bit phase
register. The NCO is used in quadrature-modulation and single-sideband modes to provide sin and cos for
mixing. The NCO tuning frequency is programmed in registers 0x1 through 0x4. Phase offset is programmed is
registers 0x5 and 0x6. A block diagram of the NCO is shown in Figure 41.

Figure 41. Block Diagram of the NCO

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NCO

freq

DAC

Register Bit Allocation Map

REGISTER DESCRIPTIONS

DAC5686

SLWS147B APRIL 2003 REVISED AUGUST 2004

The NCO accumulator is reset to zero when the PHSTR pin is high and remains at zero until PHSTR is set low.
Frequency word freq in the frequency register is added to the accumulator every clock cycle. The output
frequency of the NCO is:

While the maximum clock frequency of the DACs is 500 MSPS, the maximum clock frequency the NCO can
operate at is 320 MHz; mixing at DAC rates higher than 320 MSPS requires using the fs/4 mixing option.

NAME

R/W

AD-

BIT 7

BIT 6

BIT 5

BIT 4

BIT 3

BIT 2

BIT 1

BIT 0

DRESS

chip_ver

R/W

0x00

atest[4:0]

version[2:0] read only

freq_lsb

R/W

0x01

freq_int[7:0]

freq_lmidsb

R/W

0x02

freq_int[15:8]

freq_umidsb

R/W

0x03

freq_int[23:16]

freq_msb

R/W

0x04

freq_int[31:24]

phase_lsb

R/W

0x05

phase_int[7:0]

phase_msb

R/W

0x06

phase_int[15:8]

config_lsb

R/W

0x07

mode[1:0]

div[1:0]

sel[1:0]

counter

fbypass

config_msb

R/W

0x08

ssb

interl

sinc

dith

sync_phstr

nco

sif4

twos

config_usb

R/W

0x09

dual clk

dds_gain[1:0]

rspect

qflag

pll_rng[1:0]

rev_bbus

daca_offset_lsb

R/W

0x0A

daca_offset[7:0]

daca_gain_lsb

R/W

0x0B

daca_gain[7:0]

daca_offset_gain_

R/W

0x0C

daca_offset[10:8]

sleepA

daca_gain[11:8]

msb

dacb_offset_lsb

R/W

0x0D

dacb_offset[7:0]

dacb_gain_lsb

R/W

0x0E

dacb_gain[7:0]

dacb_offset_gain_

R/W

0x0F

dacb_offset[10:8]

sleepB

dacb_gain[11:8]

msb

Register Name: chip_ver

MSB

LSB

atest[4:0]

chip_ver[2:0] read only

chip_ver[3:0]: chip_ver [3:0] stores the device version, initially 0x5. The user can find out which version of the
DAC5686 is in the system by reading this byte.

a_test[4:0]: must be 0 for proper operation.

Register Name: freq_lsb

MSB

LSB

freq_int[7:0]

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DAC5686

SLWS147B APRIL 2003 REVISED AUGUST 2004

freq_int[7:0]: The lower 8 bits of the frequency register in the DDS block

Register Name: freq_lmidsb

MSB

LSB

freq_int[15:8]

freq_int[15:8]: The lower mid 8 bits of the frequency register in the DDS block

Register Name: freq_umidsb

MSB

LSB

freq_int[23:16]

freq_int[23:16]: The upper mid 8 bits of the frequency register in the DDS block

Register Name: freq_msb

MSB

LSB

freq_int[31:24]

freq_int[31:24]: The most significant 8 bits of the frequency register in the DDS block

Register Name: phase_lsb

MSB

LSB

phase_int[7:0]

phase_int[7:0]: The lower 8 bits of the phase register in the DDS block

Register Name: phase_msb

MSB

LSB

phase_int[15:8]

phase_int[15:8]: The most significant 8 bits of the phase register in the DDS block

Register Name: config_lsb

MSB

LSB

mode[1:0]

div[1:0]

sel[1:0]

counter

Full_bypass

mode[1:0]: Controls the mode of the DAC5686; summarized in Table 5.

Table 5. DAC5686 Modes

mode[1:0]

DAC5686 MODE

Dual-DAC

Single-sideband

Quadrature

Dual-DAC

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DAC5686

SLWS147B APRIL 2003 REVISED AUGUST 2004

div[1:0]: Controls the PLL divider value; summarized in Table 6.

Table 6. PLL Divide Ratios

div[1:0]

PLL DIVIDE RATIO

divider

sel[1:0]: Controls the selection of interpolating filters used; summarized in Table 7.

Table 7. DAC5686 Filter Configuration

sel[1:0]

INTERP. FIR SETTING

counter: When asserted, the DAC5686 goes into counter mode and uses an internal counter as a ramp input to
the DAC. The count range is determined by the A-side input data DA[2:0], as summarized in Table 8.

Table 8. DAC5686 Counter Mode Count Range

DA[2:0]

COUNT RANGE

000

All bits D[15:0]

001

Lower 7 bits D[6:0]

010

Mid 4 bits D[10:7]

100

Upper 5 bits D[15:11]

Full_bypass: When asserted, the interpolation filters and mixer logic are bypassed and the data inputs DA[15:0]
and DB[15:0] go straight to the DAC inputs.

Register Name: config_msb

MSB

LSB

ssb

interl

sinc

dith

sync_phstr

nco

sif4

twos

ssb: In single-sideband mode, assertion inverts the B data; in quadrature modulation mode, assertion routes the
A data path to DACB instead of the B data path.

interl: When asserted, data input to the DAC5686 on channel DA[15:0] is interpreted as a single interleaved
stream (I/Q); channel DB[15:0] is unused.

sinc: Assertion enables the INVSINC filter.

dith: Assertion enables dithering in the PLL.

sync_phstr: Assertion enables the PHSTR input as a sync input to the clock dividers in external single-clock
mode.

nco: Assertion enables the NCO.

sif4: When asserted, the sif interface becomes a 4-pin interface instead of a 3-pin interface. The SDIO pin
becomes an input only and the SDO is the output.

twos: When asserted, the chip interprets the input data as 2s complement form instead of binary offset.

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DAC5686

SLWS147B APRIL 2003 REVISED AUGUST 2004

Register Name: config_usb

MSB

LSB

dualclk

DDS_gain[1:0]

rspect

qflag

pll_rng[1:0]

rev_bbus

dualclk: When asserted, the DAC5686 uses both clock inputs; CLK1/CLK1C is the input data clock and
CLK2/CLK2C is the DAC output clock. These two clocks must be phase-aligned within

500 ps to function

properly. When deasserted, CLK2/CLK2C is the DAC output clock and is divided down to generate the input data
clock, which is output on PLLLOCK. Dual clock mode is only available when PLLVDD = 0.

DDS_gain[1:0]: Controls the gain of the DDS so that the overall gain of the DDS is unity. It is important to
ensure that max(abs(cos(

t) + sin(

t))) < 1. At different frequencies, the summation produces different maximum

outputs and must be reduced. The simplest is fs/4 mode where the maximum is 1 and the gain multiply should
be 1 to maintain unity. However, due to the fact that the digital logic does a divide-by-two in this summation, the
gain necessary to achieve unity must be double (DDS_gain[1:0] = 01). Table 9 shows the digital gain necessary
and the actual signal gain needed to make the above equation have a maximum value of 1.

Table 9. Digital Gain for DDS

DDS_gain [1:0]

DIGITAL GAIN

SIGNAL GAIN FOR UNITY

1.40625

0.703125

1.59375

0.7936

1.40625

0.703125

rspect: When asserted, the sin term is negated before being used in mixing. This gives the reverse spectrum in
single-sideband mode.

qflag: When asserted, the QFLAG pin is used during interleaved data input mode to identify the Q sample. When
deasserted, the TXENABLE pin transition is used to start an internal toggling signal, which is used to interpret
the interleaved data sequence; the first sample clocked into the DAC5686 after TXENABLE goes high is routed
through the A data path.

PLL_rng[1:0]: Increases the PLL VCO VtoI current, summarized in Table 10. See Figure 17 for the effect on
VCO gain and range.

Table 10. PLL VCO Vtol Current Increase

PLL_rng[1:0]

VtoI CURRENT INCREASE

nominal

15%

30%

45%

rev_bbus[1:0]: When asserted, pin 92 changes from DB15 to DB0, pin 91 changes from DB14 to DB1, etc.,
reversing the order of the DB[15:0] pins.

Register Name: daca_offset_lsb (2s complement)

MSB

LSB

daca_offset[7:0]

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fullscale

16 V

extio

biasj

(GAINCODE

)

FINEGAIN

3072

DAC5686

SLWS147B APRIL 2003 REVISED AUGUST 2004

daca_offset[7:0]: The lower 8 bits of the DACA offset

Register Name: daca_gain_lsb (2s complement)

MSB

LSB

daca_gain[7:0]

daca_gain[7:0]: The lower 8 bits of the DACA gain control register. These lower 8 bits are for fine gain control.
This word is a 2s complement value that adjusts the full-scale output current over an approximate 4% to 4%
range.

Register Name: daca_offset_gain_msb (2s complement)

MSB

LSB

daca_offset[10:8]

sleepa

daca_gain[11:8]

daca_offset[10:8]: The upper 3 bits of the DACA _offset

sleepa: When asserted, DACA is put into the sleep mode.

daca_gain[11:8]: Coarse gain control for DACA; the full-scale output current is:

where GAINCODE is the decimal equivalent of daca_gain [11:8] {0

...

15} and the FINEGAIN is daca_gain [1:0] as

2s complement [127

...

128].

Register Name: dacb_offset_lsb (2s complement)

MSB

LSB

dacb_offset[7:0]

dacb_offset[7:0]: The lower 8 bits of the DACB offset

Register Name: dacb_gain_lsb (2s complement)

MSB

LSB

dacb_gain[7:0]

dacb_gain[7:0]: The lower 8 bits of the DACB gain control register. These lower 8 bits are for fine gain control.
This word is a 2s complement value that adjusts the full-scale output current over an approximate 4% to 4%
range.

Register Name: dacb_offset_gain_msb (2s complement)

MSB

LSB

dacb_offset[10:8]

sleepb

dacb_gain[11:8]

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fullscale

16 V

extio

biasj

(GAINCODE

)

FINEGAIN

3072

DIGITAL INPUTS

DA[15:0]
DB[15:0]

SLEEP

PHSTR

TxENABLE

QFLAG

SDIO

SCLK

SDENB

Internal
Digital In

IOVDD

IOGND

RESETB

Internal
Digital In

IOVDD

IOGND

CLOCK INPUT AND TIMING

CLK

Internal

Digital In

CLKC

CLKGND

R1
10 k

CLKVDD

10 k

R2
10 k

CLKVDD

DAC5686

SLWS147B APRIL 2003 REVISED AUGUST 2004

dacb_offset[10:8]: The upper 3 bits of the DACA _offset

sleepb: When asserted, DACB is put into the sleep mode.

dacb_gain[11:8]: Coarse gain control for DACB; the full-scale output current is:

where GAINCODE is the decimal equivalent of dacb_gain [11:8] {0

...

15} and the FINEGAIN is dacb_gain [1:0] as

2s complement [127

...

128].

Figure 42 shows a schematic of the equivalent CMOS digital inputs of the DAC5686. DA[0:15], DB[0:15], SLEEP,
PHSTR, TxENABLE, QFLAG, SDIO, SCLK, and SDENB have pulldown resistors and RESETB has a pullup
resistor internal to the DAC5686. See the specification table for logic thresholds.

Figure 42. CMOS/TTL Digital Equivalent Input

Figure 43 shows an equivalent circuit for the clock input.

Figure 43. Clock Input Equivalent Circuit

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200

CLK

1:4

CLKC

Termination Resistor

Swing Limitation

Optional, May Be Bypassed

for Sine Wave Input

0.1

opt

CLK

1:1

CLKC

Optional, Reduces

Clock Feed-Through

0.01

TTL/CMOS

Source

opt

CLK

CLKC

Node CLKC Internally Biased

to CLKVDD 2

TTL/CMOS

Source

0.01

130

0.1

130

Differential

ECL

(LV)PECL

Source

CLK

CLKC

82.5

100

DAC5686

SLWS147B APRIL 2003 REVISED AUGUST 2004

CLOCK INPUT AND TIMING (continued)

Figure 44, Figure 45, and Figure 46 show various input configurations for driving the differential clock input
(CLK/CLKC).

Figure 44. Preferred Clock Input Configuration

Figure 45. Driving the DAC5686 With a Single-Ended TTL/CMOS Clock Source

Figure 46. Driving the DAC5686 With a Differential ECL/PECL Clock Source

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DAC Transfer Function

IOUT1

IOUT

CODE

65536

IOUT2

IOUT

(65536

CODE)

65536

VOUT1

IOUT1

CODE

65536

IOUT

VOUT2

IOUT2

(65536

CODE)

65536

IOUT

VOUT

DIFF

IOUT1

VOUT2

(2CODE

65536)

65536

IOUT

Reference Operation

IOUT

EXTIO

BIAS

DAC5686

SLWS147B APRIL 2003 REVISED AUGUST 2004

CLOCK INPUT AND TIMING (continued)

The CMOS DACs consist of a segmented array of NMOS current sources, capable of delivering a full-scale
output current up to 20 mA. Differential current switches direct the current of each current source to either one of
the complementary output nodes IOUT1 or IOUT2. Complementary output currents enable differential operation,
thus canceling out common-mode noise sources (digital feed-through, on-chip, and PCB noise), dc offsets,
even-order distortion components, and increasing signal output power by a factor of two.

The full-scale output current is set using external resistor R

BIAS

in combination with an on-chip band-gap voltage

reference source (1.2 V) and control amplifier. Current I

BIAS

through resistor R

BIAS

is mirrored internally to provide

a full-scale output current equal to 16 times I

BIAS

. The full-scale current can be adjusted from 20 mA down to 2

mA.

The DAC5686 delivers complementary output currents IOUT1 and IOUT2. Output current IOUT1 equals the
approximate full-scale output current when all bits (after the digital processing) are high. Full-scale output current
flows through terminal IOUT2 when all input bits are low. The relation between IOUT1 and IOUT2 can thus be
expressed as:

IOUT1 = IOUT

IOUT2

where IOUT

is the full-scale output current. The output currents can be expressed as:

where CODE is the decimal representation of the DAC data input word. Output currents IOUT1 and IOUT2 drive
resistor loads R

or a transformer with equivalent input load resistance (R

). This translates into single-ended

voltages VOUT1 and VOUT2 at terminals IOUT1 and IOUT2, respectively, of:

The differential output voltage VOUT

DIFF

can thus be expressed as:

The latter equation shows that applying the differential output results in doubling of the signal power delivered to
the load. Because the output currents IOUT1 and IOUT2 are complementary, they become additive when
processed differentially. Note that care should be taken not to exceed the compliance voltages at nodes IOUT1
and IOUT2, which would lead to increased signal distortion.

The DAC5686 comprises a band-gap reference and control amplifier for biasing the full-scale output current. The
full-scale output current is set by applying an external resistor R

BIAS

. The bias current I

BIAS

through resistor R

BIAS

is defined by the on-chip band-gap reference voltage and control amplifier. The full-scale output current equals
16 times this bias current. The full-scale output current IOUT

can thus be expressed as (coarse gain = 15, fine

gain = 0):

where V

EXTIO

is the voltage at terminal EXTIO. The band-gap reference voltage delivers an accurate voltage of

1.2 V. This reference is active when terminal EXTLO is connected to AGND. An external decoupling capacitor

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Analog Current Outputs

IOUT1

IOUT2

S(1)

S(1)C

LOAD

S(2)

S(2)C

S(N)

S(N)C

AVDD

DAC5686

SLWS147B APRIL 2003 REVISED AUGUST 2004

CLOCK INPUT AND TIMING (continued)

EXT

of 0.1

F should be connected externally to terminal EXTIO for compensation. The band-gap reference

additionally can be used for external reference operation. In that case, an external buffer with a high-impedance
input should be used in order to limit the band-gap load current to a maximum of 100 nA. The internal reference
can be disabled and overridden by an external reference by connecting EXTLO to AVDD. Capacitor C

EXT

may

hence be omitted. Terminal EXTIO serves as either input or output node.

The full-scale output current can be adjusted from 20 mA down to 2 mA by varying resistor R

BIAS

or changing the

externally applied reference voltage. The internal control amplifier has a wide input range supporting the
full-scale output current range of 20 dB.

Figure 47 shows a simplified schematic of the current source array with corresponding switches. Differential
switches direct the current of each individual NMOS current source to either the positive output node IOUT1 or
its complementary negative output node IOUT2. The output impedance is determined by the stack of the current
sources and differential switches, and is typically >300 k

in parallel with an output capacitance of 5 pF.

The external output resistors are terminated to AVDD. The maximum output compliance at nodes IOUT1 and
IOUT2 is limited to AVDD + 0.5 V, determined by the CMOS process. Beyond this value, transistor breakdown
can occur, resulting in reduced reliability of the DAC5686 device. The minimum output compliance voltage at
nodes IOUT1 and IOUT2 equals AVDD 0.5 V. Exceeding the minimum output compliance voltage adversely
affects distortion performance and integral nonlinearity. The optimum distortion performance for a single-ended
or differential output is achieved when the maximum full-scale signal at IOUT1 and IOUT2 does not exceed
0.5 V.

Figure 47. Equivalent Analog Current Output

The DAC5686 can be easily configured to drive a doubly terminated 50-

cable using a properly selected RF

transformer. Figure 48 and Figure 49 show the 50-

doubly terminated transformer configuration with 1:1 and

4:1 impedance ratios, respectively. Note that the center tap of the primary input of the transformer must be
connected to AVDD to enable a dc current flow. Applying a 20-mA full-scale output current would lead to a
0.5-Vpp output for a 1:1 transformer and a 1-Vpp output for a 4:1 transformer.

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IOUT1

1:1

IOUT2

LOAD

100

AVDD (3.3 V)

IOUT1

4:1

IOUT2

100

LOAD

AVDD (3.3 V)

SLEEP MODE

POWER-UP SEQUENCE

DAC5686

SLWS147B APRIL 2003 REVISED AUGUST 2004

CLOCK INPUT AND TIMING (continued)

Figure 48. Driving a Doubly Terminated 50-

Cable Using a 1:1 Impedance-Ratio Transformer

Figure 49. Driving a Doubly Terminated 50-

Cable Using a 4:1 Impedance-Ratio Transformer

The DAC5686 features a power-down mode that turns off the output current and reduces the supply current to
less than 5 mA over the supply range of 3 V to 3.6 V and temperature range of 40

C to 85

C. The power-down

mode is activated by applying a logic level 1 to the SLEEP pin (e.g., by connecting pin SLEEP to IOVDD). An
internal pulldown circuit at node SLEEP ensures that the DAC5686 is enabled if the input is left disconnected.
Power-up and power-down activation times depend on the value of the external capacitor at node SLEEP. For a
nominal capacitor value of 0.1 mF, it takes less than 5 ms to power down and approximately 3 ms to power up.

In all conditions, bring up DVDD first. If PLLVDD is powered (PLL on), CLKVDD should be powered before or
simultaneously with PLLVDD. AVDD, CLKVDD and IOVDD can be powered simultaneously or in any order.
Within AVDD, the multiple AVDD pins should be powered simultaneously.

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DAC5686 EVALUATION BOARD

Appendix A. PLL LOOP FILTER COMPONENTS

External

Internal

S0006-01

DAC5686

SLWS147B APRIL 2003 REVISED AUGUST 2004

There is a combination EVM board for the DAC5686 digital-to-analog converter for evaluation. This board allows
the user the flexibility to operate the DAC5686 in various configurations. Possible output configurations include
transformer-coupled, resistor-terminated, inverting/non-inverting and differential amplifier outputs. The digital
inputs are designed to be driven directly from various pattern generators with the onboard option to add a
resistor network for proper load termination.

For the external second-order filter shown in Figure 50, the components R, C1, and C2 are calculated for a
desired phase margin and loop bandwidth. Resistor R3 = 200

and capacitor C3 = 8 pF are internal to the

DAC5686.

Figure 50. DAC5686 Loop Filter

The VCO gain (Gvco) as a function of VCO frequency for the DAC5686 is shown in Figure 17. For a desired
VCO

frequency,

the

loop

filter

values

can

calculated

using

the

following

equations.

Nominal PLL design parameters include:

Charge pump current:

iqp = 1 mA

VCO gain:

VCO

= 2

VCO

rad/A

PLL divide ratio

interpolation:

N = {2, 4, 8, 16, 32}

Phase detector gain:

= iqp

A/rad

Let

Desired loop bandwidth =

Desired phase margin =

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+ t

1 1

* t

VCO

2
d

(

tan

)

sec

)

(

tan

)

sec

)

tan

)

sec

H(s)

VCO

)

sRC1)

RC1C2

)

(C1

)

C2)

f - Frequency - MHz

Gain - dB

0.01

0.1

100

-20

-40

-60

N = 2, 4, 8, 16, 32

-180

-160

-140

-120

-100

f - Frequency - MHz

Phase -

0.01

0.1

100

G005

DAC5686

SLWS147B APRIL 2003 REVISED AUGUST 2004

DAC5686 EVALUATION BOARD (continued)

Then

where

Example:

= 70

= 1 MHz, G

VCO

= 300e6 MHz/A

R (

)

C1 (

C2 (pF)

0.02

670

0.01

335

173

0.005

167

346

0.002

692

0.001

The calculated phase margin and loop bandwidth can be verified by plotting the gain and phase of the open-loop
transfer function given by

Figure 51 shows the open-loop gain and phase for the DAC5686 evaluation-board loop filter.

Figure 51. Open-Loop Phase and Gain Plots for DAC5686 Evaluation Board

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err

) w

(

]

phase step response

err

[

(

]

frequency step response

0.0

0.2

0.4

0.6

0.8

1.0

0.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

t - Time -

Normalized Phase Error

Response to a Frequency Step at Time 0

N = 2, 4, 8, 16, 32

Increasing N

G006

t - Time -

-0.5

0.0

0.5

1.0

0.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

Normalized Phase Error

Response to a Phase Step at Time 0

N = 2, 4, 8, 16, 32

Increasing N

DAC5686

SLWS147B APRIL 2003 REVISED AUGUST 2004

The phase error (

err

) phase and frequency step responses are given by the following equations and are plotted

in Figure 52 for the DAC5686 evaluation-board loop filter.

Figure 52. Phase and Frequency Step Responses for DAC5686 Evaluation Board

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Part Number DAC5686

Document Outline