Data sheet acquired from Harris Semiconductor
SCHS222C

Features

ˇ Independent Asynchronous Inputs and Outputs

ˇ Expandable in Either Direction

ˇ Reset Capability

ˇ Status Indicators on Inputs and Outputs

ˇ Three-State Outputs

ˇ Shift-Out Independent of Three-State Control

ˇ Fanout (Over Temperature Range)

- Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads

- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads

ˇ Wide Operating Temperature Range . . . -55

C to 125

ˇ Balanced Propagation Delay and Transition Times

ˇ Significant Power Reduction Compared to LSTTL

Logic ICs

ˇ HC Types

- 2V to 6V Operation

- High Noise Immunity: N

= 30%, N

= 30% of V

at V

= 5V

ˇ HCT Types

- 4.5V to 5.5V Operation

- Direct LSTTL Input Logic Compatibility,

= 0.8V (Max), V

= 2V (Min)

- CMOS Input Compatibility, I

A at V

, V

Applications

ˇ Bit-Rate Smoothing

ˇ CPU/Terminal Buffering

ˇ Data Communications

ˇ Peripheral Buffering

ˇ Line Printer Input Buffers

ˇ Auto-Dialers

ˇ CRT Buffer Memories

ˇ Radar Data Acquisition

Description

The 'HC40105 and 'HCT40105 are high-speed silicon-gate
CMOS devices that are compatible, except for "shift-out"
circuitry, with the CD40105B. They are low-power first-in-out
(FIFO) "elastic" storage registers that can store 16 four-bit
words. The 40105 is capable of handling input and output
data at different shifting rates. This feature makes it
particularly useful as a buffer between asynchronous
systems.

Each work position in the register is clocked by a control flip-
flop, which stores a marker bit. A "1" signifies that the posi-
tion's data is filled and a "0" denotes a vacancy in that posi-
tion. The control flip-flop detects the state of the preceding
flip-flop and communicates its own status to the succeeding
flip-flop. When a control flip-flop is in the "0" state and sees a
"1" in the preceeding flip-flop, it generates a clock pulse that
transfers data from the preceding four data latches into its
own four data latches and resets the preceding flip-flop to
"0". The first and last control flip-flops have buffered outputs.
Since all empty locations "bubble" automatically to the input
end, and all valid data ripple through to the output end, the
status of the first control flip-flop (DATA-IN READY) indicates
if the FIFO is full, and the status of the last flip-flop (DATA-
OUT READY) indicates if the FIFO contains data. As the
earliest data are removed from the bottom of the data stack
(the output end), all data entered later will automatically
propagate (ripple) toward the output.

Ordering Information

PART NUMBER

TEMP. RANGE (

PACKAGE

CD54HC40105F3A

-55 to 125

16 Ld CERDIP

CD54HCT40105F3A

-55 to 125

16 Ld CERDIP

CD74HC40105E

-55 to 125

16 Ld PDIP

CD74HC40105M

-55 to 125

16 Ld SOIC

CD74HC40105MT

-55 to 125

16 Ld SOIC

CD74HC40105M96

-55 to 125

16 Ld SOIC

CD74HCT40105E

-55 to 125

16 Ld PDIP

CD74HCT40105M

-55 to 125

16 Ld SOIC

CD74HCT40105MT

-55 to 125

16 Ld SOIC

CD74HCT40105M96

-55 to 125

16 Ld SOIC

NOTE: When ordering, use the entire part number. The suffix 96
denotes tape and reel. The suffix T denotes a small-quantity reel
of 250.

February 1998 - Revised October 2003

CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.

2003, Texas Instruments Incorporated

CD54HC40105, CD74HC40105,

CD54HCT40105, CD74HCT40105

High-Speed CMOS Logic

4-Bit x 16-Word FIFO Register

[ /Title
(CD74
HC401
05,
CD74
HCT40
105)
/Sub-
ject
(High
Speed
CMOS

Pinout

CD54HC40105, CD54HCT40105

(CERDIP)

CD74HC40105, CD74HCT40105

(PDIP, SOIC)

TOP VIEW

Loading Data

Data can be entered whenever the DATA-IN READY (DIR)
flag is high, by a low to high transition on the SHIFT-IN (SI)
input. This input must go low momentarily before the next
word is accepted by the FIFO. The DIR flag will go low
momentarily, until the data have been transferred to the sec-
ond location. The flag will remain low when all 16-word loca-
tions are filled with valid data, and further pulses on the SI
input will be ignored until DIR goes high.

Unloading Data

As soon as the first word has rippled to the output, the data-
out ready output (DOR) goes HIGH and data of the first word
is available on the outputs. Data of other words can be
removed by a negative-going transition on the shift-out input
(SO). This negative-going transition causes the DOR signal
to go LOW while the next word moves to the output. As long
as valid data is available in the FIFO, the DOR signal will go
high again, signifying that the next word is ready at the
output. When the FIFO is empty, DOR will remain LOW, and
any further commands will be ignored until a "1" marker
ripples down to the last control register and DOR goes
HIGH. If during unloading SI is HIGH, (FIFO is full) data on
the data input of the FIFO is entered in the first location.

Master Reset

A high on the MASTER RESET (MR) sets all the control
logic marker bits to "0". DOR goes low and DIR goes high.
The contents of the data register are not changed, only
declared invalid, and will be superseded when the first word
is loaded. Thus, MR does not clear data within the register
but only the control logic. If the shift-in flag (SI) is HIGH
during the master reset pulse, data present at the input (D0
to D3) are immediately moved into the first location upon
completion of the reset process.

Three-State Outputs

In order to facilitate data busing, three-state outputs (Q0 to
Q3) are provided on the data output lines, while the load
condition of the register can be detected by the state of the
DOR output. A HIGH on the three-state control flag (output
enable input OE) forces the outputs into the high-impedance
OFF-state mode. Note that the shift-out signal, unlike that in
the CD40105B, is independent of the three-state output
control. In the CD40105B, the three-state control must not
be shifted from High to Low when the shift-out signal is Low
(data loss would occur). In the high-speed CMOS version
this restriction has been eliminated.

Cascading

The 40105 can be cascaded to form longer registers simply
by connecting the DIR to SO and DOR to SI. In the cascaded
mode, a MASTER RESET pulse must be applied after the
supply voltage is turned on. For words wider than four bits, the
DIR and the DOR outputs must be gated together with AND
gates. Their outputs drive the SI and SO inputs in parallel, if
expanding is done in both directions (see Figures 12 and 13).

Functional Diagram

THREE-STATE

DIR

GND

DOR

CONTROL

STATE

CONTROL

SHIFT OUT

MASTER

SHIFT IN

RESET

DATA-OUT

DATA-IN

READY

GND = 8
V

= 16

THREE-

CD54HC40105, CD74HC40105, CD54HCT40105, CD74HCT40105

Absolute Maximum Ratings

Thermal Information

DC Supply Voltage, V

. . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V

DC Input Diode Current, I

For V

< -0.5V or V

> V

+ 0.5V

. . . . . . . . . . . . . . . . . . . . . .ą

20mA

DC Output Diode Current, I

For V

< -0.5V or V

> V

+ 0.5V

. . . . . . . . . . . . . . . . . . . .ą

20mA

DC Output Source or Sink Current per Output Pin, I

For V

> -0.5V or V

< V

+ 0.5V

. . . . . . . . . . . . . . . . . . . .ą

25mA

DC V

or Ground Current, I

. . . . . . . . . . . . . . . . . . . . . . . . .ą

50mA

Operating Conditions

Temperature Range (T

) . . . . . . . . . . . . . . . . . . . . . -55

C to 125

Supply Voltage Range, V

HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V
HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V

DC Input or Output Voltage, V

, V

. . . . . . . . . . . . . . . . . 0V to V

Input Rise and Fall Time

2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max)
4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max)
6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max)

Thermal Resistance (Typical, Note 1)

(

C/W)

E (PDIP) Package . . . . . . . . . . . . . . . . . . . . . . . . . .

M (SOIC) Package. . . . . . . . . . . . . . . . . . . . . . . . . .

Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 150

Maximum Storage Temperature Range . . . . . . . . . .-65

C to 150

Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300

(SOIC - Lead Tips Only)

CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTE:

1. The package thermal impedance is calculated in accordance with JESD 51-7.

DC Electrical Specifications

PARAMETER

SYMBOL

TEST

CONDITIONS

(V)

-40

C TO 85

C -55

C TO 125

UNITS

(V)

(mA)

MIN

TYP

MAX

MIN

MAX

MIN

MAX

HC TYPES

High Level Input
Voltage

1.5

4.5

3.15

4.2

Low Level Input
Voltage

0.5

4.5

1.35

1.8

High Level Output
Voltage
CMOS Loads

or V

-0.02

1.9

-0.02

4.5

4.4

-0.02

5.9

High Level Output
Voltage
TTL Loads

-4

4.5

3.98

3.84

3.7

-5.2

5.48

5.34

5.2

Low Level Output
Voltage
CMOS Loads

or V

0.02

0.1

0.02

4.5

0.1

0.02

0.1

Low Level Output
Voltage
TTL Loads

4.5

0.26

0.33

0.4

5.2

0.26

0.33

0.4

Input Leakage
Current

GND

0.1

Quiescent Device
Current

GND

160

CD54HC40105, CD74HC40105, CD54HCT40105, CD74HCT40105

Part Number CD74HCT40105