CD4066B
CMOS QUAD BILATERAL SWITCH
SCHS051D NOVEMBER 1998 REVISED SEPTEMBER 2003
1
POST OFFICE BOX 655303
·
DALLAS, TEXAS 75265
D
15-V Digital or
±
7.5-V Peak-to-Peak
Switching
D
125-
Typical On-State Resistance for 15-V
Operation
D
Switch On-State Resistance Matched to
Within 5
Over 15-V Signal-Input Range
D
On-State Resistance Flat Over Full
Peak-to-Peak Signal Range
D
High On/Off Output-Voltage Ratio: 80 dB
Typical at f
is
= 10 kHz, R
L
= 1 k
D
High Degree of Linearity: <0.5% Distortion
Typical at f
is
= 1 kHz, V
is
= 5 V p-p,
V
DD
V
SS
10 V, R
L
= 10 k
D
Extremely Low Off-State Switch Leakage,
Resulting in Very Low Offset Current and
High Effective Off-State Resistance: 10 pA
Typical at V
DD
V
SS
= 10 V, T
A
= 25
°
C
D
Extremely High Control Input Impedance
(Control Circuit Isolated From Signal
Circuit): 10
12
Typical
D
Low Crosstalk Between Switches: 50 dB
Typical at f
is
= 8 MHz, R
L
= 1 k
D
Matched Control-Input to Signal-Output
Capacitance: Reduces Output Signal
Transients
D
Frequency Response, Switch On = 40 MHz
Typical
D
100% Tested for Quiescent Current at 20 V
D
5-V, 10-V, and 15-V Parametric Ratings
D
Meets All Requirements of JEDEC Tentative
Standard No. 13-B, Standard Specifications
for Description of "B" Series CMOS
Devices
D
Applications:
Analog Signal Switching/Multiplexing:
Signal Gating, Modulator, Squelch
Control, Demodulator, Chopper,
Commutating Switch
Digital Signal Switching/Multiplexing
Transmission-Gate Logic Implementation
Analog-to-Digital and Digital-to-Analog
Conversion
Digital Control of Frequency, Impedance,
Phase, and Analog-Signal Gain
description/ordering information
The CD4066B is a quad bilateral switch intended for the transmission or multiplexing of analog or digital signals.
It is pin-for-pin compatible with the CD4016B, but exhibits a much lower on-state resistance. In addition, the
on-state resistance is relatively constant over the full signal-input range.
The CD4066B consists of four bilateral switches, each with independent controls. Both the p and the n devices
in a given switch are biased on or off simultaneously by the control signal. As shown in Figure 1, the well of the
n-channel device on each switch is tied to either the input (when the switch is on) or to V
SS
(when the switch
is off). This configuration eliminates the variation of the switch-transistor threshold voltage with input signal and,
thus, keeps the on-state resistance low over the full operating-signal range.
The advantages over single-channel switches include peak input-signal voltage swings equal to the full supply
voltage and more constant on-state impedance over the input-signal range. However, for sample-and-hold
applications, the CD4016B is recommended.
Copyright
2003, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
1
2
3
4
5
6
7
14
13
12
11
10
9
8
SIG A IN/OUT
SIG A OUT/IN
SIG B OUT/IN
SIG B IN/OUT
CONTROL B
CONTROL C
V
SS
V
DD
CONTROL A
CONTROL D
SIG D IN/OUT
SIG D OUT/IN
SIG C OUT/IN
SIG C IN/OUT
E, F, M, NS, OR PW PACKAGE
(TOP VIEW)
CD4066B
CMOS QUAD BILATERAL SWITCH
SCHS051D NOVEMBER 1998 REVISED SEPTEMBER 2003
2
POST OFFICE BOX 655303
·
DALLAS, TEXAS 75265
description/ordering information (continued)
ORDERING INFORMATION
TA
PACKAGE
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
55 C to 125 C
CDIP F
Tube of 25
CD4066BF3A
CD4066BF3A
55 C to 125 C
PDIP E
Tube of 25
CD4066BE
CD4066BE
55 C to 125 C
SOIC M
Tube of 50
CD4066BM
CD4066BM
55
°
C to 125
°
C
SOIC M
Reel of 2500
CD4066BM96
CD4066BM
55
°
C to 125
°
C
Reel of 250
CD4066BMT
SOP NS
Reel of 2000
CD4066BNSR
CD4066B
TSSOP PW
Tube of 90
CD4066BPW
CM066B
TSSOP PW
Reel of 2000
CD4066BPWR
CM066B
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design
guidelines are available at www.ti.com/sc/package.
All control inputs are protected by the CMOS protection network.
NOTES: A. All p substrates are connected to VDD.
B. Normal operation control-line biasing: switch on (logic 1), VC = VDD; switch off (logic 0), VC = VSS
C. Signal-level range: VSS
Vis
VDD
Control
VC
VDD
VSS
VSS
n
n
p
Out
Vos
Control
Switch
In
92CS-29113
n
p
Vis
Figure 1. Schematic Diagram of One-of-Four Identical Switches and Associated Control Circuitry
CD4066B
CMOS QUAD BILATERAL SWITCH
SCHS051D NOVEMBER 1998 REVISED SEPTEMBER 2003
3
POST OFFICE BOX 655303
·
DALLAS, TEXAS 75265
absolute maximum ratings over operating free-air temperature (unless otherwise noted)
DC supply-voltage range, V
DD
(voltages referenced to V
SS
terminal)
0.5 V to 20 V
. . . . . . . . . . . . . . . . . . . .
Input voltage range, V
is
(all inputs)
0.5 V to V
DD
+
0.5 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DC input current, I
IN
(any one input)
±
10 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package thermal impedance,
JA
(see Note 1): E package
80
°
C/W
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
M package
86
°
C/W
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
NS package
76
°
C/W
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PW package
113
°
C/W
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Lead temperature (during soldering):
At distance 1/16
±
1/32 inch (1,59
±
0,79 mm) from case for 10 s max
265
°
C
. . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, T
stg
65
°
C to 150
°
C
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: The package thermal impedance is calculated in accordance with JESD 51-7.
recommended operating conditions
MIN
MAX
UNIT
VDD
Supply voltage
3
18
V
TA
Operating free-air temperature
55
125
°
C
CD4066B
CMOS QUAD BILATERAL SWITCH
SCHS051D NOVEMBER 1998 REVISED SEPTEMBER 2003
4
POST OFFICE BOX 655303
·
DALLAS, TEXAS 75265
electrical characteristics
PARAMETER
TEST CONDITIONS
LIMITS AT INDICATED TEMPERATURES
UNIT
PARAMETER
TEST CONDITIONS
VIN
VDD
55
°
C
40
°
C
85
°
C
125
°
C
25
°
C
UNIT
VIN
(V)
VDD
(V)
55
°
C
40
°
C
85
°
C
125
°
C
TYP
MAX
I
Quiescent device
0, 5
5
0.25
0.25
7.5
7.5
0.01
0.25
A
IDD
Quiescent device
0, 10
10
0.5
0.5
15
15
0.01
0.5
µ
A
IDD
Quiescent device
current
0, 15
15
1
1
30
30
0.01
1
µ
A
0, 20
20
5
5
150
150
0.02
5
Signal Inputs (Vis) and Outputs (Vos)
r
On-state resistance
VC = VDD,
RL = 10 k
returned
5
800
850
1200
1300
470
1050
ron
On-state resistance
(max)
RL = 10 k returned
to ,
V
DD
*
V
SS
2
10
310
330
500
550
180
400
to ,
Vis = VSS to VDD
2
15
200
210
300
320
125
240
r
On-state resistance
R = 10 k
V = V
5
15
ron
On-state resistance
difference between
any two switches
RL = 10 k
,
VC = VDD
10
10
on
any two switches
L
C
DD
15
5
THD
Total harmonic
distortion
VC = VDD = 5 V, VSS = 5 V,
Vis(p-p) = 5 V (sine wave centered on 0 V),
RL = 10 k
,
fis = 1-kHz sine wave
0.4
%
3-dB cutoff
frequency
(switch on)
VC = VDD = 5 V, VSS = 5 V, Vis(p-p) = 5 V
(sine wave centered on 0 V), RL = 1 k
40
MHz
50-dB feedthrough
frequency (switch off)
VC = VSS = 5 V, Vis(p-p) = 5 V
(sine wave centered on 0 V), RL = 1 k
1
MHz
Iis
Input/output leakage
current (switch off)
(max)
VC = 0 V, Vis = 18 V, Vos = 0 V;
and
VC = 0 V, Vis = 0 V, Vos = 18 V
18
±
0.1
±
0.1
±
1
±
1
±
105
±
0.1
µ
A
50-dB crosstalk
frequency
VC(A) = VDD = 5 V,
VC(B) = VSS = 5 V,
Vis(A) = 5 Vp-p, 50-
source,
RL = 1 k
8
MHz
t
Propagation delay
RL = 200 k
,
VC = VDD,
VSS = GND, CL = 50 pF,
5
20
40
ns
tpd
Propagation delay
(signal input to
signal output)
VSS = GND, CL = 50 pF,
Vis = 10 V
(square wave centered on 5 V),
10
10
20
ns
signal output)
(square wave centered on 5 V),
tr, tf = 20 ns
15
7
15
Cis
Input capacitance
VDD = 5 V, VC = VSS = 5 V
8
pF
Cos
Output capacitance
VDD = 5 V, VC = VSS = 5 V
8
pF
Cios
Feedthrough
VDD = 5 V, VC = VSS = 5 V
0.5
pF
CD4066B
CMOS QUAD BILATERAL SWITCH
SCHS051D NOVEMBER 1998 REVISED SEPTEMBER 2003
5
POST OFFICE BOX 655303
·
DALLAS, TEXAS 75265
electrical characteristics (continued)
CHARACTERISTIC
TEST CONDITIONS
LIMITS AT INDICATED TEMPERATURES
UNIT
CHARACTERISTIC
TEST CONDITIONS
VDD
55
°
C
40
°
C
85
°
C
125
°
C
25
°
C
UNIT
VDD
(V)
55
°
C
40
°
C
85
°
C
125
°
C
TYP
MAX
Control (VC)
V
Control input,
|Iis| < 10
µ
A,
5
1
1
1
1
1
V
VILC
Control input,
low voltage (max)
|Iis| < 10
µ
A,
Vis = VSS, VOS = VDD, and
V = V
, V
= V
10
2
2
2
2
2
V
ILC
low voltage (max)
is
SS
OS
DD
Vis = VDD, VOS = VSS
15
2
2
2
2
2
V
Control input,
See Figure 6
5
3.5 (MIN)
V
VIHC
Control input,
high voltage
See Figure 6
10
7 (MIN)
V
IHC
high voltage
15
11 (MIN)
IIN
Input current (max)
Vis
VDD, VDD VSS = 18 V,
VCC
VDD VSS
18
±
0.1
±
0.1
±
1
±
1
±
105
±
0.1
µ
A
Crosstalk (control input
to signal output)
VC = 10 V (square wave),
tr, tf = 20 ns, RL = 10 k
10
50
mV
Turn-on and turn-off
VIN = VDD, tr, tf = 20 ns,
5
35
70
ns
Turn-on and turn-off
propagation delay
VIN = VDD, tr, tf = 20 ns,
CL = 50 pF, RL = 1 k
10
20
40
ns
propagation delay
CL = 50 pF, RL = 1 k
15
15
30
Maximum control input
Vis = VDD, VSS = GND,
RL = 1 k
to GND, CL = 50 pF,
5
6
MHz
Maximum control input
repetition rate
RL = 1 k
to GND, CL = 50 pF,
VC = 10 V (square wave
centered on 5 V), tr, tf = 20 ns,
10
9
MHz
repetition rate
centered on 5 V), tr, tf = 20 ns,
Vos = 1/2 Vos at 1 kHz
15
9.5
CI
Input capacitance
5
7.5
pF
switching characteristics
VDD
SWITCH INPUT
SWITCH
OUTPUT, Vos
VDD
(V)
Vis
(V)
Iis (mA)
OUTPUT, Vos
(V)
(V)
is
(V)
55
°
C
40
°
C
25
°
C
85
°
C
125
°
C
MIN
MAX
5
0
0.64
0.61
0.51
0.42
0.36
0.4
5
5
0.64
0.61
0.51
0.42
0.36
4.6
10
0
1.6
1.5
1.3
1.1
0.9
0.5
10
10
1.6
1.5
1.3
1.1
0.9
9.5
15
0
4.2
4
3.4
2.8
2.4
1.5
15
15
4.2
4
3.4
2.8
2.4
13.5
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