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FEATURES
FUNCTION
APPLICATIONS
DESCRIPTION
1
2
3
4
8
7
6
5
VC1
VC2
VC3
GND
OUT
VDD
CD
VC4
PW PACKAGE
(TOP VIEW)
GND
OUT
VDD
CD
VC4
VC1
VC3
1
2
VC2
3
4
5
6
7
8
DCT PACKAGE
(TOP VIEW)
bq29400, bq29400A
bq29401, bq29405
SLUS568B JULY 2003 REVISED NOVEMBER 2004
VOLTAGE PROTECTION FOR 2-, 3-, OR 4-CELL Lion BATTERIES
(2
ND
PROTECTION)
·
2-, 3-, or 4-Cell Secondary Protection
Each cell in a multiple cell pack is compared to an
internal reference voltage. If one cell reaches an
·
Low Power Consumption I
CC
< 2 µA
overvoltage condition, the protection sequence be-
[VCELL
(ALL)
< V
(PROTECT)
]
gins. The bq2940x device starts charging an external
·
High Accuracy Over Sense Voltage:
capacitor through the CD pin. When the CD pin
bq29400: 4.35 V
±
25 mV
voltage reaches 1.2 V, the OUT pin changes from a
low level to a high level.
bq29400A: 4.40 V
±
25 mV
bq29401: 4.45 V
±
25 mV
bq29405: 4.65 V
±
25 mV
·
Prefixed Protection Threshold Voltage
·
Programmable Delay Time
·
High Power Supply Ripple Rejection
·
Stable During Pulse Charge Operation
·
2
nd
Level Protection in Lion Battery Packs in
Notebook PCs
Portable Instrumentation
Medical and Test Equipment
The bq29400, bq29400A, bq29401, and bq29405 are
BiCMOS secondary protection ICs for 2-, 3-, or 4-cell
Lithium-Ion
battery
packs
that
incorporate
a
high-accuracy precision over voltage detection circuit.
They include a programmable delay circuit for over
voltage detection time.
ORDERING INFORMATION
PACKAGE
T
A
V
(PROTECT)
MSOP (DTC)
SYMBOL
TSSOP (PW)
(1)
SYMBOL
4.35 V
bq29400DCT3
CIQ
bq29400PW
2400
4.40 V
bq29400ADCT3
CIT
Not Available
-
25
°
C to 85
°
C
4.45 V
bq29401DCT3
CIR
bq29401PW
2401
4.65 V
bq29405DCT3
CIS
Not Available
-
(1)
The bq29400, bq29400A, bq29401, and bq29405 are available taped and reeled. Add an R suffix to the device type (e.g.,
bq29400PWR) to order tape and reel version.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Copyright © 20032004, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
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ABSOLUTE MAXIMUM RATINGS
PACKAGE DISSIPATION RATINGS
RECOMMENDED OPERATING CONDITIONS
bq29400, bq29400A
bq29401, bq29405
SLUS568B JULY 2003 REVISED NOVEMBER 2004
These devices have limited built-in ESD protection. The leads should be shorted together or the device
placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.
over operating free-air temperature range unless otherwise noted
(1) (2)
UNIT
Supply voltage range
(VDD)
-0.3 V to 28 V
(VC1, VC2, VC3, VC4)
-0.3 V to 28 V
Input voltage range
(VC1 to VC2, VC2 to VC3, VC3 to VC4, VC4 to GND)
-0.3 V to 8 V
(OUT)
-0.3 V to 28 V
Output voltage range
(CD)
-0.3 V to 28 V
Continuous total power dissipation
See Dissipation Rating Table
Storage temperature range, T
stg
-65
°
C to 150
°
C
Lead temperature (soldering, 10 sec)
300
°
C
(1)
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2)
All voltages are with respect to ground of this device except the differential voltage of VC1-VC2, VC2-VC3, VC3-VC4 and VC4-GND.
T
A
25
°
C
DERATING FACTOR
T
A
= 70
°
C
T
A
= 85
°
C
PACKAGE
POWER RATING
ABOVE T
A
= 25
°
C
POWER RATING
POWER RATING
DCT
412 mW
3.3 mW/
°
C
264 mW
214 mW
PW
525 mW
4.2 mW/
°
C
336 mW
273 mW
MIN
NOM
MAX UNIT
V
DD
Supply Voltage
4.0
25
V
VC1, VC2, VC3, VC4
0
V
DD
V
I
Input voltage range
V
VCn VC(n+1), (n=1, 2, 3 ), VC4-GND
0
5.0
t
d(CD)
Delay time capacitance
0.22
µF
R
IN
Voltage-monitor filter resistance
100
1k
C
IN
Voltage-monitor filter capacitance
0.01
0.1
µF
R
VD
Supply-voltage filter resistance
0
100
C
VD
Supply-voltage filter capacitance
0.1
µF
T
A
Operating ambient temperature range
-25
85
°
C
2
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ELECTRICAL CHARACTERISTICS
1
2
3
4
8
7
6
5
VC1
VC2
VC3
GND
OUT
VDD
CD
VC4
I
CC
I
IN
I
IN
I
IN
bq29400, bq29400A
bq29401, bq29405
SLUS568B JULY 2003 REVISED NOVEMBER 2004
over recommended operating free-air temperature range, T
A
= 25
°
C (unless otherwise noted)
(1)
PARAMETER
TEST CONDITION
MIN
NOM
MAX
UNIT
25
35
V
(OA)
Over voltage detection accuracy
mV
T
A
= 20
°
C to 85
°
C
25
50
bq29400
4.35
bq2940A
4.40
Over voltage detection
V
(PROTECT)
V
voltage
(1)
bq29401
4.45
bq29405
4.65
V
hys
Over voltage detection hysteresis
(1)
300
mV
V2, V3 , VC4 inputVC1 = VC2 = VC3 = VC4 = 3.5 V
I
I
Input current
±
0.3
µA
(see Figure 1)
t
D1
Over voltage detection delay time
CD = 0.22 µF
1.0
1.5
2.0
S
I
(CD_dis)
CD GND clamp current
CD = 1 V
5
12
µA
VC1 = VC2 = VC3 = VC4 = 3.5 V (see Figure 1)
2.0
3.0
I
CC
Supply current
µA
VC1 = VC2 = VC3 = VC4 = 2.3 V (see Figure 1)
1.5
2.5
V
(OUT)
OUT pin drive voltage
VC1 = VC2 = VC3 = VC4 = 4.7 V, IOH = 0 mA
7
V
I
OH
High-level output current
OUT = 3V, VC1 = VC2 = VC3 = VC4 = 4.7 V
1
mA
I
OL
Low-level output current
OUT = 0.1 V VC1 = VC3 = VC4 = 3.5 V
5
µA
(1)
Levels of the over-voltage detection and the hysteresis can be adjusted. For assistance contact Texas Instruments sales representative.
Figure 1. I
CC
, I
IN
Measurement (TSSOP Package)
Terminal Functions
TERMINAL No.
DESCRIPTION
MSOP
TSSOP
NAME
(DTC)
(PW)
8
1
VC1
Sense voltage input for most positive cell
7
2
VC2
Sense voltage input for second most positive cell
6
3
VC3
Sense voltage input for third most positive cell
5
4
GND
Ground pin
4
5
VC4
Sense voltage input for least positive cell
3
6
CD
An external capacitor is connected to determine the programmable delay time
2
7
VDD
Power supply
1
8
OUT
Output
3
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C
IN
C
IN
C
IN
C
IN
R
IN
R
IN
R
IN
R
IN
VC1
VC2
VC3
VC4
GND
1.2 V (TYP)
CD
VDD
OUT
I
CD
= 0.18
µ
A (TYP)
C
VD
C
DELAY
R
VD
OVERVOLTAGE PROTECTION
DELAY TIME CALCULATION
t
d
+
1.2 V
C
(DELAY)
I
CD
C
(DELAY)
+
t
d
I
CD
1.2 V
bq29400, bq29400A
bq29401, bq29405
SLUS568B JULY 2003 REVISED NOVEMBER 2004
FUNCTIONAL BLOCK DIAGRAM
When one of the cell voltages exceeds V
(PROTECT)
, an internal current source begins to charge the capacitor,
C
(DELAY)
, connected to the CD pin. If the voltage at the CD pin, V
CD,
reaches 1.2 V, the OUT pin is activated and
transitions high. An externally connected NCH FET is activiated and blows the external fuse in the positive
battery rail, see Figure 1.
If all cell voltages fall below V
(PROTECT)
before the voltage at pin CD reaches 1.2 V, the delay time does not run
out. An internal switch clamps the CD pin to GND and discharges the capacitor, C
(DELAY)
, and secures the full
delay time for the next occurring overvoltage event.
Once the pin OUT is activated, it transitions back from high to low after all battery cells reach V
(PROTECT)
- V
hys.
The delay time is calculated as follows:
Where I
(CD)
= CD current source = 0.18 µA
4
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V
(PROTECT)
Cell Voltage
(VCn - VC(n-1),
VC4 - GND)
CD
OUT
1.2 V
t
DELAY
V
(PROTECT)
- V
hys
t
d
= (1.2 V x C
DELAY
)/I
CD
bq29400, bq29400A
bq29401, bq29405
SLUS568B JULY 2003 REVISED NOVEMBER 2004
Figure 2. Timing for Overvoltage Sensing
5
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