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Part Number ADS1242

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PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
24-Bit
ANALOG-TO-DIGITAL CONVERTER
FEATURES
q
24 BITS NO MISSING CODES
q
SIMULTANEOUS 50Hz AND 60Hz REJECTION
(­90dB MINIMUM)
q
0.0015% INL
q
21 BITS EFFECTIVE RESOLUTION
(PGA = 1), 19 BITS (PGA = 128)
q
PGA GAINS FROM 1 TO 128
q
SINGLE-CYCLE SETTLING
q
PROGRAMMABLE DATA OUTPUT RATES
q
EXTERNAL DIFFERENTIAL REFERENCE
OF 0.1V TO 5V
q
ON-CHIP CALIBRATION
q
SPITM COMPATIBLE
q
2.7V TO 5.25V SUPPLY RANGE
q
600
µ
W POWER CONSUMPTION
q
UP TO EIGHT INPUT CHANNELS
q
UP TO EIGHT DATA I/O
DESCRIPTION
The ADS1242 and ADS1243 are precision, wide dynamic
range, delta-sigma, analog-to-digital (A/D) converters with
24-bit resolution operating from 2.7V to 5.25V supplies.
These delta-sigma, A/D converters provide up to 24 bits of no
missing code performance and effective resolution of 21 bits.
The input channels are multiplexed. Internal buffering can be
selected to provide a very high input impedance for direct
connection to transducers or low-level voltage signals. Burn-
out current sources are provided that allow for the detection
of an open or shorted sensor. An 8-bit digital-to-analog
converter (DAC) provides an offset correction with a range of
50% of the FSR (Full-Scale Range).
The Programmable Gain Amplifier (PGA) provides selectable
gains of 1 to 128 with an effective resolution of 19 bits at a gain
of 128. The A/D conversion is accomplished with a second-order
delta-sigma modulator and programmable FIR filter that pro-
vides a simultaneous 50Hz and 60Hz notch. The reference input
is differential and can be used for ratiometric conversion.
The serial interface is SPI compatible. Up to eight bits of data
I/O are also provided that can be used for input or output. The
ADS1242 and ADS1243 are designed for high-resolution
measurement applications in smart transmitters, industrial
process control, weight scales, chromatography, and portable
instrumentation.
APPLICATIONS
q
INDUSTRIAL PROCESS CONTROL
q
LIQUID /GAS CHROMATOGRAPHY
q
BLOOD ANALYSIS
q
SMART TRANSMITTERS
q
PORTABLE INSTRUMENTATION
q
WEIGHT SCALES
ADS1242
ADS1243
SBAS235B ­ DECEMBER 2001 ­ OCTOBER 2004
www.ti.com
Copyright © 2001-2004, Texas Instruments Incorporated
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
®
ADS1
243
®
ADS1
242
BUF
PGA
A = 1:128
+
Clock Generator
Serial Interface
2nd-Order
Modulator
GND
V
DD
IN+
IN­
V
REF+
V
REF­
X
IN
X
OUT
PDWN
DRDY
SCLK
D
IN
D
OUT
CS
MUX
A
IN
0/D0
A
IN
1/D1
A
IN
2/D2
A
IN
3/D3
A
IN
4/D4
A
IN
5/D5
A
IN
6/D6
A
IN
7/D7
Controller
Registers
Digital
Filter
2
µ
A
V
DD
Offset
DAC
GND
2
µ
A
ADS1243
Only
All trademarks are the property of their respective owners.
ADS1242, 1243
2
SBAS235B
www.ti.com
DIGITAL CHARACTERISTICS: T
MIN
to T
MAX
, V
DD
2.7V to 5.25V
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Digital Input/Output
Logic Family
CMOS
Logic Level: V
IH
0.8 · V
DD
V
DD
V
V
IL
(1)
GND
0.2 · V
DD
V
V
OH
I
OH
= 1mA
V
DD
­ 0.4
V
V
OL
I
OL
= 1mA
GND
GND + 0.4
V
Input Leakage: I
IH
V
I
= V
DD
10
µ
A
I
IL
V
I
= 0
­10
µ
A
Master Clock Rate: f
OSC
1
5
MHz
Master Clock Period: t
OSC
1/f
OSC
200
1000
ns
NOTE: (1) V
IL
for X
IN
is GND to GND + 0.05V.
ELECTROSTATIC
DISCHARGE SENSITIVITY
This integrated circuit can be damaged by ESD. Texas Instru-
ments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling
and installation procedures can cause damage.
ESD damage can range from subtle performance degradation
to complete device failure. Precision integrated circuits may be
more susceptible to damage because very small parametric
changes could cause the device not to meet its published
specifications.
V
DD
to GND ........................................................................... ­0.3V to +6V
Input Current ............................................................... 100mA, Momentary
Input Current ................................................................. 10mA, Continuous
A
IN
.................................................................... GND ­ 0.5V to V
DD
+ 0.5V
Digital Input Voltage to GND ...................................... ­0.3V to V
DD
+ 0.3V
Digital Output Voltage to GND ................................... ­0.3V to V
DD
+ 0.3V
Maximum Junction Temperature ................................................... +150
°
C
Operating Temperature Range ......................................... ­40
°
C to +85
°
C
Storage Temperature Range .......................................... ­60
°
C to +100
°
C
Lead Temperature (soldering, 10s) .............................................. +300
°
C
NOTE: (1) Stresses above those listed under "Absolute Maximum Ratings" may
cause permanent damage to the device. Exposure to absolute maximum
conditions for extended periods may affect device reliability.
ABSOLUTE MAXIMUM RATINGS
(1)
SPECIFIED
PACKAGE
TEMPERATURE
PACKAGE
ORDERING
TRANSPORT
PRODUCT
PACKAGE-LEAD
DESIGNATOR
RANGE
MARKING
NUMBER
(2)
MEDIA, QUANTITY
ADS1242
TSSOP-16
PW
­40
°
C to +85
°
C
ADS1242
ADS1242IPWT
Tape and Reel, 250
"
"
"
"
"
ADS1242IPWR
Tape and Reel, 2500
ADS1243
TSSOP-20
PW
­40
°
C to +85
°
C
ADS1243
ADS1243IPWT
Tape and Reel, 250
"
"
"
"
"
ADS1243IPWR
Tape and Reel, 2500
NOTES: (1) For the most current package and ordering information, see the Package Option Addendum located at the end of this data sheet.
(2) The ordering number contains grade, temperature range, package, and transport media information. Ordering the ADS1242IPWT will get a single
250-piece tape and reel of the ADS1242, Industrial Temperature Range device in a PW package.
PACKAGE/ORDERING INFORMATION
(1)
DEMO BOARD ORDERING INFORMATION
PRODUCT
DESCRIPTION
ADS1241-EVM
ADS1241 Evaluation Module
ADS1242, 1243
3
SBAS235B
www.ti.com
ELECTRICAL CHARACTERISTICS: V
DD
= 5V
All specifications T
MIN
to T
MAX
, V
DD
= +5V, f
MOD
= 19.2kHz, PGA = 1, Buffer ON, f
DATA
= 15Hz, V
REF
(REF IN+) ­ (REF IN­) = +2.5V, unless otherwise specified.
ADS1242
ADS1243
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
ANALOG INPUT (A
IN
0 ­ A
IN
7)
Analog Input Range
Buffer OFF
GND ­ 0.1
V
DD
+ 0.1
V
Buffer ON
GND + 0.05
V
DD
­ 1.5
V
Full-Scale Input Range
(In+) ­ (In­), See Block Diagram, RANGE = 0
±
V
REF
/PGA
V
RANGE = 1
±
V
REF
/(2 · PGA)
V
Differential Input Impedance
Buffer OFF
5/PGA
M
Buffer ON
5
G
Bandwidth
f
DATA
= 3.75Hz
­3dB
1.65
Hz
f
DATA
= 7.50Hz
­3dB
3.44
Hz
f
DATA
= 15.00Hz
­3dB
14.6
Hz
Programmable Gain Amplifier
User-Selectable Gain Ranges
1
128
Input Capacitance
9
pF
Input Leakage Current
Modulator OFF, T = 25
°
C
5
pA
Burnout Current Sources
2
µ
A
OFFSET DAC
Offset DAC Range
RANGE = 0
±
V
REF
/(2 · PGA)
V
RANGE = 1
±
V
REF
/(4 · PGA)
V
Offset DAC Monotonicity
8
Bits
Offset DAC Gain Error
±
10
%
Offset DAC Gain Error Drift
1
ppm/
°
C
SYSTEM PERFORMANCE
Resolution
No Missing Codes
24
Bits
Integral Nonlinearity
End Point Fit
±
0.0015
% of FS
Offset Error
(1)
7.5
ppm of FS
Offset Drift
(1)
0.02
ppm of FS/
°
C
Gain Error
(1)
0.005
%
Gain Error Drift
(1)
0.5
ppm/
°
C
Common-Mode Rejection
at DC
100
dB
f
CM
= 60Hz, f
DATA
= 15Hz
130
dB
f
CM
= 50Hz, f
DATA
= 15Hz
120
dB
Normal-Mode Rejection
f
SIG
= 50Hz, f
DATA
= 15Hz
100
dB
f
SIG
= 60Hz, f
DATA
= 15Hz
100
dB
Output Noise
See Typical Characteristics
Power-Supply Rejection
at DC, dB = ­20 log(
V
OUT
/V
DD
)
(2)
80
95
dB
VOLTAGE REFERENCE INPUT
Reference Input Range
REF IN+, REF IN­
0
V
DD
V
V
REF
V
REF
(REF IN+) ­ (REF IN­), RANGE = 0
0.1
2.5
2.6
V
RANGE = 1
0.1
V
DD
V
Common-Mode Rejection
at DC
120
dB
Common-Mode Rejection
f
VREFCM
= 60Hz, f
DATA
= 15Hz
120
dB
Bias Current
(3)
V
REF
= 2.5V
1.3
µ
A
POWER-SUPPLY REQUIREMENTS
Power-Supply Voltage
V
DD
4.75
5.25
V
Current
PGA = 1, Buffer OFF
240
375
µ
A
PGA = 128, Buffer OFF
450
800
µ
A
PGA = 1, Buffer ON
290
425
µ
A
PGA = 128, Buffer ON
960
1400
µ
A
SLEEP Mode
60
µ
A
Read Data Continuous Mode
230
µ
A
PDWN
0.5
nA
Power Dissipation
PGA = 1, Buffer OFF
1.2
1.9
mW
TEMPERATURE RANGE
Operating
­40
+85
°
C
Storage
­60
+100
°
C
NOTES: (1) Calibration can minimize these errors. (2)
V
OUT
is a change in digital result. (3) 12pF switched capacitor at f
SAMP
clock frequency.
ADS1242, 1243
4
SBAS235B
www.ti.com
ELECTRICAL CHARACTERISTICS: V
DD
= 3V
All specifications T
MIN
to T
MAX
, V
DD
= +3V, f
MOD
= 19.2kHz, PGA = 1, Buffer ON, f
DATA
= 15Hz, V
REF
(REF IN+) ­ (REF IN­) = +1.25V, unless otherwise specified.
ADS1242
ADS1243
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
ANALOG INPUT (A
IN
0 ­ A
IN
7)
Analog Input Range
Buffer OFF
GND ­ 0.1
V
DD
+ 0.1
V
Buffer ON
GND + 0.05
V
DD
­ 1.5
V
Full-Scale Input Voltage Range
(In+) ­ (In­) See Block Diagram, RANGE = 0
±
V
REF
/PGA
V
RANGE = 1
±
V
REF
/(2 · PGA)
V
Input Impedance
Buffer OFF
5/PGA
M
Buffer ON
5
G
Bandwidth
f
DATA
= 3.75Hz
­3dB
1.65
Hz
f
DATA
= 7.50Hz
­3dB
3.44
Hz
f
DATA
= 15.00Hz
­3dB
14.6
Hz
Programmable Gain Amplifier
User-Selectable Gain Ranges
1
128
Input Capacitance
9
pF
Input Leakage Current
Modulator OFF, T = 25
°
C
5
pA
Burnout Current Sources
2
µ
A
OFFSET DAC
Offset DAC Range
RANGE = 0
±
V
REF
/(2 · PGA)
V
RANGE = 1
±
V
REF
/(4 · PGA)
V
Offset DAC Monotonicity
8
Bits
Offset DAC Gain Error
±
10
%
Offset DAC Gain Error Drift
2
ppm/
°
C
SYSTEM PERFORMANCE
Resolution
No Missing Codes
24
Bits
Integral Nonlinearity
End Point Fit
±
0.0015
% of FS
Offset Error
(1)
15
ppm of FS
Offset Drift
(1)
0.04
ppm of FS/
°
C
Gain Error
(1)
0.01
%
Gain Error Drift
(1)
1.0
ppm/
°
C
Common-Mode Rejection
at DC
100
dB
f
CM
= 60Hz, f
DATA
= 15Hz
130
dB
f
CM
= 50Hz, f
DATA
= 15Hz
120
dB
Normal-Mode Rejection
f
SIG
= 50Hz, f
DATA
= 15Hz
100
dB
f
SIG
= 60Hz, f
DATA
= 15Hz
100
dB
Output Noise
See Typical Characteristics
Power-Supply Rejection
at DC, dB = ­20 log(
V
OUT
/V
DD
)
(2)
75
90
dB
VOLTAGE REFERENCE INPUT
Reference Input Range
REF IN+, REF IN­
0
V
DD
V
V
REF
V
REF
(REF IN+) ­ (REF IN­), RANGE = 0
0.1
1.25
1.30
V
RANGE = 1
0.1
2.5
2.6
V
Common-Mode Rejection
at DC
120
dB
Common-Mode Rejection
f
VREFCM
= 60Hz, f
DATA
= 15Hz
120
dB
Bias Current
(3)
V
REF
= 1.25
0.65
µ
A
POWER-SUPPLY REQUIREMENTS
Power-Supply Voltage
V
DD
2.7
3.3
V
Current
PGA = 1, Buffer OFF
190
375
µ
A
PGA = 128, Buffer OFF
460
700
µ
A
PGA = 1, Buffer ON
240
375
µ
A
PGA = 128, Buffer ON
870
1325
µ
A
SLEEP Mode
75
µ
A
Read Data Continuous Mode
113
µ
A
PDWN = 0
0.5
nA
Power Dissipation
PGA = 1, Buffer OFF
0.6
1.2
mW
TEMPERATURE RANGE
Operating
­40
+85
°
C
Storage
­60
+100
°
C
NOTES: (1) Calibration can minimize these errors. (2)
V
OUT
is a change in digital result. (3) 12pF switched capacitor at f
SAMP
clock frequency.
ADS1242, 1243
5
SBAS235B
www.ti.com
PIN CONFIGURATION (ADS1242)
PIN
NUMBER
NAME
DESCRIPTION
1
V
DD
Power Supply
2
X
IN
Clock Input
3
X
OUT
Clock Output, used with crystal or ceramic
resonator.
4
PDWN
Active LOW. Power Down. The power down func-
tion shuts down the analog and digital circuits.
5
V
REF+
Positive Differential Reference Input
6
V
REF­
Negative Differential Reference Input
7
A
IN
0/D0
Analog Input 0/Data I/O 0
8
A
IN
1/D1
Analog Input 1/Data I/O 1
9
A
IN
2/D2
Analog Input 2/Data I/O 2
10
A
IN
3/D3
Analog Input 3/Data I/O 3
11
GND
Ground
12
CS
Active LOW, Chip Select
13
D
IN
Serial Data Input, Schmitt Trigger
14
D
OUT
Serial Data Output
15
SCLK
Serial Clock, Schmitt Trigger
16
DRDY
Active LOW, Data Ready
PIN DESCRIPTIONS (ADS1242)
PIN CONFIGURATION (ADS1243)
PIN
NUMBER
NAME
DESCRIPTION
1
V
DD
Power Supply
2
X
IN
Clock Input
3
X
OUT
Clock Output, used with crystal or ceramic
resonator.
4
PDWN
Active LOW. Power Down. The power down func-
tion shuts down the analog and digital circuits.
5
V
REF+
Positive Differential Reference Input
6
V
REF­
Negative Differential Reference Input
7
A
IN
0/D0
Analog Input 0/Data I/O 0
8
A
IN
1/D1
Analog Input 1/Data I/O 1
9
A
IN
4/D4
Analog Input 4/Data I/O 4
10
A
IN
5/D5
Analog Input 5/Data I/O 5
11
A
IN
6/D6
Analog Input 6/Data I/O 6
12
A
IN
7/D7
Analog Input 7/Data I/O 7
13
A
IN
2/D2
Analog Input 2/Data I/O 2
14
A
IN
3/D3
Analog Input 3/Data I/O 3
15
GND
Ground
16
CS
Active LOW, Chip Select
17
D
IN
Serial Data Input, Schmitt Trigger
18
D
OUT
Serial Data Output
19
SCLK
Serial Clock, Schmitt Trigger
20
DRDY
Active LOW, Data Ready
PIN DESCRIPTIONS (ADS1243)
Top View
TSSOP
Top View
TSSOP
ADS1242
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
V
DD
X
IN
X
OUT
PDWN
V
REF+
V
REF­
A
IN
0/D0
A
IN
1/D1
DRDY
SCLK
D
OUT
D
IN
CS
GND
A
IN
3/D3
A
IN
2/D2
ADS1243
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
V
DD
X
IN
X
OUT
PDWN
V
REF+
V
REF­
A
IN
0/D0
A
IN
1/D1
A
IN
4/D4
A
IN
5/D5
DRDY
SCLK
D
OUT
D
IN
CS
GND
A
IN
3/D3
A
IN
2/D2
A
IN
7/D7
A
IN
6/D6
ADS1242, 1243
6
SBAS235B
www.ti.com
SPEC
DESCRIPTION
MIN
MAX
UNITS
t
1
SCLK Period
4
t
OSC
Periods
3
DRDY Periods
t
2
SCLK Pulse Width, HIGH and LOW
200
ns
t
3
CS low to first SCLK Edge; Setup Time
(2)
0
ns
t
4
D
IN
Valid to SCLK Edge; Setup Time
50
ns
t
5
Valid D
IN
to SCLK Edge; Hold Time
50
ns
t
6
Delay between last SCLK edge for D
IN
and first SCLK edge for D
OUT
:
RDATA, RDATAC, RREG, WREG
50
t
OSC
Periods
t
7
(1)
SCLK Edge to Valid New D
OUT
50
ns
t
8
(1)
SCLK Edge to D
OUT
, Hold Time
0
ns
t
9
Last SCLK Edge to D
OUT
Tri-State
6
10
t
OSC
Periods
NOTE: D
OUT
goes tri-state immediately when CS goes HIGH.
t
10
CS LOW time after final SCLK edge.
0
ns
t
11
Final SCLK edge of one command until first edge SCLK
of next command:
RREG, WREG, DSYNC, SLEEP, RDATA, RDATAC, STOPC
4
t
OSC
Periods
SELFGCAL, SELFOCAL, SYSOCAL, SYSGCAL
2
DRDY Periods
SELFCAL
4
DRDY Periods
RESET (also SCLK Reset)
16
t
OSC
Periods
t
16
Pulse Width
4
t
OSC
Periods
t
17
Allowed analog input change for next valid conversion.
5000
t
OSC
Periods
t
18
DOR update, DOR data not valid.
4
t
OSC
Periods
t
19
First SCLK after DRDY goes LOW:
RDATAC Mode
10
t
OSC
Periods
Any other mode
0
t
OSC
Periods
NOTES: (1) Load = 20pF
10k
to GND.
(2) CS may be tied LOW.
TIMING DIAGRAMS
TIMING CHARACTERISTICS TABLES
t
4
MSB
(Command or Command and Data)
LSB
t
5
t
1
t
3
CS
SCLK
(POL = 0)
D
IN
D
OUT
NOTE: (1) Bit order = 0.
SCLK Reset Waveform
t
7
MSB
(1)
LSB
(1)
t
8
t
10
t
2
t
2
t
11
t
6
t
9
t
12
t
14
t
15
t
13
t
13
SCLK
ADS1242 or ADS1243
Resets On
Falling Edge
300 · t
OSC
< t
12
< 500 · t
OSC
t
13
: > 5 · t
OSC
550 · t
OSC
< t
14
< 750 · t
OSC
1050 · t
OSC
< t
15
< 1250 · t
OSC
DIAGRAM 1.
DIAGRAM 2.
t
17
t
18
DRDY
SCLK
t
DATA
t
16
PDWN
t
19
ADS1242, 1243
7
SBAS235B
www.ti.com
TYPICAL CHARACTERISTICS
All specifications, V
DD
= +5V, f
OSC
= 2.4576MHz, PGA = 1, f
DATA
= 15Hz, and V
REF
(REF IN+) ­ (REF IN­) = +2.5V, unless otherwise specified.
21.5
21.0
20.5
20.0
19.5
19.0
18.5
18.0
17.5
17.0
EFFECTIVE NUMBER OF BITS vs PGA SETTING
PGA Setting
1
2
4
8
16
128
64
32
ENOB (rms)
Buffer OFF
DR = 10
DR = 01
DR = 00
22
21
20
19
18
17
16
15
EFFECTIVE NUMBER OF BITS vs PGA SETTING
PGA Setting
ENOB (rms)
1
2
4
8
16
128
64
32
DR = 10
DR = 00
DR = 01
Buffer ON
20.5
20.0
19.5
19.0
18.5
18.0
17.5
17.0
16.5
16.0
EFFECTIVE NUMBER OF BITS vs PGA SETTING
PGA Setting
1
2
4
8
16
64
128
32
ENOB (rms)
Buffer OFF, V
REF
= 1.25V
DR = 10
DR = 00
DR = 01
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
NOISE vs INPUT SIGNAL
V
IN
(V)
­2.5
­1.5
0.5
­0.5
1.5
2.5
Noise (rms, ppm of FS)
140
120
100
80
60
40
20
0
COMMON-MODE REJECTION RATIO
vs FREQUENCY
Frequency of Power Supply (Hz)
1
10
100
1k
10k
100k
CMRR (dB)
Buffer ON
POWER SUPPLY REJECTION RATIO
vs FREQUENCY
Frequency of Power Supply (Hz)
1
10
1k
100
10k
100k
PSRR (dB)
140
120
100
80
60
40
20
0
Buffer ON
ADS1242, 1243
8
SBAS235B
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TYPICAL CHARACTERISTICS
(Cont.)
All specifications, V
DD
= +5V, f
OSC
= 2.4576MHz, PGA = 1, f
DATA
= 15Hz, and V
REF
(REF IN+) ­ (REF IN­) = +2.5V, unless otherwise specified.
50
0
­50
­100
­150
­200
OFFSET vs TEMPERATURE
(Cal at 25
°
C)
Offset (ppm of FS)
PGA1
PGA128
PGA64
Temperature (
°
C)
­50
­30
10
­10
30
50
70
90
PGA16
1.00010
1.00006
1.00002
0.99998
0.99994
0.99990
0.99986
GAIN vs TEMPERATURE
(Cal at 25
°
C)
Temperature (
°
C)
­50
­30
10
­10
30
50
70
90
Gain (Normalized)
10
8
6
4
2
0
­2
­4
­6
­8
­10
INTEGRAL NONLINEARITY vs INPUT SIGNAL
V
IN
(V)
­2.5 ­2.0
­1.0 ­0.5
­1.5
0
0.5
1.0
1.5
2.0
2.5
INL (ppm of FS)
­40
°
C
+25
°
C
+85
°
C
260
250
240
230
220
210
200
190
CURRENT vs TEMPERATURE
(Buffer Off)
Current (
µ
A)
Temperature (
°
C)
­50
­30
10
­10
30
50
70
90
350
300
250
200
150
100
50
0
­50
CURRENT vs VOLTAGE
V
DD
(V)
3.0
3.25
3.5
3.75
4.0
4.25
4.5
4.75
5.0
Current (
µ
A)
Normal
4.91MHz
Normal
2.45MHz
SLEEP
4.91MHz
SLEEP
2.45MHz
Power Down
300
250
200
150
100
50
0
SUPPLY CURRENT vs SUPPLY
V
DD
(V)
3.0
3.5
4.0
4.5
5.0
I
DIGITAL
(
µ
A)
Normal
4.91MHz
Normal
2.45MHz
SLEEP
2.45MHz
Power Down
SLEEP
4.91MHz
ADS1242, 1243
9
SBAS235B
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TYPICAL CHARACTERISTICS
(Cont.)
All specifications, V
DD
= +5V, f
OSC
= 2.4576MHz, PGA = 1, f
DATA
= 15Hz, and V
REF
(REF IN+) ­ (REF IN­) = +2.5V, unless otherwise specified.
3500
3000
2500
2000
1500
1000
500
0
NOISE HISTOGRAM
10k
Readings
V
IN
= 0V
ppm of FS
­3.5 ­3.0
Number of Occurrences
­2.5 ­2.0 ­1.5 ­1 ­0.5 0
0.5 1.0 1.5 2.0 2.5 3.0 3.5
200
170
140
110
80
50
20
­10
­40
­70
­100
OFFSET DAC
OFFSET vs TEMPERATURE
(Cal at 25
°
C)
Offset (ppm of FSR)
Temperature (
°
C)
­50
­30
10
­10
30
50
70
90
1.00020
1.00016
1.00012
1.00008
1.00004
1.00000
0.99996
0.99992
0.99988
0.99984
0.99980
0.99976
OFFSET DAC
GAIN vs TEMPERATURE
(Cal at 25
°
C)
Gain (Normalized)
Temperature (
°
C)
­50
­30
10
­10
30
50
70
90
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
OFFSET DAC
NOISE vs SETTING
Offset DAC Setting
Noise (rms, ppm of FS)
­128
­96
­64
­32
0
32
64
96
128
ADS1242, 1243
10
SBAS235B
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channel. With this method, it is possible to have up to eight
single-ended input channels or four independent differential
input channels for the ADS1243, and four single-ended input
channels or two independent differential input channels for
the ADS1242. Note that A
INCOM
can be treated as an input
channel.
The ADS1242 and ADS1243 feature a single-cycle settling
digital filter that provides valid data on the first conversion
after a new channel selection. In order to minimize the
settling error, synchronize MUX changes to the conversion
beginning, which is indicated by the falling edge of DRDY
.
In
other words, issuing a MUX change through the WREG
command immediately after DRDY goes LOW minimizes the
settling error. Increasing the time between the conversion
beginning (DRDY goes LOW) and the MUX change com-
mand (t
DELAY
) results in a settling error in the conversion
data, as shown in Figure 2.
BURNOUT CURRENT SOURCES
The Burnout Current Sources can be used to detect sensor
short-circuit or open-circuit conditions. Setting the Burnout
Current Sources (BOCS) bit in the SETUP register activates
two 2
µ
A current sources called burnout current sources. One
of the current sources is connected to the converter's nega-
tive input and the other is connected to the converter's
positive input.
Figure 3 shows the situation for an open-circuit sensor. This
is a potential failure mode for many kinds of remotely con-
nected sensors. The current source on the positive input acts
as a pull-up, causing the positive input to go to the positive
analog supply, and the current source on the negative input
acts as a pull-down, causing the negative input to go to
ground. The ADS1242/43 therefore outputs full-scale (7FFFFF
Hex).
OVERVIEW
INPUT MULTIPLEXER
The input multiplexer provides for any combination of differ-
ential inputs to be selected on any of the input channels, as
shown in Figure 1. For example, if A
IN
0 is selected as the
positive differential input channel, any other channel can be
selected as the negative terminal for the differential input
FIGURE 1. Input Multiplexer Configuration.
FIGURE 2. Input Multiplexer Configuration.
A
IN
3/D3
A
IN
4/D4
A
IN
5/D5
A
IN
6/D6
A
IN
0/D0
A
IN
1/D1
A
IN
2/D2
A
IN
7/D7
A
INCOM
Burnout Current Source
Burnout Current Source
GND
V
DD
ADS1243
Only
Input
Buffer
SETTLING ERROR vs DELAY TIME
f
CLK
= 2.4576MHz
Delay Time, t
DELAY
(ms)
Settling Error (%)
2
4
6
8
10
12
14
16
0
10.000000
1.000000
0.100000
0.010000
0.001000
0.000100
0.000010
0.000001
New Conversion Begins,
Complete Previous Conversion
New Conversion Complete
t
DELAY
MSB
LSB
DRDY
DIN
SCLK
(POL = 0)
Previous Conversion Data
ADS1242, 1243
11
SBAS235B
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FIGURE 3. Burnout detection while sensor is open-circuited.
FIGURE 4. Burnout detection while sensor is short-circuited.
SPEED
DR BITS
1st NOTCH
f
OSC
BIT
f
MOD
00
01
10
FREQ.
2.4576MHz
0
19,200Hz
15Hz
7.5Hz
3.75Hz
50/60Hz
1
9,600Hz
7.5Hz
3.75Hz 1.875Hz
25/30Hz
4.9152MHz
0
38,400Hz
30Hz
15Hz
7.5Hz
100/120Hz
1
19,200Hz
15Hz
7.5Hz
3.75Hz
50/60Hz
TABLE I. Output Configuration.
OPEN CIRCUIT
V
DD
V
DD
0V
2
µ
A
2
µ
A
CODE = 0x7FFFFF
H
ADC
SHORT
CIRCUIT
V
DD
V
DD
/2
V
DD
/2
2
µ
A
2
µ
A
CODE
0
ADC
Figure 4 shows a short-circuited sensor. Since the inputs are
shorted and at the same potential, the ADS1242/43 signal
outputs are approximately zero. (Note that the code for
shorted inputs is not exactly zero due to internal series
resistance, low-level noise and other error sources.)
INPUT BUFFER
The input impedance of the ADS1242/43 without the buffer
enabled is approximately 5M
/PGA. For systems requiring
very high input impedance, the ADS1242/43 provides a
chopper-stabilized differential FET-input voltage buffer. When
activated, the buffer raises the ADS1242/43 input impedance
to approximately 5G
.
The buffer's input range is approximately 50mV to
V
DD
­ 1.5V. The buffer's linearity will degrade beyond this
range. Differential signals should be adjusted so that both
signals are within the buffer's input range.
The buffer can be enabled using the BUFEN pin or the
BUFEN bit in the ACR register. The buffer is on when the
BUFEN pin is high and the BUFEN bit is set to one. If the
BUFEN pin is low, the buffer is disabled. If the BUFEN bit is
set to zero, the buffer is also disabled.
The buffer draws additional current when activated. The
current required by the buffer depends on the PGA setting.
When the PGA is set to 1, the buffer uses approximately
50
µ
A; when the PGA is set to 128, the buffer uses approxi-
mately 500
µ
A.
PGA
The Programmable Gain Amplifier (PGA) can be set to gains
of 1, 2, 4, 8, 16, 32, 64, or 128. Using the PGA can improve the
effective resolution of the A/D converter. For instance, with a
PGA of 1 on a 5V full-scale signal, the A/D converter can
resolve down to 1
µ
V. With a PGA of 128 and a full-scale signal
of 39mV, the A/D converter can resolve down to 75nV. V
DD
current increases with PGA settings higher than 4.
OFFSET DAC
The input to the PGA can be shifted by half the full-scale input
range of the PGA using the Offset DAC (ODAC) register. The
ODAC register is an 8-bit value; the MSB is the sign and the
seven LSBs provide the magnitude of the offset. Using the
offset DAC does not reduce the performance of the A/D
converter. For more details on the ODAC in the ADS1242/43,
please refer to TI application report SBAA077 (available
through the TI website).
MODULATOR
The modulator is a single-loop second-order system. The
modulator runs at a clock speed (f
MOD
) that is derived from
the external clock (f
OSC
). The frequency division is deter-
mined by the SPEED bit in the SETUP register, as shown in
Table I.
CALIBRATION
The offset and gain errors can be minimized with calibration.
The ADS1242 and ADS1243 support both self and system
calibration.
Self-calibration of the ADS1242 and ADS1243 corrects inter-
nal offset and gain errors and is handled by three commands:
SELFCAL, SELFGAL, and SELFOCAL. The SELFCAL com-
mand performs both an offset and gain calibration. SELFGCAL
performs a gain calibration and SELFOCAL performs an
offset calibration, each of which takes two t
DATA
periods to
complete. During self-calibration, the ADC inputs are discon-
nected internally from the input pins. The PGA must be set to
1 prior to issuing a SELFCAL or SELFGCAL command. Any
PGA is allowed when issuing a SELFOCAL command. For
ADS1242, 1243
12
SBAS235B
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FIGURE 5. Crystal Connection.
CLOCK
PART
SOURCE
FREQUENCY
C
1
C
2
NUMBER
Crystal
2.4576
0-20pF
0-20pF
ECS, ECSD 2.45 - 32
Crystal
4.9152
0-20pF
0-20pF
ECS, ECSL 4.91
Crystal
4.9152
0-20pF
0-20pF
ECS, ECSD 4.91
Crystal
4.9152
0-20pF
0-20pF
CTS, MP 042 4M9182
TABLE II. Recommended Crystals.
C
1
Crystal
X
IN
X
OUT
C
2
example, if using PGA = 64, first set PGA = 1 and issue
SELFGCAL. Afterwards, set PGA = 64 and issue SELFOCAL.
For operation with a reference voltage greater than
(V
DD
­ 1.5) volts, the buffer must also be turned off during
gain self-calibration to avoid exceeding the buffer input
range.
System calibration corrects both internal and external offset
and gain errors. While performing system calibration, the
appropriate signal must be applied to the inputs. The system
offset calibration command (SYSOCAL) requires a zero input
differential signal (see Table IV, page 18). It then computes
the offset that nullifies the offset in the system. The system
gain calibration command (SYSGCAL) requires a positive
full-scale input signal. It then computes a value to nullify the
gain error in the system. Each of these calibrations takes two
t
DATA
periods
to complete. System gain calibration is recom-
mended for the best gain calibration at higher PGAs.
Calibration should be performed after power on, a change in
temperature, or a change of the PGA. The RANGE bit (ACR bit
2) must be zero during calibration.
Calibration removes the effects of the ODAC; therefore, dis-
able the ODAC during calibration, and enable again after
calibration is complete.
At the completion of calibration, the DRDY signal goes low,
indicating the calibration is finished. The first data after
calibration should be discarded since it may be corrupt from
calibration data remaining in the filter. The second data is
always valid.
EXTERNAL VOLTAGE REFERENCE
The ADS1242 and ADS1243 require an external voltage
reference. The selection for the voltage reference value is
made through the ACR register.
The external voltage reference is differential and is repre-
sented by the voltage difference between the pins: +V
REF
and ­V
REF
. The absolute voltage on either pin, +V
REF
or
­V
REF,
can range from GND to V
DD
. However, the following
limitations apply:
For V
DD
= 5.0V and RANGE = 0 in the ACR, the differential
V
REF
must not exceed 2.5V.
For V
DD
= 5.0V and RANGE = 1 in the ACR, the differential
V
REF
must not exceed 5V.
For V
DD
= 3.0V and RANGE = 0 in the ACR, the differential
V
REF
must not exceed 1.25V.
For V
DD
= 3.0V and RANGE = 1 in the ACR, the differential
V
REF
must not exceed 2.5V.
CLOCK GENERATOR
The clock source for the ADS1242 and ADS1243 can be
provided from a crystal, oscillator, or external clock. When the
clock source is a crystal, external capacitors must be provided
to ensure start-up and stable clock frequency. This is shown in
both Figure 5 and Table II. X
OUT
is only for use with external
crystals and it should not be used as a clock driver for external
circuitry.
DIGITAL FILTER
The ADS1242 and ADS1243 have a 1279 tap linear phase
Finite Impulse Response (FIR) digital filter that a user can
configure for various output data rates. When a 2.4576MHz
crystal is used, the device can be programmed for an output
data rate of 15Hz, 7.5Hz, or 3.75Hz. Under these conditions,
the digital filter rejects both 50Hz and 60Hz interference. Figure
6 shows the digital filter frequency response for data output
rates of 15Hz, 7.5Hz, and 3.75Hz.
If a different data output rate is desired, a different crystal
frequency can be used. However, the rejection frequencies
shift accordingly. For example, a 3.6864MHz master clock with
the default register condition has:
(3.6864MHz/2.4576MHz) · 15Hz = 22.5Hz data output rate
and the first and second notch is:
1.5 · (50Hz and 60Hz) = 75Hz and 90Hz
DATA I/O INTERFACE
The ADS1242 has four pins and the ADS1243 has eight pins
that serve a dual purpose as both analog inputs and data
I/O. These pins are configured through the IOCON, DIR, and
DIO registers and can be individually configured as either
analog inputs or data I/O. See Figure 7 (page 14) for the
equivalent schematic of an Analog/Data I/O pin.
The IOCON register defines the pin as either an analog input
or data I/O. The power-up state is an analog input. If the pin
is configured as an analog input in the IOCON register, the
DIR and DIO registers have no effect on the state of the pin.
If the pin is configured as data I/O in the IOCON register,
then DIR and DIO are used to control the state of the pin.
The DIR register controls the direction of the data pin, either
as an input or output. If the pin is configured as an input in
the DIR register, then the corresponding DIO register bit
reflects the state of the pin. Make sure the pin is driven to a
logic one or zero when configured as an input to prevent
ADS1242, 1243
13
SBAS235B
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FIGURE 6. Filter Frequency Responses.
DATA
­3dB
OUTPUT RATE
BANDWIDTH
f
IN
= 50
±
0.3Hz
f
IN
= 60
±
0.3Hz
f
IN
= 50
±
1Hz
f
IN
= 60
±
1Hz
15Hz
14.6Hz
­80.8dB
­87.3dB
­68.5dB
­76.1dB
7.5Hz
3.44Hz
­85.9dB
­87.4dB
­71.5dB
­76.2dB
3.75Hz
1.65Hz
­93.8dB
­88.6dB
­86.8dB
­77.3dB
FREQUENCY RESPONSE FROM 45Hz to 65Hz
WHEN f
DATA
= 15Hz
Frequency (Hz)
­40
­50
­60
­70
­80
­90
­100
­110
­120
­130
­140
Magnitude (dB)
FREQUENCY RESPONSE FROM 45Hz to 65Hz
WHEN f
DATA
= 7.5Hz
Frequency (Hz)
­40
­50
­60
­70
­80
­90
­100
­110
­120
­130
­140
Magnitude (dB)
FREQUENCY RESPONSE FROM 45Hz to 65Hz
WHEN f
DATA
= 3.75Hz
Frequency (Hz)
­40
­50
­60
­70
­80
­90
­100
­110
­120
­130
­140
Magnitude (dB)
ADS1242 AND ADS1243
FILTER RESPONSE WHEN f
DATA
= 15Hz
Frequency (Hz)
0
­20
­40
­60
­80
­100
­120
­140
­160
­180
0
20
80
40
60
100
120
140
160
180
200
Gain (dB)
45
50
55
60
65
45
50
55
60
65
45
50
55
60
65
ADS1242 AND ADS1243
FILTER RESPONSE WHEN f
DATA
= 7.5Hz
Frequency (Hz)
0
­20
­40
­60
­80
­100
­120
­140
­160
­180
0
20
80
40
60
100
120
140
160
180
200
Gain (dB)
ADS1242 AND ADS1243
FILTER RESPONSE WHEN f
DATA
= 3.75Hz
Frequency (Hz)
f
OSC
= 2.4576MHz, SPEED = 0 or f
OSC
= 4.9152MHz, SPEED = 1
0
­20
­40
­60
­80
­100
­120
­140
­160
­180
0
20
80
40
60
100
120
140
160
180
200
Gain (dB)
ATTENUATION
ADS1242, 1243
14
SBAS235B
www.ti.com
FIGURE 7. Analog/Data Interface Pin.
IOCON
A
IN
x/Dx
To Analog Mux
DIO WRITE
DIR
DIO READ
excess current dissipation. If the pin is configured as an
output in the DIR register, then the corresponding DIO
register bit value determines the state of the output pin
(0 = GND, 1 = V
DD
).
It is still possible to perform A/D conversions on a pin
configured as data I/O. This may be useful as a test mode,
where the data I/O pin is driven and an A/D conversion is
done on the pin.
SERIAL PERIPHERAL INTERFACE
The Serial Peripheral Interface (SPI) allows a controller to
communicate synchronously with the ADS1242 and ADS1243.
The ADS1242 and ADS1243 operate in slave-only mode.
The serial interface is a standard four-wire SPI (CS , SCLK,
D
IN
and D
OUT
) interface.
Chip Select (
CS
)
The chip select (CS ) input must be externally asserted
before communicating with the ADS1242 or ADS1243. CS
must stay LOW for the duration of the communication.
Whenever CS goes HIGH, the serial interface is reset. CS
may be hard-wired LOW.
Serial Clock (SCLK)
The serial clock (SCLK) features a Schmitt-triggered input
and is used to clock D
IN
and D
OUT
data. Make sure to have
a clean SCLK to prevent accidental double-shifting of the
data. If SCLK is not toggled within three DRDY pulses, the
serial interface resets on the next SCLK pulse and starts a
new communication cycle. A special pattern on SCLK resets
the entire chip; see the RESET section for additional informa-
tion.
Data Input (D
IN
) and Data Output (D
OUT
)
The data input (D
IN
) and data output (D
OUT
) receive and send
data from the ADS1242 and ADS1243. D
OUT
is high imped-
ance when not in use to allow D
IN
and D
OUT
to be connected
together and driven by a bidirectional bus. Note: the Read
Data Continuous Mode (RDATAC) command should not be
issued when D
IN
and D
OUT
are connected. While in RDATAC
mode, D
IN
looks for the STOPC or RESET command. If
either of these 8-bit bytes appear on D
OUT
(which is con-
nected to D
IN
), the RDATAC mode ends.
DATA READY (
DRDY
) PIN
The DRDY line is used as a status signal to indicate when
data is ready to be read from the internal data register.
DRDY goes LOW when a new data word is available in the
DOR register. It is reset HIGH when a read operation from
the data register is complete. It also goes HIGH prior to the
updating of the output register to indicate when not to read
from the device to ensure that a data read is not attempted
while the register is being updated.
The status of DRDY can also be obtained by interrogating bit
7 of the ACR register (address 2
H
). The serial interface can
operate in 3-wire mode by tying the CS input LOW. In this
case, the SCLK, D
IN
, and D
OUT
lines are used to communi-
cate with the ADS1242 and ADS1243. This scheme is
suitable for interfacing to microcontrollers. If CS is required
as a decoding signal, it can be generated from a port bit of
the microcontroller.
POWER-UP--SUPPLY VOLTAGE RAMP RATE
The power-on reset circuitry was designed to accommodate
digital supply ramp rates as slow as 1V/10ms. To ensure
proper operation, the power supply should ramp monotoni-
cally.
ADS1242, 1243
15
SBAS235B
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DETAILED REGISTER DEFINITIONS
SETUP (Address 00
H
) Setup Register
Reset Value = iiii0000
bit 7-4
Factory Programmed Bits
bit 3
BOCS: Burnout Current Source
0 = Disabled (default)
1 = Enabled
bit 2-0
PGA2: PGA1: PGA0: Programmable Gain Amplifier
Gain Selection
000 = 1 (default)
001 = 2
010 = 4
011 = 8
100 = 16
101 = 32
110 = 64
111 = 128
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
ID
ID
ID
ID
BOCS
PGA2
PGA1
PGA0
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
PSEL3
PSEL2
PSEL1
PSEL0
NSEL3
NSEL2
NSEL1
NSEL0
ADDRESS
REGISTER
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
00
H
SETUP
ID
ID
ID
ID
BOCS
PGA2
PGA1
PGA0
01
H
MUX
PSEL3
PSEL2
PSEL1
PSEL0
NSEL3
NSEL2
NSEL1
NSEL0
02
H
ACR
DRDY
U/B
SPEED
BUFEN
BIT ORDER
RANGE
DR1
DR0
03
H
ODAC
SIGN
OSET6
OSET5
OSET4
OSET3
OSET2
OSET1
OSET0
04
H
DIO
DIO_7
DIO_6
DIO_5
DIO_4
DIO_3
DIO_2
DIO_1
DIO_0
05
H
DIR
DIR_7
DIR_6
DIR_5
DIR_4
DIR_3
DIR_2
DIR_1
DIR_0
06
H
IOCON
IO7
IO6
IO5
IO4
IO3
IO2
IO1
IO0
07
H
OCR0
OCR07
OCR06
OCR05
OCR04
OCR03
OCR02
OCR01
OCR00
08
H
OCR1
OCR15
OCR14
OCR13
OCR12
OCR11
OCR10
OCR09
OCR08
09
H
OCR2
OCR23
OCR22
OCR21
OCR20
OCR19
OCR18
OCR17
OCR16
0A
H
FSR0
FSR07
FSR06
FSR05
FSR04
FSR03
FSR02
FSR01
FSR00
0B
H
FSR1
FSR15
FSR14
FSR13
FSR12
FSR11
FSR10
FSR09
FSR08
0C
H
FSR2
FSR23
FSR22
FSR21
FSR20
FSR19
FSR18
FSR17
FSR16
0D
H
DOR2
DOR23
DOR22
DOR21
DOR20
DOR19
DOR18
DOR17
DOR16
0E
H
DOR1
DOR15
DOR14
DOR13
DOR12
DOR11
DOR10
DOR09
DOR08
0F
H
DOR0
DOR07
DOR16
FSR21
DOR04
DOR03
DOR02
DOR01
DOR00
TABLE III. Registers.
ADS1242 AND ADS1243
REGISTERS
The operation of the device is set up through individual
registers. Collectively, the registers contain all the informa-
tion needed to configure the part, such as data format,
multiplexer settings, calibration settings, data rate, etc. The
16 registers are shown in Table III.
MUX (Address 01
H
) Multiplexer Control Register
Reset Value = 01
H
bit 7-4
PSEL3: PSEL2: PSEL1: PSEL0: Positive Channel
Select
0000 = A
IN
0 (default)
0001 = A
IN
1
0010 = A
IN
2
0011 = A
IN
3
0100 = A
IN
4
0101 = A
IN
5
0110 = A
IN
6
0111 = A
IN
7
1xxx = AINCOM (except when xxx = 111)
1111 = Reserved
bit 3-0
NSEL3: NSEL2: NSEL1: NSEL0: Negative Channel
Select
0000 = A
IN
0
0001 = A
IN
1 (default)
0010 = A
IN
2
0011 = A
IN
3
0100 = A
IN
4
0101 = A
IN
5
0110 = A
IN
6
0111 = A
IN
7
1xxx = AINCOM (except when xxx = 111)
1111 = Reserved
ADS1242, 1243
16
SBAS235B
www.ti.com
ACR (Address 02
H
) Analog Control Register
Reset Value = X0
H
bit 7
DRDY: Data Ready (Read Only)
This bit duplicates the state of the DRDY pin.
bit 6
U/B: Data Format
0 = Bipolar (default)
1 = Unipolar
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
DRDY
U/B
SPEED
BUFEN
BIT ORDER RANGE
DR1
DR0
U/B
ANALOG INPUT
DIGITAL OUTPUT (Hex)
+FSR
0x7FFFFF
0
Zero
0x000000
­FSR
0x800000
+FSR
0xFFFFFF
1
Zero
0x000000
­FSR
0x000000
bit 5
SPEED: Modulator Clock Speed
0 = f
MOD
= f
OSC
/128 (default)
1 = f
MOD
= f
OSC
/256
bit 4
BUFEN: Buffer Enable
0 = Buffer Disabled (default)
1 = Buffer Enabled
bit 3
BIT ORDER: Data Output Bit Order
0 = Most Significant Bit Transmitted First (default)
1 = Least Significant Bit Transmitted First
Data is always shifted in or out MSB first.
bit 2
RANGE: Range Select
0 = Full-Scale Input Range equal to
±
V
REF
(default).
1 = Full-Scale Input Range equal to
±
1/2 V
REF
NOTE: This allows reference voltages as high as
V
DD
, but even with a 5V reference voltage the
calibration must be performed with this bit set to 0.
bit 1-0
DR1: DR0: Data Rate
(f
OSC
= 2.4576MHz, SPEED = 0)
00 = 15Hz (default)
01 = 7.5Hz
10 = 3.75Hz
11 = Reserved
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
SIGN
OSET6
OSET5
OSET4
OSET3
OSET2
OSET1
OSET0
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
DIO 7
DIO 6
DIO 5
DIO 4
DIO 3
DIO 2
DIO 1
DIO 0
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
DIR7
DIR6
DIR5
DIR4
DIR3
DIR2
DIR1
DIR0
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
IO7
IO6
IO5
IO4
IO3
IO2
IO1
IO0
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
OCR07
OCR06
OCR05
OCR04
OCR03
OCR02
OCR01
OCR00
ODAC (Address 03 ) Offset DAC
Reset Value = 00
H
bit 7
Sign
0 = Positive
1 = Negative
Offset
V
2 PGA
OSET [6 : 0]
127
RANGE
0
REF
=
·
·


=
Offset
V
PGA
OSET
RANGE
REF
=
·
·


=
4
6 0
127
1
[ : ]
NOTE: The offset DAC must be enabled after calibration or the calibration
nullifies the effects.
DIO (Address 04
H
) Data I/O
Reset Value = 00
H
If the IOCON register is configured for data, a value written
to this register appears on the data I/O pins if the pin is
configured as an output in the DIR register. Reading this
register returns the value of the data I/O pins.
Bits 4 to 7 are not used in ADS1242.
DIR (Address 05
H
) Direction Control for Data I/O
Reset Value = FF
H
Each bit controls whether the corresponding data I/O pin is
an output (= 0) or input (= 1). The default power-up state is
as inputs.
Bits 4 to 7 are not used in ADS1242.
IOCON (Address 06
H
) I/O Configuration Register
Reset Value = 00
H
bit 7-0
IO7: IO0: Data I/O Configuration
0 = Analog (default)
1 = Data
Configuring the pin as a data I/O pin allows it to be controlled
through the DIO and DIR registers.
Bits 4 to 7 are not used in ADS1242.
OCR0 (Address 07
H
) Offset Calibration Coefficient
(Least Significant Byte)
Reset Value = 00
H
ADS1242, 1243
17
SBAS235B
www.ti.com
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
FSR07
FSR06
FSR05
FSR04
FSR03
FSR02
FSR01
FSR00
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
FSR15
FSR14
FSR13
FSR12
FSR11
FSR10
FSR09
FSR08
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
FSR23
FSR22
FSR21
FSR20
FSR19
FSR18
FSR17
FSR16
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
DOR23
DOR22
DOR21
DOR20
DOR19
DOR18
DOR17
DOR16
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
DOR15
DOR14
DOR13
DOR12
DOR11
DOR10
DOR09
DOR08
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
DOR07
DOR06
DOR05
DOR04
DOR03
DOR02
DOR01
DOR00
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
OCR15
OCR14
OCR13
OCR12
OCR11
OCR10
OCR09
OCR08
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
OCR23
OCR22
OCR21
OCR20
OCR19
OCR18
OCR17
OCR16
OCR1 (Address 08
H
) Offset Calibration Coefficient
(Middle Byte)
Reset Value = 00
H
OCR2 (Address 09
H
) Offset Calibration Coefficient
(Most Significant Byte)
Reset Value = 00
H
FSR0 (Address 0A
H
) Full-Scale Register
(Least Significant Byte)
Reset Value = 59
H
FSR1 (Address 0B
H
) Full-Scale Register
(Middle Byte)
Reset Value = 55
H
FSR2 (Address 0C
H
) Full-Scale Register
(Most Significant Byte)
Reset Value = 55
H
DOR2 (Address 0D
H
) Data Output Register
(Most Significant Byte) (Read Only)
Reset Value = 00
H
DOR1 (Address 0E
H
) Data Output Register
(Middle Byte) (Read Only)
Reset Value = 00
H
DOR0 (Address 0F
H
) Data Output Register
(Least Significant Byte) (Read Only)
Reset Value = 00
H
ADS1242, 1243
18
SBAS235B
www.ti.com
RDATA­Read Data
Description: Read the most recent conversion result from the
Data Output Register (DOR). This is a 24-bit value.
Operands:
None
Bytes:
1
Encoding:
0000 0001
Data Transfer Sequence:
RDATAC­Read Data Continuous
Description: Read Data Continuous mode enables the con-
tinuous output of new data on each DRDY. This command
eliminates the need to send the Read Data Command on each
DRDY. This mode may be terminated by either the STOPC
command or the RESET command. Wait at least 10 f
OSC
after
DRDY falls before reading.
Operands:
None
Bytes:
1
Encoding:
0000 0011
Data Transfer Sequence:
Command terminated when "uuuu uuuu" equals STOPC or
RESET.
COMMANDS
DESCRIPTION
OP CODE
2nd COMMAND BYTE
RDATA
Read Data
0000 0001 (01
H
)
--
RDATAC
Read Data Continuously
0000 0011 (03
H
)
--
STOPC
Stop Read Data Continuously
0000 1111 (0F
H
)
--
RREG
Read from REG "rrrr"
0001 r r r r (1x
H
)
xxxx_nnnn (# of regs-1)
WREG
Write to REG "rrrr"
0101 r r r r (5x
H
)
xxxx_nnnn (# of regs-1)
SELFCAL
Offset and Gain Self Cal
1111 0000 (F0
H
)
--
SELFOCAL
Self Offset Cal
1111 0001 (F1
H
)
--
SELFGCAL
Self Gain Cal
1111 0010 (F2
H
)
--
SYSOCAL
Sys Offset Cal
1111 0011 (F3
H
)
--
SYSGCAL
Sys GainCal
1111 0100 (F4
H
)
--
WAKEUP
Wakup from SLEEP Mode
1111 1011 (FB
H
)
--
DSYNC
Sync DRDY
1111 1100 (FC
H
)
--
SLEEP
Put in SLEEP Mode
1111 1101 (FD
H
)
--
RESET
Reset to Power-Up Values
1111 1110 (FE
H
)
--
NOTE: The received data format is always MSB first; the data out format is set by the BIT ORDER bit in the ACR register.
TABLE IV. Command Summary.
The commands listed in Table IV control the operations of
the ADS1242 and ADS1243. Some of the commands are
stand-alone commands (for example, RESET) while others
require additional bytes (for example, WREG requires the
count and data bytes).
Operands:
n = count (0 to 127)
r = register (0 to 15)
x = don't care
ADS1242 AND ADS1243 CONTROL COMMAND DEFINITIONS
D
IN
0000 0001
· · ·
(1)
xxxx xxxx
xxxx xxxx
xxxx xxxx
D
OUT
NOTE: (1) For wait time, refer to timing specification.
MSB
Mid-Byte
LSB
D
IN
· · ·
0000 0011
· · ·
(1)
uuuu uuuu
uuuu uuuu
uuuu uuuu
D
OUT
MSB
Mid-Byte
LSB
D
OUT
MSB
Mid-Byte
LSB
DRDY
DRDY
· · ·
NOTE: (1) For wait time, refer to timing specification.
ADS1242, 1243
19
SBAS235B
www.ti.com
STOPC­Stop Continuous
Description: Ends the continuous data output mode. Issue
after DRDY goes LOW.
Operands:
None
Bytes:
1
Encoding:
0000 1111
Data Transfer Sequence:
RREG­Read from Registers
Description: Output the data from up to 16 registers starting
with the register address specified as part of the instruction.
The number of registers read will be one plus the second byte
count. If the count exceeds the remaining registers, the ad-
dresses wrap back to the beginning.
Operands:
r, n
Bytes:
2
Encoding:
0001 rrrr xxxx nnnn
Data Transfer Sequence:
Read Two Registers Starting from Register 01
H
(MUX)
WREG­Write to Registers
Description: Write to the registers starting with the register
address specified as part of the instruction. The number of
registers that will be written is one plus the value of the second
byte.
Operands:
r, n
Bytes:
2
Encoding:
0101 rrrr xxxx nnnn
Data Transfer Sequence:
Write Two Registers Starting from 04
H
(DIO)
SELFCAL­Offset and Gain Self Calibration
Description: Starts the process of self calibration. The Offset
Calibration Register (OCR) and the Full-Scale Register (FSR)
are updated with new values after this operation.
Operands:
None
Bytes:
1
Encoding:
1111 0000
Data Transfer Sequence:
SELFOCAL­Offset Self Calibration
Description: Starts the process of self-calibration for offset.
The Offset Calibration Register (OCR) is updated after this
operation.
Operands:
None
Bytes:
1
Encoding:
1111 0001
Data Transfer Sequence:
SELFGCAL­Gain Self Calibration
Description: Starts the process of self-calibration for gain.
The Full-Scale Register (FSR) is updated with new values after
this operation.
Operands:
None
Bytes:
1
Encoding:
1111 0010
Data Transfer Sequence:
D
IN
0000 1111
xxx
DRDY
D
IN
0001 0001
0000 0001
xxxx xxxx
xxxx xxxx
D
OUT
MUX
ACR
· · ·
(1)
NOTE: (1) For wait time, refer to timing specification.
0101 0100
xxxx 0001
Data for DIO
Data for DIR
D
IN
D
IN
1111 0000
D
IN
1111 0001
D
IN
1111 0010
ADS1242, 1243
20
SBAS235B
www.ti.com
SYSOCAL­System Offset Calibration
Description: Initiates a system offset calibration. The input
should be set to 0V, and the ADS1242 and ADS1243 compute
the OCR value that compensates for offset errors. The Offset
Calibration Register (OCR) is updated after this operation. The
user must apply a zero input signal to the appropriate analog
inputs. The OCR register is automatically updated afterwards.
Operands:
None
Bytes:
1
Encoding:
1111 0011
Data Transfer Sequence:
SYSGCAL­System Gain Calibration
Description: Starts the system gain calibration process. For
a system gain calibration, the input should be set to the
reference voltage and the ADS1242 and ADS1243 compute
the FSR value that will compensate for gain errors. The FSR
is updated after this operation. To initiate a system gain
calibration, the user must apply a full-scale input signal to the
appropriate analog inputs. FCR register is updated automati-
cally.
Operands:
None
Bytes:
1
Encoding:
1111 0100
Data Transfer Sequence:
DSYNC­Sync DRDY
Description: Synchronizes the ADS1242 and ADS1243 to an
external event.
Operands:
None
Bytes:
1
Encoding:
1111 1100
Data Transfer Sequence:
SLEEP­Sleep Mode
Description: Puts the ADS1242 and ADS1243 into a low
power sleep mode. To exit sleep mode, issue the WAKEUP
command.
Operands:
None
Bytes:
1
Encoding:
1111 1101
Data Transfer Sequence:
RESET­Reset to Default Values
Description: Restore the registers to their power-up values.
This command stops the Read Continuous mode.
Operands:
None
Bytes:
1
Encoding:
1111 1110
Data Transfer Sequence:
WAKEUP
Description: Wakes the ADS1242 and ADS1243 from SLEEP
mode.
Operands:
None
Bytes:
1
Encoding:
1111 1011
Data Transfer Sequence:
D
IN
1111 0011
D
IN
1111 0100
D
IN
1111 1011
D
IN
1111 1100
D
IN
1111 1101
D
IN
1111 1110
ADS1242, 1243
21
SBAS235B
www.ti.com
APPLICATION EXAMPLES
GENERAL-PURPOSE WEIGHT SCALE
Figure 8 shows a typical schematic of a general-purpose
weight scale application using the ADS1242. In this ex-
ample, the internal PGA is set to either 64 or 128 (depending
on the maximum output voltage of the load cell) so that the
ADS1242
V
REF+
DRDY
SCLK
D
OUT
D
OUT
CS
X
IN
V
DD
GND
A
IN
0
V
DD
2.7V ~ 5.25V
GND
MCLK
A
IN
1
EMI Filter
Load Cell
MSP430x4xx
or other
Microprocessor
V
REF­
SPI
X
OUT
EMI Filter
EMI Filter
EMI Filter
load cell output can be directly applied to the differential
inputs of ADS1242.
HIGH PRECISION WEIGHT SCALE
Figure 9 shows the typical schematic of a high-precision
weight scale application using the ADS1242. The front-end
differential amplifier helps maximize the dynamic range.
ADS1242
ADS1243
V
REF+
DRDY
SCLK
D
OUT
D
IN
CS
X
IN
V
DD
GND
A
IN
0
V
DD
2.7V ~ 5.25V
GND
MCLK
A
IN
1
EMI Filter
EMI Filter
Load Cell
OPA2335
G = 1 + 2 · R
F
/R
G
MSP430x4xx
or other
Microprocessor
V
REF­
SPI
X
OUT
2.7V ~ 5.25V
EMI Filter
EMI Filter
OPA2335
R
F
C
I
R
G
R
F
R
I
R
I
FIGURE 8. Schematic of a General-Purpose Weight Scale.
FIGURE 9. Block Diagram for a High-Precision Weight Scale.
ADS1242, 1243
22
SBAS235B
www.ti.com
+5V SUPPLY ANALOG INPUT
(1)
GENERAL EQUATIONS
DIFFERENTIAL
PGA OFFSET
FULL-SCALE
DIFFERENTIAL
PGA SHIFT
GAIN SETTING
FULL-SCALE RANGE
INPUT VOLTAGES
(2)
RANGE
RANGE
INPUT VOLTAGES
(2)
RANGE
1
5V
±
2.5V
±
1.25V
2
2.5V
±
1.25V
±
0.625V
4
1.25V
±
0.625V
±
312.5mV
8
0.625V
±
312.5mV
±
156.25mV
16
312.5mV
±
156.25mV
±
78.125mV
32
156.25mV
±
78.125mV
±
39.0625mV
64
78.125mV
±
39.0625mV
±
19.531mV
128
39.0625mV
±
19.531mV
±
9.766mV
NOTES: (1) With a +2.5V reference. (2) Refer to electrical specification for analog input voltage range.
TABLE VI. Full-Scale Range versus PGA Setting.
RANGE = 0
RANGE = 1
V
PGA
REF
±
·
V
PGA
REF
2
±
·
V
PGA
REF
4
f
f
mfactor
SAMP
OSC
=
·
8
f
f
mfactor
SAMP
OSC
=
·
4
f
f
mfactor
SAMP
OSC
=
·
2
f
f
mfactor
SAMP
OSC
=
PGA SETTING
SAMPLING FREQUENCY
1, 2, 4, 8
16
32
64, 128
SPEED = 0
SPEED = 1
mfactor
128
256
DEFINITION OF TERMS
An attempt has been made to be consistent with the termi-
nology used in this data sheet. In that regard, the definition
of each term is given as follows:
Analog Input Voltage--the voltage at any one analog input
relative to GND.
Analog Input Differential Voltage--given by the following
equation: (IN+) ­ (IN­). Thus, a positive digital output is
produced whenever the analog input differential voltage is
positive, while a negative digital output is produced whenever
the differential is negative.
For example, when the converter is configured with a 2.5V
reference and placed in a gain setting of 1, the positive
full-scale output is produced when the analog input differen-
tial is 2.5V. The negative full-scale output is produced when
the differential is ­2.5V. In each case, the actual input
voltages must remain within the GND to V
DD
range.
Conversion Cycle--the term
conversion cycle usually refers
to a discrete A/D conversion operation, such as that per-
formed by a successive approximation converter. As used
here, a conversion cycle refers to the t
DATA
time period.
Data Rate--The rate at which conversions are completed.
See definition for f
DATA
.
f
f
SPEED
DR
DATA
osc
SPEED
DR
=
·
·
·
=
=
128 2
1280 2
0 1
0 1 2
,
, ,
f
OSC
--the frequency of the crystal oscillator or CMOS com-
patible input signal at the X
IN
input of the ADS1242 and
ADS1243.
f
MOD
--the frequency or speed at which the modulator of the
ADS1242 and ADS1243 is running. This depends on the
SPEED bit as given by the following equation:
f
f
mfactor
f
MOD
osc
osc
SPEED
=
=
·
128 2
f
SAMP
--the frequency, or switching speed, of the input sam-
pling capacitor. The value is given by one of the following
equations:
f
DATA
--the frequency of the digital output data produced by
the ADS1242 and ADS1243, f
DATA
is also referred to as the
Data Rate.
Full-Scale Range (FSR)--as with most A/D converters, the
full-scale range of the ADS1242 and ADS1243 is defined as
the input, that produces the positive full-scale digital output
minus the input, that produces the negative full-scale digital
output.
For example, when the converter is configured with a 2.5V
reference and is placed in a gain setting of 2, the full-scale
range is: [1.25V (positive full-scale) minus ­1.25V (negative
full-scale)] = 2.5V.
Least Significant Bit (LSB) Weight--this is the theoretical
amount of voltage that the differential voltage at the analog
input has to change in order to observe a change in the
output data of one least significant bit. It is computed as
follows:
LSB Weight
Full
ScaleRange
N
=
-
2
1
­
where N is the number of bits in the digital output.
t
DATA
--the inverse of f
DATA
, or the period between each data
output.
PACKAGING INFORMATION
ORDERABLE DEVICE
STATUS(1)
PACKAGE TYPE
PACKAGE DRAWING
PINS
PACKAGE QTY
ADS1242IPWR
ACTIVE
TSSOP
PW
16
2500
ADS1242IPWT
ACTIVE
TSSOP
PW
16
250
ADS1243IPWR
ACTIVE
TSSOP
PW
20
2500
ADS1243IPWT
ACTIVE
TSSOP
PW
20
250
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
PACKAGE OPTION ADDENDUM
www.ti.com
29-Oct-2004
MECHANICAL DATA

MTSS001C ­ JANUARY 1995 ­ REVISED FEBRUARY 1999
POST OFFICE BOX 655303
·
DALLAS, TEXAS 75265
PW (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
14 PINS SHOWN
0,65
M
0,10
0,10
0,25
0,50
0,75
0,15 NOM
Gage Plane
28
9,80
9,60
24
7,90
7,70
20
16
6,60
6,40
4040064/F 01/97
0,30
6,60
6,20
8
0,19
4,30
4,50
7
0,15
14
A
1
1,20 MAX
14
5,10
4,90
8
3,10
2,90
A MAX
A MIN
DIM
PINS **
0,05
4,90
5,10
Seating Plane
0
°
­ 8
°
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153
IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications,
enhancements, improvements, and other changes to its products and services at any time and to discontinue
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amplifier.ti.com
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www.ti.com/audio
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dataconverter.ti.com
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dsp.ti.com
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interface.ti.com
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www.ti.com/digitalcontrol
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logic.ti.com
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www.ti.com/military
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power.ti.com
Optical Networking
www.ti.com/opticalnetwork
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microcontroller.ti.com
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www.ti.com/video
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www.ti.com/wireless
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