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GPS PROCESSOR
FEATURES
s
Application specific features
·
12 channel GPS correlation DSP hardware
and ST20 CPU (for control and position calu-
culations) on one chip
·
no TCXO required
·
RTCA-SC159 / WAAS / EGNOS supported
s
GPS performance
·
accuracy
- stand alone
with SA on <100m, SA off <30m
- differential <1m
- surveying <1cm
·
time to first fix
- autonomous start 90s
- cold start 45s
- warm start 7s
- obscuration 1s
s
32-bit ST20 CPU
·
16/33 MHz processor clock
·
25 MIPS at 33 MHz
·
fast integer/bit operations
s
4 Kbytes on-chip SRAM
·
130 Mbytes/s maximum bandwidth
s
Programmable memory interface
·
4 separately configurable regions
·
8/16-bits wide
·
support for mixed memory
·
2 cycle external access
s
Serial communications
·
Programmable UART (ASC)
·
OS-Link
s
Vectored interrupt subsystem
·
2 dedicated interrupt pins
·
5 levels of interrupt
s
Power management
·
low power operation
·
power down modes
s
Professional toolset support
·
ANSI C compiler and libraries
·
INQUEST advanced debugging tools
s
Technology
·
Static clocked 50 MHz design
·
3.3 V, sub micron technology
s
100 pin PQFP package
ST20-GP1
ENGINEERING DATA
The information in this datasheet is subject to change
42 1672 02
October 1996
APPLICATIONS
s
Global Positioning System (GPS) receivers
s
Car navigation systems
s
Fleet management systems
s
Time reference for telecom systems
GPS
radio
12 channel GPS
Low
controller
power
Real time
clock/calendar
4K
SRAM
Programmable
memory
interface
RAM
ROM/
FLASH
ST20-GP1
ST20
CPU
Interrupt
controller
Serial
communications
Parallel
input/output
Byte-wide
parallel port
.
.
.
6
8
2 UART (ASC)
1 OS-Link
.
hardware DSP
Contents
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1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2
ST20-GP1 architecture overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3
Digital signal processing module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
3.1
DSP module registers .......................................................................................................................... 13
4
Central processing unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
4.1
Registers .............................................................................................................................................. 18
4.2
Processes and concurrency ................................................................................................................ 19
4.3
Priority .................................................................................................................................................. 21
4.4
Process communications ..................................................................................................................... 21
4.5
Timers .................................................................................................................................................. 22
4.6
Traps and exceptions .......................................................................................................................... 23
5
Interrupt controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
5.1
Interrupt vector table ............................................................................................................................ 29
5.2
Interrupt handlers ................................................................................................................................. 29
5.3
Interrupt latency ................................................................................................................................... 30
5.4
Pre-emption and interrupt priority ........................................................................................................ 30
5.5
Restrictions on interrupt handlers ........................................................................................................ 30
5.6
Interrupt configuration registers ........................................................................................................... 31
6
Instruction set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
6.1
Instruction cycles ................................................................................................................................. 34
6.2
Instruction characteristics .................................................................................................................... 35
6.3
Instruction set tables ............................................................................................................................ 36
7
Memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
7.1
System memory use ............................................................................................................................ 45
7.2
Boot ROM ............................................................................................................................................ 46
7.3
Internal peripheral space ..................................................................................................................... 46
8
Memory subsystem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
8.1
SRAM .................................................................................................................................................. 49
9
Programmable memory interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
9.1
EMI signal descriptions ........................................................................................................................ 51
9.2
Strobe allocation .................................................................................................................................. 52
9.3
External accesses ................................................................................................................................ 52
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9.4
MemWait .............................................................................................................................................. 56
9.5
EMI configuration registers .................................................................................................................. 58
9.6
Reset and bootstrap behavior .............................................................................................................. 59
10 Clocks and low power controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
10.1
Clocks .................................................................................................................................................. 61
10.2
Low power control ................................................................................................................................ 61
10.3
Low power configuration registers ....................................................................................................... 63
10.4
Clocking sources ................................................................................................................................. 65
11 System services . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
11.1
Reset, initialization and debug ............................................................................................................. 67
11.2
Bootstrap ............................................................................................................................................. 68
12 Serial link interface (OS-Link) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
12.1
OS-Link protocol .................................................................................................................................. 70
12.2
OS-Link speed ..................................................................................................................................... 70
12.3
OS-Link connections ............................................................................................................................ 71
13 UART interface (ASC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
13.1
Asynchronous serial controller operation ............................................................................................. 73
13.2
Hardware error detection capabilities .................................................................................................. 76
13.3
Baud rate generation ........................................................................................................................... 76
13.4
Interrupt control .................................................................................................................................... 77
13.5
ASC configuration registers ................................................................................................................. 79
14 Parallel input/output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
14.1
PIO Port ............................................................................................................................................... 85
15 Byte-wide parallel port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
15.1
EMI mode operation ............................................................................................................................ 88
15.2
Parallel link (DMA) mode operation ..................................................................................................... 88
15.3
Configuration registers ......................................................................................................................... 88
15.4
External data transfer protocols ........................................................................................................... 89
16 Configuration register addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
17 Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
18 GPS Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
18.1
Accuracy ............................................................................................................................................ 100
18.2
Time to first fix ................................................................................................................................... 101
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19 Timing specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
19.1
EMI timings ........................................................................................................................................ 102
19.2
Link timings ........................................................................................................................................ 104
19.3
Reset and Analyse timings ................................................................................................................ 105
19.4
ClockIn timings .................................................................................................................................. 106
19.5
Parallel port timings ........................................................................................................................... 107
20 Pin list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
21 Package specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
21.1
ST20-GP1 package pinout ................................................................................................................ 112
21.2
100 pin PQFP package dimensions .................................................................................................. 113
22 Device ID . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
23 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
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1
Introduction
The ST20-GP1 is an application-specific single chip micro using the ST20 CPU with
microprocessor style peripherals added on-chip. It incorporates DSP hardware for processing the
signals from GPS (Global Positioning System) satellites.
The twelve channel GPS correlation DSP hardware is designed to handle twelve satellites, two of
which can be initialized to support the RTCA-SC159 specification for WAAS (Wide Area
Augmentation Service) and EGNOS (European Geostationary Navigation Overlay System)
services.
The ST20-GP1 has been designed to minimize system costs and reduce the complexity of GPS
systems. It offers all hardware DSP and microprocessor functions on one chip. Whilst the entire
analogue section, RF and clock generation are available on a companion chip. Thus, with the
addition of a ROM and a RAM chip, a complete GPS system is possible using just four chips, see
Figure 1.1.
Figure 1.1 GPS system
The ST20-GP1 supports large values of frequency offset, allowing the use of a very low cost
oscillator, thus saving the cost of a Temperature Controlled Crystal Oscillator (TCXO).
The CPU and software have access to the part-processed signal to enable accelerated acquisition
time.
The ST20-GP1 can implement the GPS digital signal processing algorithms using less than 50% of
the available CPU processing power. This leaves the rest available for integrating OEM application
functions such as route-finding, map display and telemetry. A hardware microkernel in the ST20
UART
DSP
ASIC
Radio
Antenna
CPU
Real
time
clock
Watchdog
RAM
ROM
Low
cost
crystal
ST20-GP1
Parallel I/O
Single chip
No TCXO
Driver
(optional)
timer
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