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Part Number ST19KF16

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DATA BRIEFING
This is Brief Data from STMicroelectronics. Details are subject to change without notice. For complete data, please contact
your nearest Sales Office or SmartCard Products Divison, Rousset, France. Fax: (+33) 4 42 25 87 29
ST19KF16
Smartcard MCU
With 1088 Bits Modular Arithmetic Processor
s
8 BIT ARCHITECTURE CPU
s
32 KBytes of USER ROM WITH
PARTITIONING
s
SYSTEM ROM FOR LIBRARIES
s
1984 Bytes of RAM WITH PARTITIONING
s
16 KBytes of EEPROM WITH PARTITIONING
­ Highly reliable CMOS EEPROM technology
­ 10 year data retention
­ 100,000 Erase/Write cycle endurance
­ Separate Write and Erase cycles for fast "1"
programming
­ 1 to 64 bytes Erase or Program in 1 ms
s
1088 BITS MODULAR ARITHMETIC
PROCESSOR
­ Fast modular multiplication and squaring us-
ing Montgomery method
­ Software Crypto Libraries in separate ROM
area for efficient algorithm coding using a set
of advanced functions
­ Software selectable operand length
up to 2176 bits
s
SECURITY FIREWALLS FOR MAP AND
MEMORIES
s
VERY HIGH SECURITY FEATURES
INCLUDING EEPROM FLASH PROGRAM
AND RAM FLASH CLEAR
s
8 BIT TIMER
s
SERIAL ACCESS, ISO 7816-3 COMPATIBLE
s
3V
±
10% or 5V
±
10% SUPPLY VOLTAGE
s
POWER SAVING STANDBY MODE
s
UP TO 10 MHz INTERNAL OPERATING
FREQUENCY
s
CONTACT ASSIGNMENT COMPATIBLE ISO
7816-2
s
ESD PROTECTION GREATER THAN 5000V
s
FAST CRYPTOGRAPHIC FUNCTIONS
PROCESSING (5V
±
10%, 5MHz)
*CRT: Chinese Remainder Theorem
Function
Speed
RSA 512 bits signature with CRT *
20 ms
RSA 512 bits signature without CRT
60 ms
RSA 512 bits verification (e=$10001)
2 ms
RSA 1024 bits signature with CRT
110 ms
RSA 1024 bits signature without CRT
380 ms
RSA 1024 bits verification (e=$10001)
5 ms
RSA 2048 bits signature with CRT
800 ms
RSA 2048 bits verification (e=$10001)
100 ms
EC 160 bits signature
250 ms
EC 160 bits verification
500 ms
2
2
2
2
Micromodule (D4)
Wafer
BD.KF16/9809VP1
ST19KF16
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HARDWARE DESCRIPTION
The ST19KF16, a member of the ST19 device
family, is a serial access microcontroller especially
designed for very large volume and cost competi-
tive secure portable objects, where high perform-
ance Public Key Algorithms will be implemented,
to cut down initialization and communication costs
and to increase security.
Its internal Modular Arithmetic Processor is de-
signed to speed up cryptographic calculations us-
ing Public Key Algorithms. Based on a 1088 bit
architecture, it processes modular multiplication
and squaring up to 2176 bit operands.
The ST19KF16 is based on a STMicroelectronics
8 bit CPU core including on-chip memories: 1984
Bytes of RAM, 32 KBytes of USER ROM and 16
KBytes of EEPROM.
RAM, ROM and EEPROM memories can be con-
figured into partitions. Access rules from any
memory partition to another partition are setup by
the user defined Memory Access Control Logic.
It is manufactured using the highly reliable ST
CMOS EEPROM technology.
As all other ST19 family members, it is fully com-
patible with the ISO standards for Smartcard appli-
cations.
SOFTWARE SUPPORT
SOFTWARE DEVELOPMENT
Software development and firmware (ROM code/
options) generation are completed by the ST16-19
HDS development system.
CRYPTO LIBRARIES
For an easy and efficient use of the Modular Arith-
metic Processor (MAP), ST proposes a complete
set of firmware subroutines. This library is located
in a specific ROM area, leaving 32 KBytes in the
User ROM for the application software. This li-
brary saves the operating system designer from
coding first layer functions and allows the designer
to concentrate on algorithms and Public Key Cryp-
tographic (PKC) protocol implementation.
This library contains firmware functions for:
­ loading and unloading parameters and results
to or from the MAP
­ calculating Montgomery constants
­ basic mathematics including modular squaring
and multiplication for various lengths
­ modular exponentiation using or not the Chi-
nese Remainder Theorem (CRT),
­ more elaborate functions such as RSA signa-
tures and authentications for any modulo length
up to 2176 bits long or DSA signature and veri-
fication and elliptic curves.
­ full internal key generation for signatures/au-
thentications. This guarantees that the secret
key will never be known outside the chip and
contributes to overall system security.
­ long random number generation
­ sha-1
Figure 1. Block Diagram
SCP 133b/DS
INTERNAL BUS
RAM
Bytes
USER
ROM
Bytes
EEPROM
Bytes
MAP
SERIAL
I/O
INTER-
FACE
8 BIT
CPU
8 BIT
TIMER
CLOCK
GENERA-
TOR
MODULE
UNPRE-
DICTABLE
NUMBER
GENERATOR
SECURITY
SYSTEM ROM
AND
MAP FIREWALL
MEMORY ACCESS FIREWALL
CLK
SYSTEM ROM
AND
CRYPTO
LIBRARIES
RESET
VCC
I/O
GND
ADMINISTRATOR
a
a
1984
16 K
32 K
1088 Bits