Document Outline

• FEATURES SUMMARY
  • Figure 1. Packages
• SUMMARY DESCRIPTION
  • Figure 2. Logic Diagram (FWH/LPC Interface)
  • Figure 3. Logic Diagram (A/A Mux Interface)
  • Table 1. Signal Names (FWH/LPC Interface)
  • Table 2. Signal Names (A/A Mux Interface)
  • Figure 4. PLCC Connections
  • Figure 5. TSOP32 Connections
  • Figure 6. TSOP40 Connections
  • Table 3. Addresses (M50FLW040A)
  • Table 4. Addresses (M50FLW040B)
• SIGNAL DESCRIPTIONS
  • Firmware Hub/Low Pin Count (FWH/LPC) Signal Descriptions
    • Input/Output Communications (FWH0/LAD0- FWH3/LAD3).
    • Input Communication Frame (FWH4/ LFRAME).
    • Identification Inputs (ID0-ID3).
    • General Purpose Inputs (GPI0-GPI4).
    • Interface Configuration (IC).
    • Interface Reset (RP).
    • CPU Reset (INIT).
    • Clock (CLK).
    • Top Block Lock (TBL).
    • Write Protect (WP).
    • Reserved for Future Use (RFU).
  • Address/Address Multiplexed (A/A Mux) Signal Descriptions
    • Address Inputs (A0-A10).
    • Data Inputs/Outputs (DQ0-DQ7).
    • Output Enable (G).
    • Write Enable (W).
    • Row/Column Address Select (RC).
    • Ready/Busy Output (RB).
  • Supply Signal Descriptions
    • VCC Supply Voltage.
    • VPP Optional Supply Voltage.
    • VSS Ground.
    • Table 5. Memory Identification Input Configuration (LPC mode)
• BUS OPERATIONS
  • Firmware Hub/Low Pin Count (FWH/LPC) Bus Operations
    • Bus Read.
    • Bus Write.
    • Bus Abort
    • Standby.
    • Reset.
    • Block Protection.
  • Address/Address Multiplexed (A/A Mux) Bus Operations
    • Bus Read.
    • Bus Write.
    • Output Disable.
    • Reset.
    • Table 6. FWH Bus Read Field Definitions
    • Figure 7. FWH Bus Read Waveforms
    • Table 7. FWH Bus Write Field Definitions
    • Figure 8. FWH Bus Write Waveforms
    • Table 8. LPC Bus Read Field Definitions (1-Byte)
    • Figure 9. LPC Bus Read Waveforms (1-Byte)
    • Table 9. LPC Bus Write Field Definitions (1 Byte)
    • Figure 10. LPC Bus Write Waveforms (1 Byte)
    • Table 10. A/A Mux Bus Operations
• COMMAND INTERFACE
  • Table 11. Command Codes
  • Read Memory Array Command
  • Read Status Register Command
  • Read Electronic Signature Command
  • Table 12. Electronic Signature Codes
  • Program Command
  • Quadruple Byte Program Command (A/A Mux Interface)
  • Double/Quadruple Byte Program Command (FWH Mode)
  • Chip Erase Command
  • Block Erase Command
  • Sector Erase Command
  • Clear Status Register Command
  • Program/Erase Suspend Command
  • Program/Erase Resume Command
  • Table 13. Commands
• STATUS REGISTER
  • Program/Erase Controller Status (Bit SR7)
  • Erase Suspend Status (Bit SR6)
  • Erase Status (Bit SR5)
  • Program Status (Bit SR4)
  • VPP Status (Bit SR3)
  • Program Suspend Status (Bit SR2)
  • Block Protection Status (Bit SR1)
  • Reserved (Bit SR0)
  • Table 14. Status Register Bits
• FIRMWARE HUB/LOW PIN COUNT (FWH/LPC) INTERFACE CONFIGURATION REGISTERS
  • Lock Registers
    • Write Lock
    • Read Lock
    • Lock Down
    • Table 15. Configuration Register Map
    • Table 16. Lock Register Bit Definitions
    • Table 17. General Purpose Inputs Register Definition
  • Firmware Hub/Low Pin Count (FWH/LPC) General Purpose Input Register
  • Manufacturer Code Register
• PROGRAM AND ERASE TIMES
  • Table 18. Program and Erase Times
• MAXIMUM RATING
  • Table 19. Absolute Maximum Ratings
• DC and AC PARAMETERS
  • Table 20. Operating Conditions
  • Table 21. FWH/LPC Interface AC Measurement Conditions
  • Table 22. A/A Mux Interface AC Measurement Conditions
  • Figure 11. FWH/LPC Interface AC Measurement I/O Waveforms
  • Figure 12. A/A Mux Interface AC Measurement I/O Waveform
  • Figure 13. AC Measurement Load Circuit
  • Table 23. Impedance
  • Table 24. DC Characteristics
  • Figure 14. FWH/LPC Interface Clock Waveform
  • Table 25. FWH/LPC Interface Clock Characteristics
  • Figure 15. FWH/LPC Interface AC Signal Timing Waveforms
  • Table 26. FWH/LPC Interface AC Signal Timing Characteristics
  • Figure 16. Reset AC Waveforms
  • Table 27. Reset AC Characteristics
  • Figure 17. A/A Mux Interface Read AC Waveforms
  • Table 28. A/A Mux Interface Read AC Characteristics
  • Figure 18. A/A Mux Interface Write AC Waveforms
  • Table 29. A/A Mux Interface Write AC Characteristics
• PACKAGE MECHANICAL
  • Figure 19. PLCC32 … 32 pin Rectangular Plastic Leaded Chip Carrier, Package Outline
  • Table 30. PLCC32 … 32 pin Rectangular Plastic Leaded Chip Carrier, Package Mechanical Data
  • Figure 20. TSOP32 … 32 lead Plastic Thin Small Outline, 8x14 mm, Package Outline
  • Table 31. TSOP32 … 32 lead Plastic Thin Small Outline, 8x14 mm, Package Mechanical Data
  • Figure 21. TSOP40 … 40 lead Plastic Thin Small Outline, 10 x 20mm, Package Outline
  • Table 32. TSOP40 … 40 lead Plastic Thin Small Outline, 10 x 20mm, Package Mechanical Data
• PART NUMBERING
  • Table 33. Ordering Information Scheme
• APPENDIX A. BLOCK AND SECTOR ADDRESS TABLE
  • Table 34. M50FLW040A Block and Sector Addresses
  • Table 35. M50FLW040B Block and Sector Addresses
• APPENDIX B. FLOWCHARTS AND PSEUDO CODES
  • Figure 22. Program Flowchart and Pseudo Code
  • Figure 23. Double/Quadruple Byte Program Flowchart and Pseudo code (FWH Mode Only)
  • Figure 24. Quadruple Byte Program Flowchart and Pseudo Code (A/A Mux Interface Only)
  • Figure 25. Program Suspend and Resume Flowchart and Pseudo Code
  • Figure 26. Chip Erase Flowchart and Pseudo Code (A/A Mux Interface Only)
  • Figure 27. Sector/Block Erase Flowchart and Pseudo Code
  • Figure 28. Erase Suspend and Resume Flowchart and Pseudo Code
• REVISION HISTORY
  • Table 36. Document Revision History