1/19
September 2003
Rev. 1.3
M40SZ100Y
M40SZ100W
5V or 3V NVRAM SUPERVISOR FOR LPSRAM
* Contact Local Sales Office
FEATURES SUMMARY
s
CONVERT LOW POWER SRAMs INTO
NVRAMs
s
5V OR 3V OPERATING VOLTAGE
s
PRECISION POWER MONITORING and
POWER SWITCHING CIRCUITRY
s
AUTOMATIC WRITE-PROTECTION WHEN
V
CC
IS OUT-OF-TOLERANCE
s
CHOICE OF SUPPLY VOLTAGES and
POWER-FAIL DESELECT VOLTAGES:
M40SZ100Y: V
CC
= 4.5 to 5.5V;
4.20V
V
PFD
4.50V
M40SZ100W: V
CC
= 2.7 to 3.6V;
2.55V
V
PFD
2.70V
s
RESET OUTPUT (RST) FOR POWER ON
RESET
s
1.25V REFERENCE (for PFI/PFO)
s
LESS THAN 10ns CHIP ENABLE ACCESS
PROPAGATION DELAY (at 5V)
s
OPTIONAL PACKAGING INCLUDES A 28-
LEAD SOIC and SNAPHAT
®
TOP (to be
ordered separately)
s
28-LEAD SOIC PACKAGE PROVIDES
DIRECT CONNECTION FOR A SNAPHAT
TOP WHICH CONTAINS THE BATTERY
s
BATTERY LOW PIN (BL)
Figure 1. 16-pin SOIC Package
Figure 2. 28-pin SOIC Package*
SO16 (MQ)
16
1
SOH28 (MH)
SNAPHAT (SH)
Battery
28
1
M40SZ100Y, M40SZ100W
2/19
TABLE OF CONTENTS
SUMMARY DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Logic Diagram (Figure 3.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Signal Names (Table 1.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
SOIC16 Connections (Figure 4.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
SOIC28 Connections (Figure 5.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Block Diagram (Figure 6.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Hardware Hookup (Figure 7.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Absolute Maximum Ratings (Table 2.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
DC AND AC PARAMETERS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
DC and AC Measurement Conditions (Table 3.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
AC Testing Load Circuit (Figure 8.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
AC Testing Input/Output Waveforms (Figure 9.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Capacitance (Table 4.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
DC Characteristics (Table 5.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
OPERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Data Retention Lifetime Calculation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Power Down Timing (Figure 10.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Power Up Timing (Figure 11.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Power Down/Up AC Characteristics (Table 6.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Power-on Reset Output. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Reset Input (RSTIN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
RSTIN Timing Waveform (Figure 12.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Reset AC Characteristics (Table 7.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Battery Low Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Power-fail Input/Output. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
V
CC
Noise And Negative Going Transients. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Supply Voltage Protection (Figure 13.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
PACKAGE MECHANICAL INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
SNAPHAT® Battery Table (Table 13.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 7
REVISION HISTORY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
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M40SZ100Y, M40SZ100W
SUMMARY DESCRIPTION
The M40SZ100Y/W NVRAM Controller is a self-
contained device which converts a standard low-
power SRAM into a non-volatile memory. A preci-
sion voltage reference and comparator monitors
the V
CC
input for an out-of-tolerance condition.
When an invalid V
CC
condition occurs, the condi-
tioned chip enable output (E
CON
) is forced inactive
to write protect the stored data in the SRAM. Dur-
ing a power failure, the SRAM is switched from the
V
CC
pin to the lithium cell within the SNAPHAT (or
external battery for the 16-lead SOIC) to provide
the energy required for data retention. On a sub-
sequent power-up, the SRAM remains write pro-
tected until a valid power condition returns.
The 28-pin, 330 mil SOIC provides sockets with
gold plated contacts for direct connection to a sep-
arate SNAPHAT
®
housing containing the battery.
The SNAPHAT housing has gold plated pins
which mate with the sockets, ensuring reliable
connection. The housing is keyed to prevent im-
proper insertion. This unique design allows the
SNAPHAT battery package to be mounted on top
of the SOIC package after the completion of the
surface mount process which greatly reduces the
board manufacturing process complexity of either
directly soldering or inserting a battery into a sol-
dered holder. Providing non-volatility becomes a
"SNAP." This feature is also available in the "top-
less" 16-pin SOIC package (MQ).
Insertion of the SNAPHAT housing after reflow
prevents potential battery damage due to the high
temperatures required for device surface-mount-
ing. The SNAPHAT housing is also keyed to pre-
vent reverse insertion.
The 28-pin SOIC and battery packages are
shipped separately in plastic anti-static tubes or in
Tape & Reel form. For the 28-lead SOIC, the bat-
tery/crystal package (e.g., SNAPHAT) part num-
ber is "M4ZXX-BR00SH" (see Table 13, page 17).
Caution: Do not place the SNAPHAT battery top
in conductive foam, as this will drain the lithium
button-cell battery.
Figure 3. Logic Diagram
Note: 1. For 16-pin SOIC package only.
Table 1. Signal Names
Note: 1. For SO16 only.
AI03933
VCC
M40SZ100Y
M40SZ100W
BL
VSS
E
VOUT
PFI
ECON
PFO
RST
RSTIN
VBAT
(1)
E
Chip Enable Input
E
CON
Conditioned Chip Enable Output
RST
Reset Output (Open Drain)
RSTIN
Reset Input
BL
Battery Low Output (Open Drain)
V
OUT
Supply Voltage Output
V
CC
Supply Voltage
V
BAT
(1)
Back-up Supply Voltage
PFI
Power Fail Input
PFO
Power Fail Output
V
SS
Ground
NC
Not Connected Internally
5/19
M40SZ100Y, M40SZ100W
Figure 7. Hardware Hookup
Note: 1. User supplied for the 16-pin package
MAXIMUM RATING
Stressing the device above the rating listed in the
"Absolute Maximum Ratings" table may cause
permanent damage to the device. These are
stress ratings only and operation of the device at
these or any other conditions above those indicat-
ed in the Operating sections of this specification is
not implied. Exposure to Absolute Maximum Rat-
ing conditions for extended periods may affect de-
vice reliability. Refer also to the
STMicroelectronics SURE Program and other rel-
evant quality documents.
Table 2. Absolute Maximum Ratings
Note: 1. Reflow at peak temperature of 215°C to 225°C for < 60 seconds (total thermal budget not to exceed 180°C for between 90 to 120
seconds).
CAUTION: Negative undershoots below 0.3V are not allowed on any pin while in the Battery Back-up mode.
CAUTION: Do NOT wave solder SOIC to avoid damaging SNAPHAT sockets.
AI04767
VCC
E
ECON
VSS
VOUT
VCC
1Mb or 4Mb
LPSRAM
3.0V, 3.3V or 5V
PFI
0.1
µ
F
0.1
µ
F
M40SZ100Y
M40SZ100W
E
PFO
RST
BL
To Microprocessor Reset
To Battery Monitor Circuit
Unregulated
Voltage
Regulator
VCC
VIN
R1
R2
From Microprocessor
RSTIN
VBAT
(1)
To Microprocessor NMI
Symbol
Parameter
Value
Unit
T
STG
Storage Temperature (V
CC
Off)
SNAPHAT
40 to 85
°C
SOIC
55 to 125
°C
T
SLD
(1)
Lead Solder Temperature for 10 seconds
260
°C
V
IO
Input or Output Voltages
0.3 to V
CC
+0.3
V
V
CC
Supply Voltage
M40SZ100Y
0.3 to 7
V
M40SZ100W
0.3 to 4.6
V
I
O
Output Current
20
mA
P
D
Power Dissipation
1
W
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