M27V102
1 Mbit (64Kb x 16) Low Voltage UV EPROM and OTP EPROM
May 1998
1/15
AI01912
16
A0-A15
P
Q0-Q15
VPP
VCC
M27V102
G
E
VSS
16
Figure 1. Logic Diagram
LOW VOLTAGE READ OPERATION:
3V to 3.6V
FAST ACCESS TIME: 90ns
LOW POWER CONSUMPTION:
Active Current 15mA at 5MHz
Standby Current 20
µ
A
PROGRAMMING VOLTAGE: 12.75V
±
0.25V
PROGRAMMING TIME: 100
µ
s/byte (typical)
ELECTRONIC SIGNATURE
Manufacturer Code: 0020h
Device Code: 008Ch
DESCRIPTION
The M27W102 is a low voltage 1 Mbit EPROM
offeredin the two ranges UV (ultra violet erase) and
OTP (one time programmable). It is ideally suited
for microprocessor systems requiring large data or
program storage and is organized as 65,536 words
by 16 bits.
The M27V102 operates in the read mode with a
supply voltage as low as 3V. The decrease in
operating power allows either a reduction of the
size of the battery or an increase in the time be-
tween battery recharges.
The FDIP40W (window ceramic frit-seal package)
has a transparent lid which allows the user to
expose the chip to ultraviolet light to erase the bit
pattern. A new pattern can then be written to the
device by following the programming procedure.
A0 - A15
Address Inputs
Q0 - Q15
Data Outputs
E
Chip Enable
G
Output Enable
P
Program
V
PP
Program Supply
V
CC
Supply Voltage
V
SS
Ground
Table 1. Signal Names
PLCC44 (K)
1
40
FDIP40W (F)
TSOP40 (N)
10 x 14mm
1
40
PDIP40 (B)
Q6
Q5
Q4
Q11
Q8
VSS
Q7
Q10
Q9
A12
A8
A11
A10
A6
A13
A9
VSS
A7
A2
Q1
Q0
A0
G
A1
A5
NC
P
E
Q12
VPP
VCC
Q15
AI01913
M27V102
8
1
2
3
4
5
6
7
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
Q3
Q2
Q14
Q13
A4
A3
40
39
38
37
36
35
34
33
A14
A15
Figure 2A. DIP Pin Connections
AI01914
A14
A11
A7
A3
23
Q6
Q5
Q4
Q3
Q2
NC
A2
Q12
Q8
VSS
NC
Q11
Q10
12
A15
A9
1
Q15
VSS
A12
Q13
A5
44
NC
NC
M27V102
Q14
A13
A4
NC
A6
34
Q1
Q9
A10
A8
Q7
Q0
G
A0
A1
V
PP
E
P
V
CC
Figure 2B. LCC Pin Connections
Warning: NC = Not Connected.
For application where the content is programmed
only one time and erasure is not required, the
M27V102 is offered in PDIP40, PLCC32 and
TSOP40 (10 x 14 mm) packages.
DEVICE OPERATION
The operating modes of the M27V102 are listed in
the Operating Modes table. A single power supply
is required in the read mode. All inputs are TTL
levels except for Vpp and 12V on A9 for Electronic
Signature.
Read Mode
The M27V102 has two control functions, both of
which must be logically active in order to obtaindata
at the outputs. Chip Enable (E) is the power control
and should be used for device selection. Output
Enable (G) is the output control and should be used
to gate data to the output pins, independent of
device selection. Assuming that the addresses are
stable, the address access time (t
AVQV
) is equal to
the delay from E to output (t
ELQV
). Data is available
at the output after a delay of t
OE
from the falling
edge of G, assuming that E has been low and the
addresses have been stable for at least t
AVQV
-
t
GLQV
.
Warning: NC = Not Connected.
DQ6
DQ3
DQ2
DQ13
DQ8
DQ7
DQ10
DQ9
A14
A8
A11
A10
A4
A15
A9
G
A7
A2
DQ1
DQ0
A0
A1
A3
NC
P
E
DQ14
VPP
VCC
DQ15
AI01915
M27V102
(Normal)
10
1
11
20
21
30
31
40
VSS
A12
A6
A13
A5
DQ12
DQ4
DQ11
DQ5
VSS
Figure 2C. TSOP Pin Connections
Warning: NC = Not Connected.
DESCRIPTION (cont'd)
2/15
M27V102
Symbol
Parameter
Value
Unit
T
A
Ambient Operating Temperature
(3)
40 to 125
°
C
T
BIAS
Temperature Under Bias
50 to 125
°
C
T
STG
Storage Temperature
65 to 150
°
C
V
IO
(2)
Input or Output Voltages (except A9)
2 to 7
V
V
CC
Supply Voltage
2 to 7
V
V
A9
(2)
A9 Voltage
2 to 13.5
V
V
PP
Program Supply Voltage
2 to 14
V
Notes: 1. Except for the rating "Operating Temperature Range", stresses above those listed in the Table "Absolute Maximum Ratings"
may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other
conditions above those indicated in the Operating sections of this specification is not i mplied. Exposure to Absolute Maximum
Rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other
relevant quality documents.
2. Minimum DC voltage on Input or Output is 0.5V with possible undershoot to 2.0V for a period less than 20ns. Maximum DC
voltage on Output is V
CC
+0.5V with possible overshoot to V
CC
+2V for a period less than 20ns.
3. Depends on range.
Table 2. Absolute Maximum Ratings
(1)
Mode
E
G
P
A9
V
PP
Q0 - Q15
Read
V
IL
V
IL
V
IH
X
V
CC
or V
SS
Data Output
Output Disable
V
IL
V
IH
X
X
V
CC
or V
SS
Hi-Z
Program
V
IL
X
V
IL
Pulse
X
V
PP
Data Input
Verify
V
IL
V
IL
V
IH
X
V
PP
Data Output
Program Inhibit
V
IH
X
X
X
V
PP
Hi-Z
Standby
V
IH
X
X
X
V
CC
or V
SS
Hi-Z
Electronic Signature
V
IL
V
IL
V
IH
V
ID
V
CC
Codes
Note: X = V
IH
or V
IL
, V
ID
= 12V
±
0.5V
Table 3. Operating Modes
Identifier
A0
Q7
Q6
Q5
Q4
Q3
Q2
Q1
Q0
Hex Data
Manufacturer's Code
V
IL
0
0
1
0
0
0
0
0
20h
Device Code
V
IH
1
0
0
0
1
1
0
0
8Ch
Table 4. Electronic Signature
Standby Mode
The M27V102 has a standby mode which reduces
the active current from 15mA to 20
µ
A with low
voltage operation V
CC
3.6V, see Read Mode DC
Characteristics table for details. The M27V102 is
placed in the standby mode by applying a TTL high
signal to the E input. When in the standby mode,
the outputs are in a high impedance state, inde-
pendent of the G input.
Two Line Output Control
BecauseEPROMs are usually used in larger mem-
ory arrays, this product features a 2 line control
function which accommodates the use of multiple
memory connection. The two line control function
allows:
a. the lowest possible memory power dissipation,
b. complete assurance that output bus contention
will not occur.
3/15
M27V102
AI01822
3V
High Speed
0V
1.5V
2.4V
Standard
0.4V
2.0V
0.8V
Figure 3. AC Testing Input Output Waveform
AI01823B
1.3V
OUT
CL
CL = 30pF for High Speed
CL = 100pF for Standard
CL includes JIG capacitance
3.3k
1N914
DEVICE
UNDER
TEST
Figure 4. AC Testing Load Circuit
High Speed
Standard
Input Rise and Fall Times
10ns
20ns
Input Pulse Voltages
0 to 3V
0.4V to 2.4V
Input and Output Timing Ref. Voltages
1.5V
0.8V and 2V
Table 5. AC Measurement Conditions
Symbol
Parameter
Test Condition
Min
Max
Unit
C
IN
Input Capacitance
V
IN
= 0V
6
pF
C
OUT
Output Capacitance
V
OUT
= 0V
12
pF
Note: 1. Sampled only, not 100% tested.
Table 6. Capacitance
(1)
(T
A
= 25
°
C, f = 1 MHz )
For the most efficient use of thesetwo control lines,
E should be decoded and used as the primary
device selecting function, while G should be made
a common connection to all devices in the array
and connected to the READ line from the system
control bus. This ensures that all deselectedmem-
ory devices are in their low power standby mode
and that the output pins are only active when data
is required from a particular memory device.
System Considerations
The power switching characteristics of Advanced
CMOS EPROMs require careful decoupling of the
devices. The supply current, I
CC
, has three seg-
ments that are of interest to the system designer :
the standby current level, the active current level,
and transient current peaks that are produced by
the falling and rising edges of E. The magnitude of
transientcurrent peaks is dependenton the capaci-
tive and inductive loading of the device at the
output.
The associated transient voltage peaks can be
suppressed by complying with the two line output
control and by properly selected decoupling ca-
pacitors. It is recommended that a 0.1
µ
F ceramic
capacitor be used on every device between V
CC
and V
SS
. This should be a high frequency capacitor
of low inherent inductance and should be placed
as close to the device as possible. In addition, a
4.7
µ
F bulk electrolytic capacitor should be used
between Vcc and V
SS
for every eight devices. The
bulk capacitor should be located near the power
supply connection point. The purpose of the bulk
capacitor is to overcome the voltage drop caused
by the inductive effects of PCB traces.
4/15
M27V102
Symbol
Parameter
Test Condition
Min
Max
Unit
I
LI
Input Leakage Current
0V
V
IN
V
CC
±
10
µ
A
I
LO
Output Leakage Current
0V
V
OUT
V
CC
±
10
µ
A
I
CC
Supply Current
E = V
IL
, G = V
IL
, I
OUT
= 0mA,
f = 5MHz, V
CC
3.6V
15
mA
I
CC1
Supply Current (Standby) TTL
E = V
IH
1
mA
I
CC2
Supply Current (Standby)
CMOS
E > V
CC
0.2V, V
CC
3.6V
20
µ
A
I
PP
Program Current
V
PP
= V
CC
10
µ
A
V
IL
Input Low Voltage
0.3
0.8
V
V
IH
(2)
Input High Voltage
2
V
CC
+ 1
V
V
OL
Output Low Voltage
I
OL
= 2.1mA
0.4
V
V
OH
Output High Voltage TTL
I
OH
= 400
µ
A
2.4
V
Output High Voltage CMOS
I
OH
= 100
µ
A
V
CC
0.7V
V
Notes: 1. V
CC
must be applied simultaneously with or before V
PP
and removed simultaneously or after V
PP
.
2. Maximum DC voltage on Output is V
CC
+0.5V
Table 7. Read Mode DC Characteristics
(1)
(T
A
= 0 to 70
°
C or 40 to 85
°
C; V
CC
= 3.3V
±
10%; V
PP
= V
CC
)
Symbol
Alt
Parameter
Test Condition
M27V102
Unit
-90
(3)
-100
Min
Max
Min
Max
t
AVQV
t
ACC
Address Valid to Output Valid
E = V
IL
, G = V
IL
90
100
ns
t
ELQV
t
CE
Chip Enable Low to Output Valid
G = V
IL
90
100
ns
t
GLQV
t
OE
Output Enable Low to Output Valid
E = V
IL
45
50
ns
t
EHQZ
(2)
t
DF
Chip Enable High to Output Hi-Z
G = V
IL
0
30
0
30
ns
t
GHQZ
(2)
t
DF
Output Enable High to Output Hi-Z
E = V
IL
0
30
0
30
ns
t
AXQX
t
OH
Address Transition to Output Transition
E = V
IL
, G = V
IL
0
0
ns
Notes: 1. V
CC
must be applied simultaneously with or before V
PP
and removed simultaneously with or after V
PP.
2. Sampled only, not 100% tested.
3. Speed obtained with High Speed AC measurement conditions.
Table 8A. Read Mode AC Characteristics
(1)
(T
A
= 0 to 70
°
C or 40 to 85
°
C; V
CC
= 3.3V
±
10%; V
PP
= V
CC
)
5/15
M27V102
Symbol
Alt
Parameter
Test Condition
M27V102
Unit
-120
-150
-200
Min
Max
Min
Max
Min
Max
t
AVQV
t
ACC
Address Valid to Output Valid
E = V
IL
, G = V
IL
120
150
200
ns
t
ELQV
t
CE
Chip Enable Low to Output Valid
G = V
IL
120
150
200
ns
t
GLQV
t
OE
Output Enable Low to Output Valid
E = V
IL
50
60
90
ns
t
EHQZ
(2)
t
DF
Chip Enable High to Output Hi-Z
G = V
IL
0
40
0
50
0
70
ns
t
GHQZ
(2)
t
DF
Output Enable High to Output Hi-Z
E = V
IL
0
40
0
50
0
70
ns
t
AXQX
t
OH
Address Transition to Output
Transition
E = V
IL
, G = V
IL
0
0
0
ns
Notes: 1. V
CC
must be applied simultaneously with or before V
PP
and removed simultaneously with or after V
PP.
2. Sampled only, not 100% tested.
Table 8B. Read Mode AC Characteristics
(1)
(T
A
= 0 to 70
°
C or 40 to 85
°
C; V
CC
= 3.3V
±
10%; V
PP
= V
CC
)
AI00705B
tAXQX
tEHQZ
A0-A15
E
G
Q0-Q15
tAVQV
tGHQZ
tGLQV
tELQV
VALID
Hi-Z
VALID
Figure 5. Read Mode AC Waveforms
Programming
The M27V102 has been designed to be fully com-
patible with the M27C1024 and has the same
elecronic signature. As a result the M27V102 can
be programmed as the M27C1024 on the same
programming equipments applying 12.75V on V
PP
and 6.25V on V
CC
by the use of the same PRESTO
II algorithm. When delivered (and after each '1's
erasure for UV EPROM), all bits of the M27V102
are in the '1' state. Data is introduced by selectively
programming '0's into the desired bit locations.
Although only '0's will be programmed, both '1's
and '0's can be present in the data word. The only
way to change a '0' to a '1' is by die exposure to
ultraviolet light (UV EPROM). The M27V102 is in
the programming mode when V
PP
input is at
12.75V, E is at V
IL
and P is pulsed to V
IL
. The data
to be programmed is applied to 16 bits in parallel
to the data output pins. The levels required for the
address and data inputs are TTL. V
CC
is specified
to be 6.25V
±
0.25V.
6/15
M27V102
Symbol
Parameter
Test Condition
Min
Max
Unit
I
LI
Input Leakage Current
0
V
IN
V
IH
±
10
µ
A
I
CC
Supply Current
50
mA
I
PP
Program Current
E = V
IL
50
mA
V
IL
Input Low Voltage
0.3
0.8
V
V
IH
Input High Voltage
2
V
CC
+ 0.5
V
V
OL
Output Low Voltage
I
OL
= 2.1mA
0.4
V
V
OH
Output High Voltage TTL
I
OH
= 400
µ
A
2.4
V
V
ID
A9 Voltage
11.5
12.5
V
Note: 1. V
CC
must be applied simultaneously with or before V
PP
and removed simultaneously with or after V
PP
.
Table 9. Programming Mode DC Characteristics
(1)
(T
A
= 25
°
C; V
CC
= 6.25V
±
0.25V; V
PP
= 12.75V
±
0.25V)
Symbol
Alt
Parameter
Test Condition
Min
Max
Unit
t
AVPL
t
AS
Address Valid to Program Low
2
µ
s
t
QVPL
t
DS
Input Valid to Program Low
2
µ
s
t
VPHPL
t
VPS
V
PP
High to Program Low
2
µ
s
t
VCHPL
t
VCS
V
CC
High to Program Low
2
µ
s
t
ELPL
t
CES
Chip Enable Low to Program Low
2
µ
s
t
PLPH
t
PW
Program Pulse Width
95
105
µ
s
t
PHQX
t
DH
Program High to Input Transition
2
µ
s
t
QXGL
t
OES
Input Transition to Output Enable
Low
2
µ
s
t
GLQV
t
OE
Output Enable Low to Output Valid
100
ns
t
GHQZ
(2)
t
DFP
Output Enable High to Output Hi-Z
0
130
ns
t
GHAX
t
AH
Output Enable High to Address
Transition
0
ns
Notes: 1. V
CC
must be applied simultaneously with or before V
PP
and removed simultaneously with or after V
PP
.
2. Sampled only, not 100% tested.
Table 10. Programming Mode AC Characteristics
(1)
(T
A
= 25
°
C; V
CC
= 6.25V
±
0.25V; V
PP
= 12.75V
±
0.25V)
7/15
M27V102
tAVPL
VALID
AI00706
A0-A15
Q0-Q15
VPP
VCC
P
G
DATA IN
DATA OUT
E
tQVPL
tVPHPL
tVCHPL
tPHQX
tPLPH
tGLQV
tQXGL
tELPL
tGHQZ
tGHAX
PROGRAM
VERIFY
Figure 6. Programming and Verify Modes AC Waveforms
PRESTO II Programming Algorithm
PRESTO II Programming Algorithm allows pro-
gramming of the whole array with a guaranteed
margin, in a typical time of 6.5 seconds. Program-
ming with PRESTO II consists of applying a se-
quenceof 100
µ
s program pulses to each word until
a correct verify occurs (see Figure 7). During pro-
gramming and verify operation, a MARGIN MODE
circuit is automaticallyactivated in order to guaran-
tee that each cell is programmed with enough
margin. No overprogram pulse is applied since the
verify in MARGIN MODE at V
CC
much higher than
3.6V provides necessary margin to each pro-
grammed cell.
Program Inhibit
Programming of multiple M27V102s in parallel with
different data is also easily accomplished. Except
for E, all like inputs including G of the parallel
M27V102 may be common. A TTL low level pulse
applied to a M27V102'sP input, with E low and V
PP
at 12.75V, will program that M27V102. A high level
E input inhibits the other M27V102s from being
programmed.
Program Verify
A verify (read) should be performed on the pro-
grammed bits to determine that they were correctly
programmed. The verify is accomplished with E
AI00707C
n = 0
Last
Addr
VERIFY
P = 100
µ
s Pulse
++n
= 25
++ Addr
VCC = 6.25V, VPP = 12.75V
FAIL
CHECK ALL WORDS
1st: VCC = 6V
2nd: VCC = 4.2V
YES
NO
YES
NO
YES
NO
Figure 7. Programming Flowchart
8/15
M27V102
and G at V
IL
, P at V
IH
, V
PP
at 12.75V and V
CC
at
6.25V.
On-Board Programming
The M27V102 can be directly programmed in the
application circuit. See the relevant Application
Note AN620.
Electronic Signature
The Electronic Signature (ES) mode allows the
reading out of a binary code from an EPROM that
will identify its manufacturer and type. This mode
is intended for use by programming equipment to
automatically match the device to be programmed
with its correspondingprogramming algorithm. The
ES mode is functional in the 25
°
C
±
5
°
C ambient
temperature range that is required when program-
ming the M27V102. To activate the ES mode, the
programming equipmentmust force 11.5Vto 12.5V
on address line A9 of the M27V102 with V
PP
= V
CC
= 5V. Two identifier bytes may then be sequenced
from the device outputs by togglingaddress line A0
from V
IL
to V
IH
. All other address lines must be held
at V
IL
during Electronic Signature mode. Byte 0
(A0=V
IL
) represents the manufacturer code and
byte 1 (A0=V
IH
) the device identifier code. For the
STMicroelectronics M27V102, these two iden-tifier
bytes are given in Table 4 and can be read-out on
outputs Q0 to Q7. Note that the M27V102 and
M27C1024 have the same identifier bytes.
ERASURE OPERATION (applies to UV EPROM)
The erasure characteristics of the M27V102is such
that erasure begins when the cells are exposed to
light with wavelengths shorter than approximately
4000 Å. It should be noted that sunlight and some
type of fluorescent lamps have wavelengths in the
3000-4000 Å range. Research shows that constant
exposure to room level fluorescent lighting could
erase a typical M27V102 in about 3 years, while it
would take approximately 1 week to cause erasure
when exposed to direct sunlight. If the M27V102
is to be exposed to these types of lighting condi-
tions for extended periods of time, it is suggested
that opaque labels be put over the M27V102 win-
dow to prevent unintentional erasure. The recom-
mended erasure procedure for the M27V102 is
exposure to short wave ultraviolet light which has
wavelength 2537 Å. The integrated dose (i.e. UV
intensity x exposure time) for erasure should be a
minimum of 15 W-sec/cm
2
. The erasure time with
this dosage is approximately 15 to 20 minutes
using an ultravioletlamp with 12000
µ
W/cm
2
power
rating. The M27V102 should be placed within 2.5
cm (1 inch) of the lamp tubes during the erasure.
Some lamps have a filter on their tubes which
should be removed before erasure.
9/15
M27V102
ORDERING INFORMATION SCHEME
Note: 1. High Speed, see AC Characteristics section for further information.
For a list of available options (Speed, Package, etc...) or for further informationon any aspect of this device,
please contact the STMicroelectronics Sales Office nearest to you.
Speed
-90
(1)
90 ns
-100
100 ns
-120
120 ns
-150
150 ns
-200
200 ns
Package
F
FDIP40W
B
PDIP40
K
PLCC44
N
TSOP40
8 x 14mm
Temperature Range
1
0 to 70
°
C
6
40 to 85
°
C
Option
TR
Tape & Reel
Packing
Example:
M27V102
-90
K
1
TR
10/15
M27V102
FDIP40W - 40 pin Ceramic Frit-seal DIP, with window
FDIPW-a
A3
A1
A
L
B1
B
e
D
S
E1
E
N
1
C
eA
D2
eB
A2
Symb
mm
inches
Typ
Min
Max
Typ
Min
Max
A
5.72
0.225
A1
0.51
1.40
0.020
0.055
A2
3.91
4.57
0.154
0.180
A3
3.89
4.50
0.153
0.177
B
0.41
0.56
0.016
0.022
B1
1.45
0.057
C
0.23
0.30
0.009
0.012
D
51.79
52.60
2.039
2.071
D2
48.26
1.900
E
15.24
0.600
E1
13.06
13.36
0.514
0.526
e
2.54
0.100
eA
14.99
0.590
eB
16.18
18.03
0.637
0.710
L
3.18
0.125
S
1.52
2.49
0.060
0.098
7.62
0.300
4
°
11
°
4
°
11
°
N
40
40
Drawing is not to scale.
11/15
M27V102
PDIP40 - 40 pin Plastic DIP, 600 mils body width
PDIP
A2
A1
A
L
B1
B
e1
D
S
E1
E
N
1
C
eA
eB
D2
Symb
mm
inches
Typ
Min
Max
Typ
Min
Max
A
4.45
0.175
A1
0.64
0.38
0.025
0.015
A2
3.56
3.91
0.140
0.154
B
0.38
0.53
0.015
0.021
B1
1.14
1.78
0.045
0.070
C
0.20
0.31
0.008
0.012
D
51.78
52.58
2.039
2.070
D2
48.26
1.900
E
14.80
16.26
0.583
0.640
E1
13.46
13.99
0.530
0.551
e1
2.54
0.100
eA
15.24
0.600
eB
15.24
17.78
0.600
0.700
L
3.05
3.81
0.120
0.150
S
1.52
2.29
0.060
0.090
0
°
15
°
0
°
15É
N
40
40
Drawing is not to scale.
12/15
M27V102
PLCC44 - 44 lead Plastic Leaded Chip Carrier, square
PLCC
D
Ne
E1 E
1 N
D1
Nd
CP
B
D2/E2
e
B1
A1
A
R
0.51 (.020)
1.14 (.045)
F
A2
Symb
mm
inches
Typ
Min
Max
Typ
Min
Max
A
4.20
4.70
0.165
0.185
A1
2.29
3.04
0.090
0.120
A2
0.51
0.020
B
0.33
0.53
0.013
0.021
B1
0.66
0.81
0.026
0.032
D
17.40
17.65
0.685
0.695
D1
16.51
16.66
0.650
0.656
D2
14.99
16.00
0.590
0.630
E
17.40
17.65
0.685
0.695
E1
16.51
16.66
0.650
0.656
E2
14.99
16.00
0.590
0.630
e
1.27
0.050
F
0.00
0.25
0.000
0.010
R
0.89
0.035
N
44
44
CP
0.10
0.004
Drawing is not to scale.
13/15
M27V102
TSOP40 - 40 lead Plastic Thin Small Outline, 10 x 14mm
TSOP-a
D1
E
1
N
CP
B
e
A2
A
N/2
D
DIE
C
L
A1
Symb
mm
inches
Typ
Min
Max
Typ
Min
Max
A
1.20
0.047
A1
0.05
0.15
0.002
0.006
A2
0.95
1.05
0.037
0.041
B
0.17
0.27
0.007
0.011
C
0.10
0.21
0.004
0.008
D
13.80
14.20
0.543
0.559
D1
12.30
12.50
0.484
0.492
E
9.90
10.10
0.390
0.398
e
0.50
0.020
L
0.50
0.70
0.020
0.028
0
°
5
°
0
°
5
°
N
40
40
CP
0.10
0.004
Drawing is not to scale.
14/15
M27V102
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
by implication or otherwise under any patent or patent rights of STMicroelectronics. Spec ifications mentioned in this publication are subject to
change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.
The ST logo is a registered trademark of STMicroelectronics.
©
1998 STMicroelectronics - All Rights Reserved
STMicroelectronics GROUP OF COMPANIES
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15/15
M27V102
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