1/17

L6565

January 2003

QUASI-RESONANT (QR) ZERO-VOLTAGE-
SWITCHING (ZVS) TOPOLOGY

LINE FEED FORWARD TO DELIVER
CONSTANT POWER vs. MAINS CHANGE

FREQUENCY FOLDBACK FOR OPTIMUM
STANDBY EFFICIENCY

PULSE-BY-PULSE & HICCUP-MODE OCP

ULTRA-LOW START-UP (< 70µA) AND
QUIESCENT CURRENT (< 3.5mA)

DISABLE FUNCTION (ON/OFF CONTROL)

1% PRECISION (@ T

= 25°C) INTERNAL

REFERENCE VOLTAGE

±400mA TOTEM POLE GATE DRIVER WITH
UVLO PULL-DOWN

BLUE ANGEL, ENERGY STAR, ENERGY
2000 COMPLIANT

APPLICATIONS

TV/MONITOR SMPS

AC-DC ADAPTERS/CHARGERS

DIGITAL CONSUMER

PRINTERS, FAX MACHINES,
PHOTOCOPIERS AND SCANNERS

DESCRIPTION

The L6565 is a current-mode primary controller IC,
specifically designed to build offline Quasi-resonant
ZVS (Zero Voltage Switching at switch turn-on) fly-
back converters.

Quasi-resonant operation is achieved by means of a
transformer demagnetization sensing input that trig-
gers MOSFET's turn-on.

DIP8(Minidip)

SO-8

ORDERING NUMBERS:

L6565N L6565D

QUASI-RESONANT SMPS CONTROLLER

BLOCK DIAGRAM

REF2

VOLTAGE

REGULATOR

INTERNAL

SUPPLY

2.5V

DRIVER

ZERO CURRENT

DETECTOR

2.1V
1.6V

ZCD

INV

COMP

VFF

GND

20V

40K

5pF

BLANKING

LINE VOLTAGE

FEEDFORWARD

Hiccup-mode

OCP

DISABLE

STARTER

2 V

Hiccup-mode

OCP

Starter

STOP

UVLO

Blanking

START

L6565

2/17

DESCRIPTION (continued)

Converter's power capability variations with the mains voltage are compensated by line voltage feedforward.
At light load the device features a special function that automatically lowers the operating frequency still main-
taining the operation as close to ZVS as possible. In addition to very low start-up and quiescent currents, this
feature helps keep low the consumption from the mains at light load and be Blue Angel and Energy Star com-
pliant.
The IC includes also a disable function, an on-chip filter on current sense, an error amplifier with a precise ref-
erence voltage for primary regulation and an effective two-level overcurrent protection.

PIN CONNECTION (Top view, Minidip and SO8)

PIN DESCRIPTION

N°

Name

Function

INV

Inverting input of the error amplifier. The information on the output voltage is fed into the pin
through either a resistor divider (primary regulation) or an optocoupler (secondary feedback).
This pin can be grounded in some secondary feedback schemes (see pin 2).

COMP

Output of the error amplifier. Typically, a compensation network is placed between this pin and
the INV pin to achieve stability and good dynamic performance of the voltage control loop. With
secondary feedback, the pin can be also driven directly by an optocoupler to control PWM by
modulating the current sunk from the pin (with the INV pin grounded).

VFF

Line voltage feedforward. The information on the converter's input voltage is fed into the pin
through a resistor divider and is used to change the setpoint of the pulse-by-pulse current
limitation (the higher the voltage, the lower the setpoint). If this function is not desired the pin will
be grounded and the current limitation setpoint will be maximum.

Input to the PWM comparator. The primary current is sensed through a resistor, the resulting
voltage is applied to this pin and compared with an internal reference to determine MOSFET's
turn-off. The internal reference is clamped at a value, which defines the pulse-by-pulse current
limitation setpoint, depending on the voltage at pin VFF. If the signal at the pin CS exceeds 2 V,
the gate driver will be disabled (Hiccup-mode OCP).

ZCD

Transformer's demagnetization sensing input for Quasi-Resonant operation. Alternately,
synchronization input for an external signal. A negative-going edge triggers MOSFET's turn-on.
The trigger circuit is blanked for a minimum of 3.5 µs after MOSFET turn-off, for safe operation
under short circuit conditions and frequency foldback. If the pin is grounded the IC will be
disabled.

GND

Ground. Current return for both the signal part of the IC and the gate driver.

Gate driver output. The totem pole output stage is able to drive power MOSFET's and IGBT's
with a peak current of 400 mA (source and sink).

Vcc

Supply Voltage of both the signal part of the IC and the gate driver. An electrolytic capacitor is
connected between this pin and ground. A resistor connected from this pin to the converter's
input bulk capacitor will be typically used to start up the device.

ZCD

INV

COMP

VFF

Vcc

GND

3/17

L6565

THERMAL DATA

ABSOLUTE MAXIMUM RATINGS

Symbol

Parameter

SO8

Minidip

Unit

j-amb

Max. Thermal Resistance, Junction-to-ambient

150

100

°C/W

Symbol

Pin

Parameter

Value

Unit

Vcc

+ I

Output Totem Pole Peak Current (2 µs)

700

INV, COMP,

VFF, CS

1, 2, 3 4

Analog Inputs & Outputs

-0.3 to 7

ZCD

Zero Current Detector

50 (source)

-10 (sink)

tot

Power Dissipation @T

amb

= 50°C

(Minidip)

(SO8)

0.65

Junction Temperature Operating range

-40 to 150

°C

stg

Storage Temperature

-55 to 150

°C

ELECTRICAL CHARACTERISTCS
(T

= -25 to 125°C, V

= 12V, C

= 1nF; unless otherwise specified)

Symbol

Parameter

Test Condition

Min.

Typ.

Max.

Unit

SUPPLY VOLTAGE

Operating range

After turn-on

10.3

CCOn

Turn-on threshold

12.5

13.5

14.5

CCOff

Turn-off threshold

8.7

9.5

10.3

Hys

Hysteresis

3.65

4.3

Zener Voltage

= 25 mA

SUPPLY CURRENT

start-up

Start-up Current

Before turn-on, V

= 12V

µA

Quiescent Current

After turn-on

2.3

3.5

Operating Supply Current

@ 70 kHz

3.5

Quiescent Current

During Hiccup-mode OCP

1.6

3.5

Quiescent Current

ZCD

< V

DIS

, V

CCOff

1.4

2.1

LINE FEEDFORWARD

VFF

Input Bias Current

VFF

= 0 to 3 V

-1

µA

VFF

Operating Range

0 to 3

Gain

VFF

= 1.5V, V

COMP

= 4V

0.16

ERROR AMPLIFIER

INV

Voltage Feedback Input
Threshold

amb

= 25°C

2.465

2.5

2.535

12V < V

< 18V

2.44

2.56

Line Regulation

Vcc = 12 to 18V

INV

Input Bias Current

-0.1

-1

µA

L6565

4/17

Voltage Gain

Open loop

Gain-Bandwidth Product

MHz

COMP

Source Current

COMP

= 4V, V

INV

= 2.4 V

-2

-3.5

-5

Sink Current

COMP

= 4V, V

INV

= 2.6 V

2.5

4.5

COMP

Upper Clamp Voltage

SOURCE

= 0.5 mA

5.5

Lower Clamp Voltage

SINK

= 0.5 mA

2.25

2.55

CURRENT SENSE COMPARATOR

Input Bias Current

= 0

-0.05

-1

µA

d(H-L)

Delay to Output

200

450

CSx

Current Sense Reference Clamp

COMP

= Upper clamp, V

VFF

= 0V

1.28

1.4

1.5

COMP

= Upper clamp, V

VFF

= 1.5V

0.62

0.7

0.78

COMP

= Upper clamp, V

VFF

= 3V

0.2

CSdis

Hiccup-mode OCP level

1.85

2.0

2.2

ZERO CURRENT DETECTOR/ SYNCHRONIZATION

ZCDH

Upper Clamp Voltage

ZCD

= 3mA

4.7

5.2

6.1

ZCDL

Lower Clamp Voltage

ZCD

= - 3mA

0.3

0.65

ZCDA

Arming Voltage
(positive-going edge)

(1)

2.1

ZCDT

Triggering Voltage
(negative-going edge)

1.6

ZCDb

Input Bias Current

ZCD

= 1 to 4.5 V

µA

ZCDsrc

Source Current Capability

-3

-10

ZCDsnk

Sink Current Capability

DIS

Disable Threshold

150

200

250

ZCDr

Restart Current After Disable

ZCD

< V

DIS

, Vcc > Vcc

off

-70

-150

-230

µA

BLANK

Blanking time after pin 7 high-to-
low transition

COMP

3.2 V

3.5

µs

COMP

= 2.5 V

START TIMER

START

Start Timer period

250

400

550

µs

GATE DRIVER

Dropout Voltage

GDsource

= 200mA

1.2

GDsource

= 20mA

0.7

GDsink

= 200mA

GDsink

= 20mA

0.3

Current Fall Time

100

Current Rise Time

100

GDoff

sink current

Vcc = 4 V, V

= 1 V

(1) Parameters guaranteed by design, not tested in production.

ELECTRICAL CHARACTERISTCS (continued)
(T

= -25 to 125°C, V

= 12V, C

= 1nF; unless otherwise specified)

Symbol

Parameter

Test Condition

Min.

Typ.

Max.

Unit

5/17

L6565

Figure 1. Supply current vs. Supply voltage

Figure 2. Start-up & UVLO vs. Temperature

Figure 3. Feedback reference vs. Temperature

Figure 4. Line feedforward characteristics

Figure 5. Pin 2 (COMP) V-I characteristics

Figure 6. ZCD blanking time vs. COMP voltage

(V)

0.005

0.01

0.05

0.1

0.5

(mA)

CL = 1nF
f = 70KHz
TA = 25°C

T (°C)

CC-ON

(V)

CC-OFF

(V)

-25

100

125

-50

100

2.46

2.48

2.50

T (°C)

REF

(V)

D94IN048A

csx

[V]

0.5

1.5

2.5

3.5

0.5

1.5

VFF

[V]

COMP

= 2.5V

3.0 V

3.5 V

4.0 V

4.5 V

5.0 V

Upper clamp

Regulation

range

COMP

[V]

COMP

[mA]

Tj = 25 °C
Vpin1 = 0

BLANK

[µs]

COMP

[V]

Tj = 25 °C

L6565

6/17

Figure 7. Gate-drive output saturation

Figure 8. Gate-drive output saturation

Figure 9. IC consumption vs. temperature

Figure 10. Zener voltage at Vcc pin vs. Tj

Figure 11. Start-up timer period vs. Tj

pin7

[V]

100

200

300

400

500

0.5

1.5

2.5

[mA]

Tj = 25 °C

Vcc = 14.5 V

SINK

pin7

[V]

100

200

300

400

500

-2.5

-2

-1.5

-1

-0.5

[mA]

Tj = 25 °C

Vcc = 14.5 V

SOURCE

Vcc - 0.5

Vcc - 1.0

Vcc - 1.5

Vcc - 2.0

Vcc - 0.5

Icc [mA]

-50

100

150

0.02

0.05

0.1

0.2

0.5

Tj [°C]

Quiescent

Before Start-up

Vcc=12V

Vz [V]

-50

100

150

Tj [°C]

START

[µs]

-50

100

150

250

300

350

400

450

Tj [°C]

Vcc=12V

7/17

L6565

APPLICATION INFORMATION

Quasi-resonant operation in offline flyback converters lies in synchronizing MOSFET's turn-on to the transform-
er's demagnetization. Detecting the resulting negative-going edge of the voltage across any winding of the
transformer can do this. The L6565 is provided with a dedicated pin that allows doing the job with a very simple
interface, just one resistor.

Variable frequency operation - as a result of different operating conditions in terms of input voltage and output
current - is inherent in such functionality. The system always works close to the boundary between DCM (Dis-
continuous Conduction Mode) and CCM (Continuous Conduction Mode) operation of the transformer. The op-
eration is then identical to that of the so-called self-oscillating or Ringing Choke Converter (RCC).

Detailed Device Description

Internal Supply Block (see fig. 12)

A linear voltage regulator supplied by V

(pin 8) generates an internal 7V rail used for supplying the entire IC,

except for the gate driver that is supplied directly from Vcc. In addition, a bandgap circuit generates a precise
internal reference (2.5V±1% @ 25°C) used by the control loop to ensure a good regulation with primary feed-
back technique.

In figure 12 it is also shown the undervoltage lockout (UVLO) comparator with hysteresis used to enable the
chip as long as the Vcc voltage is high enough to ensure a reliable operation.

Figure 12. L6565 internal supply block

REF.

UVLO

2.5V

7V bus

LIN.

REG.

Vcc

L6565

8/17

Zero Current Detection and Triggering Block (see fig. 13):

The Zero Current Detection (ZCD) block switches on the external MOSFET if a negative-going edge falling be-
low 1.6 V is applied to the input (pin 5, ZCD). However, to ensure high noise immunity, the triggering block must
be armed first: prior to falling below 1.6V, the voltage on pin 5 must experience a positive-going edge exceeding
2.1 V.

This feature is typically used to detect transformer demagnetization for QR operation, where the signal for the
ZCD input is obtained from the transformer's auxiliary winding used also to supply the IC. Alternatively, this can
be used to synchronize MOSFET's turn-on to the negative-going edge of an external clock signal, in case the
device is not required to work in QR mode but as a standard PWM controller in a synchronized system (e.g.
monitor SMPS).

The triggering block is blanked for a certain time after the MOSFET has been turned off. This has two goals:
first, to prevent any negative-going edge that follows leakage inductance demagnetization from triggering the
ZCD circuit erroneously; second, to realize the Frequency Foldback function (see the relevant description).

Figure 13. Zero Current Detection and Triggering Block; Disable and Frequency Foldback Blocks

A circuit is needed that turns on the external MOSFET at start-up since no signal is coming from the ZCD pin.
This is realized with an internal starter, which forces the driver to deliver a pulse to the gate of the MOSFET.

To minimize the external interface with the synchronization source (either the auxiliary winding or an external
clock), the voltage at the pin is both top and bottom limited by a double clamp, as illustrated in the internal dia-
gram of the ZCD block of figure 13. The upper clamp is typically located at 5.2 V, while the lower clamp is at
one V

above ground. The interface will then be made by just one resistor that has to limit the current sourced

by and sunk from the pin within the rated capability of the internal clamps.

Disable Block (see fig. 13):

The ZCD pin is used also to activate the Disable Block. If the voltage on the pin is taken below 150 mV the de-
vice will be shut down. To do so, it is necessary to override the source capability (10 mA max.) of the internal
lower clamp. While in disable, the current consumption of the IC will be reduced. To re-enable device operation,
the pull-down on the pin must be released.

Frequency Foldback Block (see fig. 13):

To prevent the switching frequency from reaching too high values, which is a typical drawback of QR operation,

1.6V
2.1V

0.2V
0.3V

DISABLE

DRIVER

5.2V

+Vin

ZCD

PWM

0µ

BLANKING

TIME

2.5V

INV

COMP

E/A

to line

FFWD

L6565

STARTER

MONO

STABLE

ZCD

starter STOP

blanking
START

9/17

L6565

the L6565 puts a limit on the minimum OFF-time of the switch. This is done by blanking the triggering block of
the ZCD circuit as mentioned before. The duration of the blanking time (3.5µs min.) is a function of the error
amplifier output VCOMP, as shown in the diagram of figure 6.

If the load current and the input voltage are such that the switch OFF-time falls below the minimum blanking
time of 3.5µs, the system will enter the "Frequency Foldback" mode, a sort of "ringing cycle skipping" illustrated
schematically in figure 14.

Figure 14. Frequency foldback: ringing cycle skipping as the load is progressively reduced

In this mode, uneven switching cycles may be observed under some line/load conditions, due to the fact that
the OFF-time of the MOSFET is allowed to change with discrete steps (2·Tv), while the OFF-time needed for
cycle-by-cycle energy balance may fall in between. Thus one or more longer switching cycles will be compen-
sated by one or more shorter ones and vice versa. However, this mechanism is absolutely normal and there is
no appreciable effect on the performance of the converter or on its output voltage.

BLANKmin

BLANK

= P

in'

(limit condition)

= P

in''

< P

in'

= P

in'''

< P

in''

BLANK

Figure 15. Frequency Foldback: qualitative

frequency dependence on power
throughput

Further load reductions involve lower values for
VCOMP, which increases the blanking time. There-
fore, more and more ringing cycles will be skipped.
When the load is low enough, so many ringing cycles
need to be skipped that their amplitude becomes
very small and they can no longer trigger the ZCD cir-
cuit. In that case the internal starter of the IC will be
activated, resulting in burst-mode operation: a series
of few switching cycles spaced out by long periods
where the MOSFET is in OFF state.

Voltage Feedforward block (see fig. 17b):

The power that QR flyback converters with a fixed
overcurrent setpoint (like fixed-frequency systems)
are able to deliver changes with the input voltage
considerably. With wide-range mains, at maximum
line it can be more than twice the value at minimum
line, as shown by the upper curve in the diagram of
figure 16. The L6565 has the Line Feedforward func-
tion available to solve this issue.

Figure 16. Typical power capability change vs.

input voltage in ZVS QR flyback
converters

00000000

BURST MO

without frequency foldback

with frequency foldback

Vin fixed

inmin

l
i
m

@ V

lim

@ V

min

1.5

2.5

3.5

0.5

1.5

2.5

system optimally

compensated

system not

compensated

L6565

10/17

It acts on the clamp level of the control voltage V

csx

, that is on the overcurrent setpoint, so that it is a function

of the converter's input voltage sensed through a dedicated pin (#3, VFF): the higher the input voltage, the lower
the setpoint. This is illustrated in the diagram of figure 17a that shows the relationship between the voltage at
the pin VFF and V

csx

(with the error amplifier saturated high in the attempt of keeping output voltage regulation).

The schematic in figure 17b shows also how the function is included in the control loop. With a proper selection
of the external divider R1-R2 it is possible to achieve the optimum compensation described by the lower curve
in the diagram of figure 16.

In applications where this function is not wanted, e.g. because of a narrow input voltage range, the VFF pin can
be simply grounded, thus saving the resistor divider. The overcurrent setpoint will be then fixed at the maximum
value of about 1.4V (1.5V max.).

Line Feedforward is also beneficial to other characteristics of quasi-resonant converters: it improves their input
ripple rejection ability and limits the variation of the power stage's small-signal gain versus the line voltage.

Figure 17. a) Overcurrent setpoint vs. VFF voltage; b) Line Feedforward function block

csx

[V]

0.5

1.5

2.5

3.5

0.5

1.5

VFF

[V]

COMP

= Upper clamp

E/A

PWM

VOLTAGE

FEED

FORWARD

+Vin

2.5V

DRIVER

INV

COMP

VFF

L6565

2 V

Hiccup

DISABLE

ZCD

STARTER

ZCD

(reset-dominant)

starter STOP

11/17

L6565

Error Amplifier Block (see fig. 17b):

The Error Amplifier (E/A) inverting input is used in primary feedback technique to compare a partition of the volt-
age generated by the auxiliary winding with the internal reference, to achieve converter's output voltage regu-
lation (see "Application Ideas", fig. 24). With secondary feedback (typically using a TL431 at the secondary side
and an optocoupler to transfer output voltage information to the primary side through the isolation barrier) the
E/A can be used as an inverting level-shifter to achieve negative feedback and shape the loop gain (see "Ap-
plication Ideas", fig. 23).

The E/A output is used typically for control loop compensation, realized with an RC network connected to the
inverting input. With other secondary feedback techniques, the output is driven directly by an emitter-grounded
optocoupler to modulate the duty cycle (the inverting input will be grounded in that case - see figure 23 in "Ap-
plication Ideas").

Current Comparator, PWM Latch and Hiccup-mode OCP (see fig. 17b):

The current comparator senses the voltage across the current sense resistor (Rs) and, by comparing it with the
programming signal delivered by the feedforward block, determines the exact time when the external MOSFET
is to be switched off. The PWM latch avoids spurious switching of the MOSFET, which might result from the
noise generated ("double-pulse suppression").

A comparator senses the voltage on the current sense input and disables the gate driver if the voltage at the pin
exceeds 2 V. Such anomalous condition is typically generated by a short circuit on the secondary rectifier or on
the secondary winding. To re-enable the driver, first the IC must be turned off and then can be restarted, that is
the Vcc voltage must fall below the UVLO threshold.

When the gate driver is disabled the quiescent current of the IC is unchanged and, since no energy is coming
from the self-supply circuit, the Vcc capacitor will be discharged below the UVLO threshold after some time.
Then the device will initiate a new start-up cycle. In case of failure of the secondary diode the resulting behavior
will be a low-frequency intermittent operation (Hiccup-mode operation), with very low stress on the power circuit.

Gate Driver (see fig. 18):

A totem pole buffer, with 400mA source and sink capability, drives the external MOSFET. It is made up of a
high-side NPN Darlington and a low-side MOSFET. In this way there is no need of an external diode clamp to
prevent the voltage at the gate drive output (pin 7, GD) from being pulled too negative.

An internal pull-down circuit holds the output low when the device is in UVLO conditions, to ensure that the ex-
ternal MOSFET cannot be turned on accidentally (e.g. at power-on).

Figure 18. Gate driver with UVLO pull-down

UVLO

GND

DRIVER

Vcc

L6565

L6565

12/17

TYPICAL APPLICATIONS

Figure 19. 50W Wide Range Mains SMPS for 14" TV

Figure 20. 40W Wide Range Mains SMPS for inkjet printer

TRANSFORMER SPECS:

CORE: ETD29x16x10, N67 material or equivalent

1 mm air gap for a primary inductance of 285 µH

N1: 48 T (24T+24T series connected), 2xAWG28

(

0.37 mm)

N2: 31 T, AWG28
N3: 5 T, AWG28
Naux: 5 T, AWG32 (

0.24 mm)

IC1

L6565

105 V

0.35 A

B1 2KBP04M

150

400 V

180 pF

630V

R6 100

25V

STP7NB80FI

R8 22

1N4148

R11
0.47

75k

Vin

88 to

264 Vac

2A fuse

75k

1N4148

C12

100 µF 25V

R15

1.8 k

C13

100 nF

D3 STTA106

R12
47 k

R13

3.3 k

DZ1

15 V

R14

1.5 k

C6 4700pF/ 4KV

4.7M

R10

4.7M

C7 4700pF/ 4KV

R18

150 k

R17

4.7 k

220

160 V

100 k

ZCD

Vcc

GND

INV

VFF

COMP

+5 V

50 mA

C11

47 µF

25V

IC4

L7805

14 V

1 A

BYW98-100

C10

470

25 V

3 M

16 K

BYT01-400

1 nF

R7 10

8.2 nF

250 V

100 k

IC2 TL431

IC3 PC817

2.2 nF

R16

220 k

R20 22 k

1N4148

C22

100 pF

C23

100nF

C24

100nF

C25
1nF

C26
1nF

NTC1

16R

15mH

C27

220nF

Naux

L6565

10 nF

250V

STP4NA80FP

STTA106

1N4148

0.39

1/2 W

PC817

2200pF 4KV

2 x 470

35V

100 nF

28V / 0.7A

GND

470

16V

BYW100-50

BYW98-100

BYW100-200

12V / 1.5A

5V / 0.5A

2 x

1000µF

16V

PC817A

TL431

3.3 nF

47 k

75 k

56 k

2 W

3.9 k

5.1 k

270 k

2.7 k

220

16 k

3 M

10 nF

2KBP04M

Vin

88 to

264 Vac

2A fuse

100nF

1nF

16R

15mH

75 k

1N4148

TRANSFORMER SPECS:

CORE: ETD29x16x10, 3C85 material or equivalent

1 mm air gap for a primary inductance of 700 µH

N1: 75 T, AWG25

(

0.51 mm)

N2: 8 T, AWG25
N3: 7 T, AWG20 (

0.89 mm)

N4: 3 T, AWG25
N5: 7 T, AWG32 (

0.24 mm)

13/17

L6565

APPLICATION IDEAS

Here follows a series of ideas/suggestions aimed at either improving performance or solving common applica-
tion issues of L6565-based power supplies.

Figure 21. Enhanced turn-off for big MOSFET's drive

Figure 22. Latched shutdown on: a) feedback disconnection; b) overload or short circuit

Figure 23. Secondary Feedback loop configurations

GND

DRIVER

Vcc

L6565

BC327

Vcc

L6565

COMP

Vcc

L6565

COMP

BC337

BC327

1N4148

BC337

BC327

1N4148

Vout

TL431

L6565

COMP

INV

Vcc

Vout

TL431

L6565

COMP

INV

COMP

Vout

TL431

L6565

INV

Vcc

Roff

L6565

14/17

Figure 24. Primary Feedback loop configurations

Vcc

GND

L6565

E/A

INV

2.5V

COMP

to VFF

block

Vcc

GND

L6565

E/A

INV

2.5V

COMP

to VFF

block

Figure 25. Protection against secondary

feedback disconnection by primary
regulation take-over

Figure 26. Leading edge blanking circuit for

enhanced primary regulation

Figure 27. Remote ON/OFF control

Figure 28. Low-consumption start-up circuit

Vcc

L6565

INV

15 V

2.2 k

COMP

Vcc

GND

L6565

1N4148

BC327

2.7 k

470 pF

L6565

ZCD

OFF

BC337

L6565

SUPPLY

Vac

1N4148

+Vin

Vcc

GND

START

1N4148

RELATED DOCUMENTATION
[1] "L6565, QUASI-RESONANT CONTROLLER" (AN1326)
[2] "25W QUASI-RESONANT FLYBACK CONVERTER FOR SET-TOP BOX APPLICATIONS USING THE

L6565" (AN1376)

[3] "EVAL6565N, 30W AC-DC ADAPTER WITH THE L6565 QUASI-RESONANT PWM CONTROLLER"

(AN1439).

L6565

16/17

DIM.

inch

MIN.

TYP.

MAX.

MIN.

TYP.

MAX.

1.75

0.069

0.1

0.25

0.004

0.010

1.65

0.065

0.65

0.85

0.026

0.033

0.35

0.48

0.014

0.019

0.19

0.25

0.007

0.010

0.25

0.5

0.010

0.020

(typ.)

D (1)

4.8

5.0

0.189

0.197

5.8

6.2

0.228

0.244

1.27

0.050

3.81

0.150

F (1)

3.8

4.0

0.15

0.157

0.4

1.27

0.016

0.050

0.6

0.024

(max.)

(1) D and F do not include mold flash or protrusions. Mold flash or
potrusions shall not exceed 0.15mm (.006inch).

SO8

OUTLINE AND

MECHANICAL DATA

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by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.

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17/17

L6565

Part Number L6565D