SMSC DS - LPC47S45x
Rev. 07/09/2001
PRELIMINARY
LPC47S45x
Advanced I/O with X-Bus Interface
FEATURES
3.3 Volt Operation (5V tolerant)
Floppy Disk Controller (Supports 2 FDCs)
Multi-Mode Parallel Port
Two UARTs
8042 Keyboard Controller
SMBus Controller
- SMBus access to LCD Interface
- SMBus Serial Port 2 Interface Disable
- SMBus access to Power On Elapsed Time
Counters
- Programmable Slave Address
X-Bus Interface
- Supports up to four external I/O components
- Offers two modes of operation
- Support for Driving LCD Panel Interface
Controller
- Supports Port 80h "Snooping"
Programmable Wakeup Event Interface (IO_PME#
Pin)
SMI Support (IO_SMI# Pin)
GPIOs (55)
Fan Controller
- One Fan Speed Control Output
- One Fan Tachometer Input
ISA IRQ to Serial IRQ Conversion
XNOR Chain for Board Test Mode
PC2001 and ACPI 2.0 Compliant
128-pin QFP Package
ISA Plug-and-Play Compatible Register Set
Intelligent Auto Power Management
Power On Elapsed Time Counters
- Counter for Main Power
- Counter for Standby Power
Real Time Clock
- MC146818 and DS1287 Compatible
- 256 Bytes of Battery Backed CMOS in Two 128-
Byte Banks
- 128 Bytes of CMOS RAM Lockable in 4x32 Byte
Blocks
- 12 and 24 Hour Time Format
- 24-hour daily alarm
- 30-day alarm
- Binary and BCD Format
- <1
µ
A Standby Current (typ)
2.88MB Super I/O Floppy Disk Controller
- Licensed CMOS 765B Floppy Disk Controller
- Software and Register Compatible with SMSC's
Proprietary 82077AA Compatible Core
- Configurable Open Drain/Push-Pull Output
Drivers
- Supports Vertical Recording Format
- 16-Byte Data FIFO
- 100% IBM Compatibility
- Detects All Overrun and Underrun Conditions
- Sophisticated Power Control Circuitry (PCC)
Including Multiple Powerdown Modes for
Reduced Power Consumption
- DMA Enable Logic
- Data Rate and Drive Control Registers
- 480 Address, up to 15 IRQ and Four DMA
Options
Enhanced Digital Data Separator
- 2 Mbps, 1 Mbps, 500 Kbps, 300 Kbps, 250 Kbps
Data Rates
- Programmable Precompensation Modes
Keyboard Controller
- 8042 Software Compatible
- 8-Bit Microcomputer
- 2k Bytes of Program ROM
- 256 Bytes of Data RAM
- Four Open Drain Outputs Dedicated for
Keyboard/Mouse Interface
- Asynchronous Access to Two Data Registers and
One Status Register
- Supports Interrupt and Polling Access
- 8-Bit Counter Timer
- Port 92 Support
- Fast Gate A20 and KRESET Outputs
Serial Ports
- Two Full Function Serial Ports
- High Speed NS16C550A Compatible UARTs with
Send/Receive 16-Byte FIFOs
- Supports 230k and 460k Baud
- Programmable Baud Rate Generator
- Modem Control Circuitry
- 480 Address and 15 IRQ Options
- IrDA 1.0, HP-SIR, ASK IR Support
Multi-Mode Parallel Port with ChiProtect
SMSC DS LPC47S45x
Page 2 of 259
Rev. 07/09/2001
PRELIMINARY
- Standard Mode IBM PC/XT, PC/AT, and PS/2
Compatible Bi-directional Parallel Port
- Enhanced Parallel Port (EPP) Compatible - EPP
1.7 and EPP 1.9 (IEEE 1284 Compliant)
- IEEE 1284 Compliant Enhanced Capabilities Port
(ECP)
- ChiProtect Circuitry for Protection Against
Damage Due to Printer Power-On
- 960 Address, up to 15 IRQ and Four DMA
Options
Pin Reduced ISA Host Interface (LPC Bus)
- Multiplexed Command, Address and Data Bus
- 8-Bit I/O Transfers
- 8-Bit DMA Transfers
- 16-Bit Address Qualification
- Serial IRQ Interface Compatible with
Serialized
IRQ Support for PCI Systems
- Power Management Event (PME) Interface Pin
Power Management
ACPI Registers
© STANDARD MICROSYSTEMS CORPORATION (SMSC) 2001
80 Arkay Drive
Hauppauge, NY 11788
(631) 435-6000
FAX (631) 273-3123
Standard Microsystems is a registered trademark of Standard Microsystems Corporation, and SMSC, ChiProtect, and Multi-Mode are trademarks of
Standard Microsystems Corporation. Product names and company names are the trademarks of their respective holders. Circuit diagrams utilizing
SMSC products are included as a means of illustrating typical applications; consequently complete information sufficient for construction purposes is
not necessarily given. Although the information has been checked and is believed to be accurate, no responsibility is assumed for inaccuracies.
SMSC reserves the right to make changes to specifications and product descriptions at any time without notice. Contact your local SMSC sales office
to obtain the latest specifications before placing your product order. The provision of this information does not convey to the purchaser of the
semiconductor devices described any licenses under the patent rights of SMSC or others. All sales are expressly conditional on your agreement to the
terms and conditions of the most recently dated version of SMSC's standard Terms of Sale Agreement dated before the date of your order (the "Terms
of Sale Agreement"). The product may contain design defects or errors known as anomalies which may cause the product's functions to deviate from
published specifications. Anomaly sheets are available upon request. SMSC products are not designed, intended, authorized or warranted for use in
any life support or other application where product failure could cause or contribute to personal injury or severe property damage. Any and all such
uses without prior written approval of an Officer of SMSC and further testing and/or modification will be fully at the risk of the customer. Copies of this
document or other SMSC literature, as well as the Terms of Sale Agreement, may be obtained by visiting SMSC's website at http://www.smsc.com.
SMSC DISCLAIMS AND EXCLUDES ANY AND ALL WARRANTIES, INCLUDING WITHOUT LIMITATION ANY AND ALL IMPLIED WARRANTIES
OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, TITLE, AND AGAINST INFRINGEMENT, AND ANY AND ALL
WARRANTIES ARISING FROM ANY COURSE OF DEALING OR USAGE OF TRADE.
IN NO EVENT SHALL SMSC BE LIABLE FOR ANY DIRECT, INCIDENTAL, INDIRECT, SPECIAL, PUNITIVE, OR CONSEQUENTIAL DAMAGES,
OR FOR LOST DATA, PROFITS, SAVINGS OR REVENUES OF ANY KIND; REGARDLESS OF THE FORM OF ACTION, WHETHER BASED ON
CONTRACT, TORT, NEGLIGENCE OF SMSC OR OTHERS, STRICT LIABILITY, BREACH OF WARRANTY, OR OTHERWISE; WHETHER OR
NOT ANY REMEDY IS HELD TO HAVE FAILED OF ITS ESSENTIAL PURPOSE; AND WHETHER OR NOT SMSC HAS BEEN ADVISED OF THE
POSSIBILITY OF SUCH DAMAGES.
SMSC DS LPC47S45x
Page 3 of 259
Rev. 07/09/2001
PRELIMINARY
GENERAL DESCRIPTION
The LPC47S45x is a 3.3V PC2001 compliant Super I/O controller designed for server applications. The LPC47S45x
implements the LPC interface, a pin reduced ISA interface which provides the same or better performance as the
ISA/X-bus with a substantial savings in pins used. The part provides 55 GPIO pins, ACPI support, an X-Bus
interface, two SMBus controllers, a fan speed control output, a fan tachometer input and four ISA IRQs that can be
routed to any of the serial IRQs. The LPC47S45x also provides Power on Elapsed Time counters for Main Power and
Standby Power, power supply on/off control, and a Real Time Clock.
The X-Bus interface allows the LPC47S45x to interface to as many as four external components that have an eight
bit data bus and occupy up to 4 contiguous I/O address ports. It is accessible by either the SMBus or the LPC
interface. It is capable of interfacing to an LCD Panel Interface Controller without any external logic and it can be
used for Port 80h "snooping".
The LPC47S45x offers two SMBus controllers that share the same pin interface. The SMBus slave only device
provides external access to an LCD controller that can be attached to the X-Bus. It is capable of disabling the floppy
port, the serial ports, and the parallel port. The SMBus slave only device can also tristate the Serial Port 2 interface
so that it may be muxed with an external UART controller. The LPC47S45x is equipped with two counters that may
be monitored either by the SMBus slave only device or by the LPC interface, which monitor the length of time VCC
and VTR are active.
The LPC47S45x incorporates a keyboard interface, SMSC's true CMOS 765B floppy disk controller, advanced digital
data separator, two 16C550 compatible UARTs, one Multi-Mode parallel port which includes ChiProtect circuitry plus
EPP and ECP, and Intelligent Power Management. The true CMOS 765B core provides 100% compatibility with IBM
PC/XT and PC/AT architectures in addition to providing data overflow and underflow protection. The SMSC
advanced digital data separator incorporates SMSC's patented data separator technology, allowing for ease of
testing and use. The on-chip UARTs are compatible with the NS16C550. The parallel port is compatible with IBM
PC/AT architecture, as well as IEEE 1284 EPP and ECP. The LPC47S45x incorporates sophisticated power control
circuitry (PCC). The PCC supports multiple low power down modes.
The LPC47S45x supports the ISA Plug-and-Play Standard (Version 1.0a) and provides the recommended
functionality to support Windows 2000, Windows Me, and PC2001. The I/O Address, DMA Channel and Hardware
IRQ of each logical device in the LPC47S45x may be reprogrammed through the internal configuration registers.
There are 480 I/O address location options, a Serialized IRQ interface, and three DMA channels.
ORDERING INFORMATION
Order Numbers:
LPC47S452-NC
for 128 Pin QFP Package with AMI Keyboard BIOS
LPC47S457-NC
for 128 Pin QFP Package with Phoenix 42i Keyboard BIOS
SMSC DS LPC47S45x
Page 4 of 259
Rev. 07/09/2001
PRELIMINARY
TABLE OF CONTENTS
1
PIN CONFIGURATION.........................................................................................................................10
2
PINOUT.................................................................................................................................................11
3
PIN DESCRIPTION ..............................................................................................................................12
3.1
B
UFFER
T
YPE
D
ESCRIPTIONS
............................................................................................................................ 17
3.2
P
INS
T
HAT
R
EQUIRE
E
XTERNAL
P
ULLUP
R
ESISTORS
........................................................................................... 18
4
DESCRIPTION OF POWER SOURCES AND CLOCK INPUT/OUTPUTS.........................................19
4.1
3.3 V
OLT
O
PERATION
/ 5 V
OLT
T
OLERANCE
....................................................................................................... 19
4.2
P
OWER
F
UNCTIONALITY
.................................................................................................................................... 19
4.2.1
VCC Power ............................................................................................................................................ 19
4.2.2
VTR Support .......................................................................................................................................... 19
4.2.3
Vbat Input............................................................................................................................................... 19
4.3
I
NTERNAL
PWRGOOD .................................................................................................................................... 20
4.4
32.768 KHZ T
RICKLE
C
LOCK
I
NPUT
.................................................................................................................. 20
4.5
I
NDICATION OF
32KHZ C
LOCK
.......................................................................................................................... 20
4.6
XOSEL .......................................................................................................................................................... 21
4.7
T
RICKLE
P
OWER
F
UNCTIONALITY
....................................................................................................................... 21
4.8
40MH
Z
C
LOCK
O
UTPUT
................................................................................................................................... 23
4.9
M
AXIMUM
C
URRENT
V
ALUES
............................................................................................................................. 23
4.10
P
OWER
M
ANAGEMENT
E
VENTS
(PME/SCI).................................................................................................... 23
5
FUNCTIONAL DESCRIPTION .............................................................................................................24
5.1
S
UPER
I/O R
EGISTERS
..................................................................................................................................... 24
5.2
H
OST
P
ROCESSOR
I
NTERFACE
(LPC)................................................................................................................ 24
5.3
LPC I
NTERFACE
.............................................................................................................................................. 24
5.3.1
LPC Interface Signal Definition .............................................................................................................. 25
5.3.2
Power Management............................................................................................................................... 26
5.3.3
LPC Transfers........................................................................................................................................ 27
5.4
F
LOPPY
D
ISK
C
ONTROLLER
.............................................................................................................................. 28
5.4.1
FDC Internal Registers........................................................................................................................... 28
5.4.2
Status Register Encoding....................................................................................................................... 38
5.4.3
DMA Transfers....................................................................................................................................... 41
5.4.4
Controller Phases .................................................................................................................................. 41
5.4.5
Command Set/Descriptions ................................................................................................................... 42
5.4.6
Instruction Set ........................................................................................................................................ 45
5.4.7
Data Transfer Commands...................................................................................................................... 51
5.4.8
Control Commands ................................................................................................................................ 57
5.4.9
Direct Support for Two Floppy Drives .................................................................................................... 62
5.5
S
ERIAL
P
ORT
(UART)...................................................................................................................................... 63
5.5.1
Register Description............................................................................................................................... 63
5.5.2
Programmable Baud Rate Generator (AND Divisor Latches DLH, DLL) ............................................... 70
5.5.3
Effect Of The Reset on Register File ..................................................................................................... 70
5.5.4
FIFO Interrupt Mode Operation.............................................................................................................. 70
5.5.5
FIFO Polled Mode Opertion ................................................................................................................... 71
5.5.6
Notes On Serial Port Operation ............................................................................................................. 75
5.6
I
NFRARED
I
NTERFACE
....................................................................................................................................... 76
5.6.1
IR Transmit Pin ...................................................................................................................................... 76
5.7
P
ARALLEL
P
ORT
.............................................................................................................................................. 77
5.7.1
IBM XT/AT Compatible, Bi-Directional And EPP Modes ....................................................................... 78
5.7.2
EPP 1.9 Operation ................................................................................................................................. 80
5.7.3
EPP 1.7 Operation ................................................................................................................................. 81
5.7.4
Extended Capabilities Parallel Port........................................................................................................ 83
5.7.5
Vocabulary ............................................................................................................................................. 83
5.7.6
ECP Implementation Standard............................................................................................................... 83
5.7.7
Parallel Port Floppy Disk Controller ....................................................................................................... 92
5.8
P
OWER
M
ANAGEMENT
...................................................................................................................................... 94
SMSC DS LPC47S45x
Page 5 of 259
Rev. 07/09/2001
PRELIMINARY
5.8.1
FDC Power Management....................................................................................................................... 94
5.8.2
UART Power Management .................................................................................................................... 96
5.8.3
Parallel Port ........................................................................................................................................... 96
5.9
R
EAL
T
IME
C
LOCK
........................................................................................................................................... 97
5.9.1
Configuration Registers.......................................................................................................................... 97
5.9.2
Host I/O Interface................................................................................................................................... 98
5.9.3
Internal Registers................................................................................................................................... 98
5.9.4
Time Calendar and Alarm ...................................................................................................................... 99
5.9.5
Update Cycle ....................................................................................................................................... 100
5.9.6
Control and Status Registers ............................................................................................................... 100
5.9.7
Interrupts.............................................................................................................................................. 103
5.9.8
32kHz Clock Input................................................................................................................................ 104
5.9.9
Power Management............................................................................................................................. 104
5.10
S
ERIAL
IRQ ............................................................................................................................................... 105
5.10.1
Timing Diagrams For SER_IRQ Cycle ............................................................................................. 105
5.10.2
Routable IRQ To Serial IRQ Conversion Capability ......................................................................... 107
5.11
8042 K
EYBOARD
C
ONTROLLER
D
ESCRIPTION
............................................................................................... 108
5.11.1
Keyboard Interface ........................................................................................................................... 108
5.11.2
External Keyboard and Mouse Interface .......................................................................................... 109
5.11.3
Keyboard Power Management ......................................................................................................... 110
5.11.4
Interrupts .......................................................................................................................................... 110
5.11.5
Memory Configurations .................................................................................................................... 110
5.11.6
Register Definitions .......................................................................................................................... 110
5.11.7
External Clock Signal ....................................................................................................................... 111
5.11.8
Default Reset Conditions.................................................................................................................. 111
5.11.9
Latches On Keyboard and Mouse IRQs ........................................................................................... 113
5.11.10
Keyboard and Mouse PME Generation ............................................................................................ 114
5.12
G
ENERAL
P
URPOSE
I/O .............................................................................................................................. 115
5.12.1
GPIO Pins ........................................................................................................................................ 115
5.12.2
Description ....................................................................................................................................... 116
5.12.3
GPIO Control.................................................................................................................................... 118
5.12.4
GPIO Operation................................................................................................................................ 119
5.12.5
GPIO PME and SMI Functionality .................................................................................................... 120
5.12.6
Either Edge Triggered Interrupts ...................................................................................................... 121
5.12.7
LED Functionality ............................................................................................................................. 122
5.13
W
ATCH
D
OG
T
IMER
.................................................................................................................................... 122
5.14
P
OWER
O
N
E
LAPSED
T
IMER
(POET) ........................................................................................................... 123
5.14.1
VCC Power on Elapsed Time Counter ............................................................................................. 123
5.14.2
VTR Power on Elapsed Time Counter.............................................................................................. 123
5.15
F
AN
S
PEED
C
ONTROL
A
ND
M
ONITORING
...................................................................................................... 124
5.15.1
Fan Speed Control ........................................................................................................................... 124
5.15.2
Fan Speed Monitoring ...................................................................................................................... 125
5.16
D
EVICE
D
ISABLE
R
EGISTER
......................................................................................................................... 128
5.16.1
Device Disable Register (LPC only) ................................................................................................. 128
5.16.2
SMBus2 Device Disable Register (SMBus2 only) ............................................................................ 128
5.17
SMB
US
C
ONTROLLER
................................................................................................................................. 129
5.17.1
Configuration Registers .................................................................................................................... 129
5.17.2
Runtime Registers ............................................................................................................................ 129
5.18
SMB
US
2 S
LAVE
D
EVICE
............................................................................................................................. 135
5.18.1
SMBus Protocols supported by SMBus2.......................................................................................... 136
5.18.2
Command Codes ............................................................................................................................. 136
5.18.3
X-Bus SMBus2/LPC Arbitration........................................................................................................ 137
5.18.4
SMBus2 Register Summary ............................................................................................................. 139
5.18.5
SMBus2 Register Description........................................................................................................... 139
5.18.6
Invalid Command Protocol Response Behavior ............................................................................... 141
5.18.7
Slave Device Time-Out..................................................................................................................... 142
5.18.8
Stretching the SCLK Signal .............................................................................................................. 142
5.18.9
SMBus Timing .................................................................................................................................. 142
5.18.10
Bus Reset Sequence........................................................................................................................ 142
5.19
X-B
US
I
NTERFACE
...................................................................................................................................... 143
5.19.1
I/O Cycles......................................................................................................................................... 143
5.19.2
Supported LCD Controllers .............................................................................................................. 146
6
ACPI/PME/SMI FEATURES...............................................................................................................147
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