Document Outline
- FEATURES
- IN NO EVENT SHALL SMSC BE LIABLE FOR ANY DIRECT, INCIDENTAL, INDIRECT, SPECIAL, PUNITIVE, OR CONSEQUENTIAL DAMAGES, OR FOR LOST DATA, PROFITS, SAVINGS OR REVENUES OF ANY KIND; REGARDLESS OF THE FORM OF ACTION, WHETHER BASED ON CONTRACT, TORT, NEGLIGENCE
- GENERAL DESCRIPTION
- PIN LAYOUT
- PIN CONFIGURATION
- DESCRIPTION OF PIN FUNCTIONS
- BLOCK DIAGRAM
- POWER FUNCTIONALITY
- FUNCTIONAL DESCRIPTION
- SUPER I/O REGISTERS
- HOST PROCESSOR INTERFACE (LPC)
- LPC INTERFACE
- FLOPPY DISK CONTROLLER
- SERIAL PORT (UART)
-
-
-
-
-
- Address Offset = 0H, DLAB = 0, READ ONLY
- Address Offset = 0H, DLAB = 0, WRITE ONLY
- Address Offset = 1H, DLAB = 0, READ/WRITE
- Address Offset = 2H, DLAB = X, WRITE
- Address Offset = 2H, DLAB = X, READ
- Address Offset = 5H, DLAB = X, READ/WRITE
- Address Offset = 6H, DLAB = X, READ/WRITE
- Address Offset =7H, DLAB =X, READ/WRITE
- INFRARED INTERFACE
- MPU-401 MIDI UART
- PARALLEL PORT
- POWER MANAGEMENT
- SERIAL IRQ
- 8042 KEYBOARD CONTROLLER DESCRIPTION
- GENERAL PURPOSE I/O
- SYSTEM MANAGEMENT INTERRUPT (SMI)
- PME SUPPORT
- FAN SPEED CONTROL AND MONITORING
- SECURITY FEATURE
- GAME PORT LOGIC
- HARDWARE MONITORING INTERFACE
- RUNTIME REGISTERS
- CONFIGURATION
- REGISTERS FOR HARDWARE MONITORING BLOCK
- OPERATIONAL DESCRIPTION
- TIMING DIAGRAMS
- PACKAGE OUTLINE
- APPENDIX A … THERMAL DIODE PARAMETERS
- APPENDIX B … ADC VOLTAGE CONVERSION
- APPENDIX C - TEST MODE
- REFERENCE DOCUMENTS
SMSC DS LPC47M15x
Rev. 08/02/2001
LPC Super I/O with Hardware Monitoring Block
FEATURES
3.3 Volt Operation (SIO Block is 5 Volt Tolerant)
LPC
Interface
ACPI 1.0 Compliant
Fan
Control
-
Fan Speed Control Outputs (2)
-
Fan Tachometer Inputs (2)
Programmable Wake-up Event Interface
PC98, PC99 Compliant
Dual Game Port Interface
MPU-401 MIDI Support
General Purpose Input/Output Pins (37)
ISA Plug-and-Play Compatible Register Set
Intelligent Auto Power Management
System
Management
Interrupt
2.88MB Super I/O Floppy Disk Controller
-
Licensed CMOS 765B Floppy Disk
Controller
-
Software and Register Compatible with
SMSC's Proprietary 82077AA
Compatible Core
-
Supports Two Floppy Drives
-
Configurable Open Drain/Push-Pull Output
Drivers
-
Supports Vertical Recording Format
-
16-Byte Data FIFO
-
100% IBM Compatibility
-
Detects All Overrun and Underrun
Conditions
-
Sophisticated Power Control Circuitry
(PCC) Including Multiple Powerdown
Modes for Reduced Power Consumption
-
DMA Enable Logic
-
Data Rate and Drive Control Registers
-
480 Address, Up to 15 IRQ and Three
DMA Options
Enhanced Digital Data Separator
-
2 Mbps, 1 Mbps, 500 Kbps, 300 Kbps, 250
Kbps Data Rates
-
Programmable Precompensation Modes
Keyboard
Controller
-
8042 Software Compatible
-
8 Bit Microcomputer
-
2k Bytes of Program ROM
-
256 Bytes of Data RAM
-
Four Open Drain Outputs Dedicated for
Keyboard/Mouse Interface
-
Asynchronous Access to Two Data
Registers and One Status Register
-
Supports Interrupt and Polling Access
-
8 Bit Counter Timer
-
Port 92 Support
-
Fast Gate A20 and KRESET Outputs
Serial
Ports
-
Two Full Function Serial Ports
-
High Speed NS16C550A Compatible UARTs
with Send/Receive 16-Byte FIFOs
-
Supports 230k and 460k Baud
Programmable Baud Rate Generator
Modem Control Circuitry
-
480 Address and 15 IRQ Options
Infrared
Port
-
Multiprotocol Infrared Interface
-
IrDA 1.0 Compliant
-
SHARP ASK IR
-
480 Addresses, Up to 15 IRQ
Multi-Mode Parallel Port with ChiProtect
-
Standard Mode IBM PC/XT PC/AT, and
PS/2 Compatible Bi-directional Parallel Port
-
Enhanced Parallel Port (EPP) Compatible -
EPP 1.7 and EPP 1.9 (IEEE 1284
Compliant)
-
IEEE 1284 Compliant Enhanced Capabilities
Port (ECP)
-
ChiProtect Circuitry for Protection
-
960 Address, Up to 15 IRQ and Three DMA
Options
LPC
Interface
- Multiplexed Command, Address and Data
Bus
-
Serial IRQ Interface Compatible with
Serialized IRQ Support for PCI Systems
- PME
Interface
Hardware
Monitor
-
Monitor Power supplies (+2.5V, +3.3V, +5V,
+12V, +1.8V, +1.5V, Vccp (processor
voltage), and HVCC or HVSB)
- Remote Thermal Diode Sensing for Two
External Temperature Measurements
-
Internal Ambient Temperature Measurement
-
Limit Comparison of all Monitored Values
-
System Management Bus (SMBus) Interface
-
nTHERM Pin for out-of-limit Temperature or
Voltage Indication
- nRESET Pin for generating 20msec Low
Reset Pulse
- Configurable offset for internal or external
temperature channels.
128 Pin QFP Package, 3.9MM Footprint
LPC47M15x
PRELIMINARY
SMSC DS LPC47M15x
Page 2
Rev. 08/02/2001
© STANDARD MICROSYSTEMS CORPORATION (SMSC) 2001
80 Arkay Drive
Hauppauge, NY 11788
(631) 435-6000
FAX (631) 273-3123
Standard Microsystems is a registered trademark of Standard Microsystems Corporation, and SMSC, ChiProtect and Multi-Mode are trademarks of
Standard Microsystems Corporation. Product names and company names are the trademarks of their respective holders. Circuit diagrams utilizing
SMSC products are included as a means of illustrating typical applications; consequently complete information sufficient for construction purposes is
not necessarily given. Although the information has been checked and is believed to be accurate, no responsibility is assumed for inaccuracies.
SMSC reserves the right to make changes to specifications and product descriptions at any time without notice. Contact your local SMSC sales office
to obtain the latest specifications before placing your product order. The provision of this information does not convey to the purchaser of the
semiconductor devices described any licenses under the patent rights of SMSC or others. All sales are expressly conditional on your agreement to the
terms and conditions of the most recently dated version of SMSC's standard Terms of Sale Agreement dated before the date of your order (the "Terms
of Sale Agreement"). The product may contain design defects or errors known as anomalies which may cause the product's functions to deviate from
published specifications. Anomaly sheets are available upon request. SMSC products are not designed, intended, authorized or warranted for use in
any life support or other application where product failure could cause or contribute to personal injury or severe property damage. Any and all such
uses without prior written approval of an Officer of SMSC and further testing and/or modification will be fully at the risk of the customer. Copies of this
document or other SMSC literature, as well as the Terms of Sale Agreement, may be obtained by visiting SMSC's website at http://www.smsc.com.
SMSC DISCLAIMS AND EXCLUDES ANY AND ALL WARRANTIES, INCLUDING WITHOUT LIMITATION ANY AND ALL IMPLIED WARRANTIES
OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, TITLE, AND AGAINST INFRINGEMENT, AND ANY AND ALL
WARRANTIES ARISING FROM ANY COURSE OF DEALING OR USAGE OF TRADE.
IN NO EVENT SHALL SMSC BE LIABLE FOR ANY DIRECT, INCIDENTAL, INDIRECT, SPECIAL, PUNITIVE, OR CONSEQUENTIAL DAMAGES,
OR FOR LOST DATA, PROFITS, SAVINGS OR REVENUES OF ANY KIND; REGARDLESS OF THE FORM OF ACTION, WHETHER BASED ON
CONTRACT, TORT, NEGLIGENCE OF SMSC OR OTHERS, STRICT LIABILITY, BREACH OF WARRANTY, OR OTHERWISE; WHETHER OR
NOT ANY REMEDY IS HELD TO HAVE FAILED OF ITS ESSENTIAL PURPOSE; AND WHETHER OR NOT SMSC HAS BEEN ADVISED OF THE
POSSIBILITY OF SUCH DAMAGES.
SMSC DS LPC47M15x
Page 3
Rev. 08/02/2001
GENERAL DESCRIPTION
The LPC47M15x* is a PC99/2001 compliant Advanced I/O controller with an LPC interface and Hardware Monitoring
capabilities. The design is compatible with a family of SMSC Advanced I/O Controllers, the LPC47M13x and
LPC47M14x. Each device in the family is pin compatible within the I/O section and offers enhanced functionality. The
LPC47M13x is the base part offering complete I/O functionality, LPC47M14x includes a 4 port USB Hub as well as
I/O, and the LPC47M15x contains hardware monitoring capability.
The LPC47M15x's hardware monitoring capability includes voltage and temperature monitoring with the ability to alert
the system of out-of-limit conditions. There are 7 analog inputs for monitoring external voltages of +1.5V, +1.8V,
+2.5V, +3.3V, +5V, +12V and Vccp (core processor voltage), as well as internal monitoring of the devices own HVCC
or HVSB. The LPC47M15x includes support for monitoring two external temperatures via thermal diode inputs and an
internal sensor for measuring ambient temperature. The nTHERM pin is implemented to indicate out-of-limit
temperature and voltage conditions. The block has an ability to output 20ms low pulse via nRESET pin. The
hardware monitoring block of the LPC47M15x is accessible via the System Management Bus (SMBus).
The LPC47M15x incorporates complete legacy Super I/O functionality including an 8042 based keyboard and mouse
controller, an IEEE 1284, EPP, and ECP compatible parallel port, two serial ports that are 16C550A UART
compatible, two IrDA 1.0 infrared ports, and a floppy disk controller with SMSC's true CMOS 765B core and enhanced
digital data separator, The true CMOS 765B core provides 100% compatibility with IBM PC/XT and PC/AT
architectures and is software and register compatible with SMSC's proprietary 82077AA core. System related
functionality, which offers flexibility to the system designer, includes an MPU-401 MIDI interface, (37) General
Purpose I/O control functions, control of two LED's, a game port interface supporting two joysticks, and fan control
using fan tachometer inputs and pulse width modulator, (PWM), outputs.
The LPC47M15x is ACPI 1.0 compatible and therefore supports multiple low power-down modes. It incorporates
sophisticated power control circuitry (PCC) which includes support for keyboard and mouse wake-up events.
The LPC47M15x supports the ISA Plug-and-Play Standard register set (Version 1.0a). The I/O Address, DMA
Channel and hardware IRQ of each logical device in the LPC47M15x may be reprogrammed through the internal
configuration registers. There are upto 480 (960 - Parallel Port) I/O address location options, a Serialized IRQ
interface, and Three DMA channels.
The LPC47M15x does not require any external filter components and is therefore easy to use and offers lower system
costs and reduced board area.
* The "x" in the part number is a designator that changes depending upon the particular BIOS used inside the specific
chip.
ORDERING INFORMATION
PART#
PACKAGE
KEYBOARD BIOS
LPC47M152-NC
128 Pin QFP
AMI
LPC47M157-NC
128 Pin QFP
Phoenix 42i
SMSC DS LPC47M15x
Page 4
Rev. 08/02/2001
TABLE OF CONTENTS
1. PIN LAYOUT ..........................................................................................................................................9
2. PIN CONFIGURATION.........................................................................................................................10
3. DESCRIPTION OF PIN FUNCTIONS ..................................................................................................11
3.1
B
UFFER
NAME D
ESCRIPTIONS
.........................................................................................................19
3.2
P
INS
T
HAT
R
EQUIRE
E
XTERNAL
P
ULLUP
R
ESISTORS
..........................................................................20
3.2.1
Super I/O Pins........................................................................................................................................ 20
3.2.2
Hardware Monitoring Block Pins ............................................................................................................ 20
4. BLOCK DIAGRAM ...............................................................................................................................21
5. POWER FUNCTIONALITY ..................................................................................................................22
5.1
VCC/HVCC P
OWER
........................................................................................................................22
5.1.1
3 VOLT OPERATION / 5 VOLT TOLERANCE ...................................................................................... 22
5.2
VREF P
IN
........................................................................................................................................22
5.3
VTR S
UPPORT
.................................................................................................................................22
5.3.1
Trickle Power Functionality .................................................................................................................... 22
5.4
32.768
K
H
Z
T
RICKLE
C
LOCK
I
NPUT
...................................................................................................24
5.5
I
NTERNAL
PWRGOOD.....................................................................................................................24
5.6
M
AXIMUM
C
URRENT
V
ALUES
.............................................................................................................24
5.6.1
Super I/O Functions ............................................................................................................................... 24
5.6.2
Hardware Monitoring Block Functions.................................................................................................... 25
5.7
P
OWER
M
ANAGEMENT
E
VENTS
(PME/SCI) .......................................................................................25
6. FUNCTIONAL DESCRIPTION .............................................................................................................26
6.1
S
UPER
I/O R
EGISTERS
.....................................................................................................................26
6.2
H
OST
P
ROCESSOR
I
NTERFACE
(LPC)................................................................................................26
6.3
LPC I
NTERFACE
...............................................................................................................................27
6.3.1
LPC Interface Signal Definition .............................................................................................................. 27
6.3.2
LPC Cycles ............................................................................................................................................ 27
6.3.3
Field Definitions ..................................................................................................................................... 27
6.3.4
nLFRAME Usage ................................................................................................................................... 27
6.3.5
I/O Read and Write Cycles..................................................................................................................... 27
6.3.6
DMA Read and Write Cycles ................................................................................................................. 28
6.3.7
DMA Protocol......................................................................................................................................... 28
6.3.8
Power Management............................................................................................................................... 28
6.3.9
SYNC Protocol....................................................................................................................................... 28
6.3.10
LPC TRANSFERS.............................................................................................................................. 29
6.4
FLOPPY DISK CONTROLLER ......................................................................................................29
6.4.1
FDC Internal Registers........................................................................................................................... 29
6.4.2
STATUS REGISTER ENCODING ......................................................................................................... 40
6.4.3
Instruction Set ........................................................................................................................................ 47
6.4.4
DATA TRANSFER COMMANDS ........................................................................................................... 53
6.4.5
DIRECT SUPPORT FOR TWO FLOPPY DRIVES ................................................................................ 64
6.4.6
FDC Swap Bit ........................................................................................................................................ 64
6.5
SERIAL PORT (UART) ..................................................................................................................64
6.6
INFRARED INTERFACE................................................................................................................76
6.7
MPU-401 MIDI UART .....................................................................................................................78
6.7.1
Overview ................................................................................................................................................ 78
6.7.2
Host Interface......................................................................................................................................... 78
6.7.3
MIDI Data Port ....................................................................................................................................... 79
6.7.4 ..................................................................................................................................................................... 79
6.7.5
Status Port ............................................................................................................................................. 79
6.7.6
MPU-401 Command Controller.............................................................................................................. 81
6.7.7
MIDI UART............................................................................................................................................. 81
6.7.8
MPU-401 Configuration Registers ......................................................................................................... 82
6.8
PARALLEL PORT ..........................................................................................................................82
SMSC DS LPC47M15x
Page 5
Rev. 08/02/2001
6.8.1
IBM XT/AT Compatible, Bi-Directional and EPP Modes ........................................................................ 83
6.8.2
Extended Capabilities Parallel Port........................................................................................................ 88
6.9
POWER MANAGEMENT ...............................................................................................................98
6.10
SERIAL IRQ ..............................................................................................................................101
6.11
8042 KEYBOARD CONTROLLER DESCRIPTION..................................................................104
6.11.1
Keyboard Interface ........................................................................................................................... 104
6.11.2
External Keyboard and Mouse Interface .......................................................................................... 106
6.11.3
Keyboard Power Management ......................................................................................................... 106
6.11.4
Interrupts .......................................................................................................................................... 106
6.11.5
Memory Configurations .................................................................................................................... 106
6.11.6
Register Definitions .......................................................................................................................... 106
6.11.7
External Clock Signal ....................................................................................................................... 107
6.11.8
Default Reset Conditions.................................................................................................................. 107
6.11.9
Keyboard and Mouse PME Generation ............................................................................................ 111
6.12
GENERAL PURPOSE I/O.........................................................................................................112
6.12.1
GPIO Pins ........................................................................................................................................ 112
6.12.2
Description ....................................................................................................................................... 113
6.12.3
GPIO Control.................................................................................................................................... 114
6.12.4
GPIO Operation................................................................................................................................ 115
6.12.5
GPIO PME and SMI Functionality .................................................................................................... 116
6.12.6
Either Edge Triggered Interrupts ...................................................................................................... 117
6.12.7
LED Functionality ............................................................................................................................. 117
6.13
SYSTEM MANAGEMENT INTERRUPT (SMI) .........................................................................118
6.13.1
SMI Registers................................................................................................................................... 118
6.14
PME SUPPORT ........................................................................................................................119
6.14.1
`Wake on Specific Key' Option ......................................................................................................... 120
6.15
FAN SPEED CONTROL AND MONITORING ..........................................................................121
6.15.1
Fan Speed Control ........................................................................................................................... 121
6.15.2
Fan Speed Monitoring ...................................................................................................................... 122
6.16
SECURITY FEATURE ..............................................................................................................124
6.16.1
GPIO Device Disable Register Control............................................................................................. 124
6.16.2
Device Disable Register ................................................................................................................... 125
6.17
GAME PORT LOGIC ................................................................................................................125
6.17.1
Power Control Register .................................................................................................................... 127
6.17.2
VREF Pin.......................................................................................................................................... 127
6.18
H
ARDWARE
M
ONITORING
I
NTERFACE
...........................................................................................128
6.18.1
Hardware Monitoring Interface Signal Definition .............................................................................. 128
6.18.2
SMBus Interface............................................................................................................................... 129
6.18.2.1
SMBus Slave Interface..................................................................................................................................129
6.18.3
Hardware Monitoring Block .............................................................................................................. 131
6.18.3.1
Input Monitoring ...........................................................................................................................................131
6.18.3.2
Resetting the Hardware Monitoring Block....................................................................................................132
6.18.3.3
Reset Out Pin ................................................................................................................................................132
6.18.3.4
Monitoring Modes.........................................................................................................................................132
6.18.3.5
Interrupt Status Registers ..............................................................................................................................133
6.18.3.6
Low Power Modes ........................................................................................................................................133
6.18.3.7
Analog Voltage Measurement.......................................................................................................................134
6.18.3.8
Voltage ID.....................................................................................................................................................134
6.18.3.9
Temperature Measurement............................................................................................................................134
6.18.3.10
Thermal / Voltage Interrupt Pin ..................................................................................................................135
6.18.3.11
Input Safety.................................................................................................................................................136
6.18.3.12
Layout Considerations ................................................................................................................................136
7. RUNTIME REGISTERS......................................................................................................................138
8. CONFIGURATION..............................................................................................................................164
9. REGISTERS FOR HARDWARE MONITORING BLOCK..................................................................182
9.1
R
EGISTER
S
UMMARY
......................................................................................................................182
9.2
I
NTERNAL
A
DDRESS
R
EGISTER
........................................................................................................182
9.3
V
ALUE OR
L
IMIT
R
EGISTERS
(15
H
-3D
H
)...........................................................................................183
9.3.1.1
Registers 3Eh-4Fh .........................................................................................................................................184
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