The Siemens Power Hybrid SPH 4692 contains the SMPS IC TDA 4605-3 as well as the SIEMENS
POWER MOSFET in a P-DIP-18 package.
The IC TDA 4605-3 controls the MOS-power transistor and performs all necessary control and
protection functions in free running flyback converters. Because of the fact that a wide load range
is achieved, this IC is applicable for consumer as well as industrial power supplies.
Type
Ordering Code
Package
SPH 4692
Q67000A5069
P-DIP-18-4
Siemens Power Hybrid for SMPS
Preliminary Data
Bipolar IC
SPH 4692
P-DIP-18-4
Features
q
Fold-back characteristics provides overload protection for
external components
q
Burst operation under secondary short-circuit condition
implemented
q
Protection against open or a short of the control loop
q
Switch-off if line voltage is too low (undervoltage switch-off)
q
Line voltage depending compensation of fold-back point
q
Soft-start for quiet start-up without noise generated by the
transformer
q
Chip-over temperature protection implemented (thermal
shutdown)
q
On-chip ringing suppression circuit against parasitic
oscillations of the transformer
Power MOSFET
q
V
DS
= 600 V
q
R
DS ON
= 3.0
q
Repetitive Avalanche
Semiconductor Group
1
02.95
Semiconductor Group
2
SPH 4692
The serial circuit and primary winding of the flyback transformer are connected in series to the input
voltage. During the switch-on period of the transistor, energy is stored in the transformer. During the
switch-off period the energy is fed to the load via the secondary winding. By varying the switch-on
time of the power transistor, the IC controls each portion of energy transferred to the secondary side
such that the output voltage remains nearly independent of load variations. The required control
information is taken from the input voltage during the switch-on period of the transistor and from a
regulation winding during the switch-off period. A new cycle will start if the transformer has
transferred the stored energy completely into the load.
In the different load ranges the switched-mode power supply (SMPS) behaves as follows:
No-load Operation
The power supply is operating in the burst mode at typical 20 to 40 kHz. The output voltage can be
a little bit higher or lower than the nominal value depending of the design of the transformer and the
resistor of the control voltage divider.
Nominal Operation
The switching frequency is reduced with increasing load and decreasing AC-voltage.
The output voltage is only dependent on the load.
Overload Point
Maximal output power is available at this point of the output characteristic.
Overload
The energy transferred per operation cycle is limited at the top. Therefore the output voltages
declines by secondary overloading.
Pin Configuration Control IC
Pin 1
Pin 2
Pin 3
Pin 4
Pin 15
Pin 16
Pin 17
Pin 18
Regulating voltage
Primary current simulation
Primary voltage detector
Ground
Push-pull output
Supply voltage
Soft-start
Zero detector
Pin Configuration Power MOSFET
Pin 5, 12
Pin 6-11
Pin 13
Pin 14
N.C.
MOSFET-Drain
MOSFET-Source
MOSFET-Gate
Semiconductor Group
3
SPH 4692
Pin Definitions and Functions
Pin No.
Function
1
Information Input Concerning Secondary Voltage. By comparing the
regulating voltage - obtained from the regulating winding of the transformer - with
the internal reference voltage, the output impulse width on pin 15 is adapted to
the load of the secondary side (normal, overload, short-circuit, no load).
2
Information Input Regarding the Primary Current. The primary current rise in
the primary winding is simulated at pin 2 as a voltage rise by means of external
RC-element. When a value is reached that's derived from the regulating voltage
at pin 1, the output impulse at pin 15 is terminated. The RC-element serves to set
the maximum power at the overload point set.
3
Input for Primary Voltage Monitoring. In the normal operation
V
3
is moving
between the thresholds
V
3H
and
V
3L
(
V
3H
>
V
3
>
V
3L
).
V
3
<
V
3L
: SMPS is switched
OFF (line voltage too low).
V
3
>
V
3H
: Compensation of the overload point
regulation (controlled by pin 2) starts at
V
3H
:
V
3L
= 1.7.
4
Ground
5
Not connected
6-11
MOSFET-Drain
12
Not connected
13
MOSFET-Source
14
MOSFET-Gate
15
Output: Push-pull output provides
±
1 A for rapid charge and discharge of the
gate capacitance of the power MOS-transistor.
16
Supply Voltage Input. From it a stable internal reference voltage
V
REF
and the
switching thresholds
V
16A
,
V
16E
,
V
16 max
and
V
16 min
for the supply voltage
detector is formed. If
V
16
>
V
16E
then
V
REF
is switched on and switched off when
V
16
< V
16A
. In addition the logic is only enabled for V
16 min
> V
16
.
17
Input for Soft-Start. Start-up will begin with short pulses by connecting a
capacitor from pin 7 to ground.
18
Input for the Oscillation Feedback. After starting oscillation, every zero transit
of the feedback voltage (falling edge) triggers an output impulse at pin 15. The
trigger threshold is at + 50 mV typical.
Semiconductor Group
4
SPH 4692
Block Diagram
Semiconductor Group
5
SPH 4692
Circuit Description
Application Circuit
The application circuit shows a flyback converter for video recorders with an output power rating of
25 W. The circuit is designed as a wide-range power supply for AC-line voltage of 180 to 264 V. The
AC-input voltage is rectified by the bridge rectifier GR1 and smoothed by
C
1
. The NTC limits the
rush-in current.
In the period before the switch-on threshold is reached the IC is supplied via resistor
R
1
; during the
start-up phase it uses the energy stored in
C
2
, under steady state conditions the IC receives its
supply voltage from transformer winding
n
1
via diode D1. The switching transistor T1 is a BUZ 92.
The parallel connected capacitor
C
3
and the inductance of primary winding
n
2
determine the system
resonance frequency. The
R
2
-
C
4
-D2 circuitry limits overshoot peaks, and
R
13
protects the gate of
T1 against static charges.
During the conductive phase of the power transistor T1 the current rise in the primary winding
depends on the winding inductance and the mains voltage. The network consisting of
R
4
-
C
5
is used
to create a model of the sawtooth shaped rise of the collector current. The resulting control voltage
is fed into pin 2 of the IC. The RC-time constant given by
R
4
-
C
5
must be designed that way that
driving the transistor core into saturation is avoided.
The ratio of the voltage divider
R
10
/
R
11
is fixing a voltage level threshold. Below this threshold the
switching power supply shall stop operation because of the low mains voltage. The control voltage
present at pin 3 also determines the correction current for the fold-back point. This current added
to the current flowing through
R
4
and represents an additional charge to
C
5
in order to reduce the
turn-on phase of T1. This is done to stabilize the fold-back point even under higher main voltages.
Regulation of the switched-mode power supply is via pin 1.The control voltage of winding
n
1
during
the off period of T1 is rectified by D3, smoothed by
C
6
and stepped down at an adjustable ratio by
R
5
,
R
6
and
R
7
. The
R
8
-
C
7
network suppresses parasitic overshoots (transformer oscillation). The
peak voltage at pin 2, and thus the primary peak current, is adjusted by the IC so that the voltage
applied across the control winding, and hence the output voltages, are at the desired level.
When the transformer has supplied its energy to the load, the control voltage passes through zero.
The IC detects the zero crossing via series resistors
R
9
connected to pin 18. But zero crossings are
also produced by transformer oscillation after T1 has turned off if outputs is short-circuited.
Therefore the IC ignores zero crossings occurring within a specified period of time after T1 turn-off.
The capacitor
C
8
connected to pin 17 causes the power supply to be started with shorter pulses to
keep the operating frequency outside the audible range during start-up.
On the secondary side, three output voltages are produced across winding
n
3
to
n
5
rectified by D4
to D6 and smoothed by
C
9
to
C
11
. Resistor
R
12
is used as a bleeder resistor. Fusable resistors
R
15
and
R
16
protect the rectifiers against short-circuits in the output circuits, which are designed to
supply only small loads.
Semiconductor Group
6
SPH 4692
Block Diagram
Pin 1
The regulating voltage forwarded to this pin is compared with a stable internal reference voltage
V
R
in the regulating and overload amplifier. The output of this stage is fed to the stop comparator. If
the control voltage is rather small at pin 1 an additional current is added by means of current source
which is controlled according the level at pin 17. This additional current is virtually reducing the
control voltage present at pin 1.
Pin 2
A voltage proportional to the drain current of the switching transistor is generated there by the
external RC-combination in conjunction with the primary current transducer. The output on this
transducer is controlled by the logic and referenced to the internal stable voltage
V
2B
. If the voltage
V
2
exceeds the output voltage of the regulations amplifier, the logic is reset by the stop comparator
and consequently the output of pin 15 is switched to low potential. Further inputs for the logic stage
are the output for the start impulse generator with the stable reference potential
V
ST
and the
supply voltage motor.
Pin 3
The down divide primary voltage applied there stabilized the overload point. In addition the logic is
disabled in the event of low voltage by comparison with the internal stable voltage
V
V
in the primary
voltage monitor block.
Pin 4
Ground
Pin 15
In the output stage the output signals produced by the logic are shifted to a level suitable for MOS-
power transistors.
Pin 16
From the supply voltage
V
16
are derived a stable internal references
V
REF
and the switching
threshold
V
16 A
,
V
16 E
,
V
16 max
and
V
16 min
for the supply voltage monitor. All references values
(
V
R
,
V
2 B
,
V
ST
) are derived from
V
REF
. If
V
16
>
V
VE
, the
V
REF
is switched on and switched off
when
V
16
<
V
16 A
. In addition, the logic is released only for
V
16 min
<
V
16
<
V
16 max
.
Pin17
The output of the overload amplifier is connected to pin 17. A load on this output causes a reduction
in maximal impulse duration. This function can be used to implement a soft start, when pin 17 is
connected to ground by a capacitor.
Semiconductor Group
7
SPH 4692
Pin 18
The zero detector controlling the logic block recognizes the transformer being discharged by
positive to negative zero crossing of pin 18 voltage and enables the logic for a new pulse. Parasitic
oscillations occurring at the end of a pulse cannot lead to a new pulse (double pulsing), because an
internal circuit inhibits the zero detector for a finite time
t
UL
after the end of each pulse.
Start-Up Behaviour
The start-up behaviour of the application circuit per page 133 is represented on page 135 for a line
voltage barely above the lower acceptable limit time
t
0
the following voltages built up:
V
16
corresponding to the half-wave charge current over
R
1
V
2
to
V
2 max
(typically 6.6 V)
V
3
to the value determined by the divider
R
10
/
R
11
.
The current drawn by the IC in this case is less than 0.8 mA.
If
V
16
reaches the threshold
V
16 E
(time point
t
1
), the IC switches on the internal reference voltage.
The current draw max. rises to 12 mA. The primary current-voltage reproducer regulates
V
2
down
to
V
2B
and the starting impulse generator generates the starting impulses from time point
t
5
to
t
6
.
The feedback to pin 18 starts the next impulse and so on. All impulses including the starting impulse
are controlled in width by regulating voltage of pin 1. When switching on this corresponds to a short-
circuit event, i.e.
V
1
= 0. Hence the IC starts up with "short-circuit impulses" to assume a width
depending on the regulating voltage feedback (the IC operates in the overload range). The IC
operates at the overload point. Thereafter the peak values of
V
2
decrease rapidly, as the starting
attempt is aborted (pin 15 is switched to low). As the IC remains switched on,
V
16
further decreases
to
V
16
. The IC switches off;
V
16
can rise again (time point
t
4
) and a new start-up attempt begins at
time point
t
1
. If the rectified alternating line voltage (primary voltage) collapses during load,
V
3
can
fall below
V
3 A
, as is happening at time point
t
3
(switch-on attempt when voltage is too low). The
primary voltage monitor then clamps
V
3
to
V
3 S
until the IC switches off (
V
16
<
V
16 A
). Then a new
start-up attempt begins at time point
t
1
.
Semiconductor Group
8
SPH 4692
Regulation, Overload and No-Load Behaviour
When the IC has started up, it is operating in the regulation range. The potential at pin 1 typically is
400 mV. If the output is loaded, the regulation amplifier allows broader impulses (
V
15
= H). The peak
voltage value at pin 2 increases up to
V
2S max
. If the secondary load is further increased, the
overload amplifier begins to regulate the pulse width downward. This point is referred to as the
overload point of the power supply. As the IC supply voltage
V
16
is directly proportional to the
secondary voltage, it goes down in accordance with the overload regulation behaviour. If
V
16
falls
below the value
V
16 min
, the IC goes into burst operation. As the time constant of the half-wave
charge-up is relatively large, the short-circuit power remains small. The overload amplifier cuts back
to the pulse width
t
pk
. This pulse width must remain possible, in order to permit the IC to start-up
without problems from the virtual short-circuit, which every switching on with
V
1
= 0 represents. If
the secondary side is unloaded, the loading impulses (
V
15
= H) become shorter. The frequency
increases up to the resonance frequency of the system. If the load is further reduced, the secondary
voltages and
V
16
increase. When
V
16
=
V
16 max
, the logic is blocked. The IC converts to burst
operation. This renders the circuit absolutely safe under no-load conditions.
Behaviour when Temperature Exceeds Limit
An integrated temperature protection disables the logic when the chip temperature becomes too
high. The IC automatically interrogates the temperature and starts as soon as the temperature
decreases to permissible values.
Semiconductor Group
9
SPH 4692
Absolute Maximum Ratings
T
A
= 20 to 85 °C
Parameter
Symbol
Limit Values
Unit
Remarks
min.
typ.
max.
Control Circuit
Voltage
pin 1
pin 2
pin 3
pin 15
pin 16
pin 17
V
1
V
2
V
3
V
15
V
16
V
17
0.3
0.3
0.3
0.3
0.3
0.3
3
V
16
20
V
V
V
V
V
V
Supply voltage
Current
pin 1
pin 2
pin 3
pin 4
pin 15
pin 16
pin 17
pin 18
I
1
I
2
I
3
I
4
I
15
I
16
I
17
I
18
1.5
0.5
5
3
3
3
1.5
0.5
3
3
mA
mA
mA
A
A
A
mA
mA
t
p
50
µ
s; v
0.1
t
p
50
µ
s; v
0.1
t
p
50
µ
s; v
0.1
Junction temperature
T
j
125
°C
Storage temperature
T
stg
40
125
°C
Power MOSFET
Drain current
I
D
2
A
T
A
= 25 °C
Pulsed drain current
I
D pulse
4.5
A
T
A
= 25 °C
Gate source voltage
V
GS
20
+ 20
V
Power dissipation
P
D
1.7
W
T
A
= 25 °C
Single pulse
Avalanche Energy
E
AS
220
mJ
I
D
= 3.3 A;
V
DD
= 50 V
R
GS
= 25
;
L
= 30 mH
Repetitive avalanche Energy
E
AR
6
mJ
limited by
T
j
Avalanche current
repet. or non-repet.
I
AR
3.3
A
limited by
T
j max
Junction temperature
T
j
150
°C
Semiconductor Group
10
SPH 4692
Operating Range
Storage temperature
T
stg
40
125
°C
Thermal resistance
system-air
R
th SA
70
K/W
Cooling surface
100 mm
2
Parameter
Symbol
Limit Values
Unit
Remarks
min.
typ.
max.
Control Circuit
Supply voltage
V
16
7.5
15.5
V
IC "on"
Ambient temperature
T
A
20
85
°C
Heat resistance
Junction to environment
Junction to package
R
th JE
R
th JG
100
70
K/W
K/W
measured at pin 4
Absolute Maximum Ratings (cont'd)
T
A
= 20 to 85 °C
Parameter
Symbol
Limit Values
Unit
Remarks
min.
typ.
max.
Semiconductor Group
11
SPH 4692
Characteristics
T
A
= 25 °C;
V
S
= 10 V
Parameter
Symbol
Limit Values
Unit
Test Condition
Test
Circuit
min.
typ.
max.
Control Circuit
Start-Up Hysteresis
Start-up current
I
16 E0
0.6
0.8
mA
V
16
=
V
16 E
1
Switch-on voltage
V
16 E
11
12
13
V
1
Switch-off voltage
V
16 A
4.5
5
5.5
V
1
Switch-on current
I
16 E1
11
mA
V
16
=
V
16 E
1
Switch-off current
I
16 A1
10
mA
V
16
=
V
16 A
1
Voltage Clamp (
V
16
= 10 V,
I
C switched-off)
At pin 2 (
V
16
<
V
16 E
)
V
2 max
5.6
6.6
8
V
I
2
= 1 mA
1
At pin 3 (
V
16
<
V
16 E
)
V
3 max
5.6
6.6
8
V
I
3
= 1 mA
1
Control Range
Control input voltage
V
1 R
390
400
410
mV
2
Voltage gain of the
control circuit in the
control range
V
R
43
dB
V
R
= d (
V
2S
V
2B
)/
d
V
1
f
= 1 kHz
2
Primary Current Simulation Voltage
Basic value
V
2 B
0.97
1.00
1.03
V
2
Overload Range and Short-Circuit Operation
Peak value in the range
of secondary overload
V
2 B
2.9
3.0
3.1
V
V
1
=
V
1R
10 mV
2
Peak value in the range
of secondary short
circuit operation
V
2 K
2.2
2.4
2.9
V
V
1
= 0
2
Fold-Back Point Correction
Fold-back point
correction current
I
2
300
500
650
µ
A
V
3
= 3.7 V
1
Semiconductor Group
12
SPH 4692
Generally Valid Data (
V
16
= 10 V)
Voltage of the Zero Transition Detector
Positive clamping
V
18 P
0.75
V
I
18
= 1 mA
2
Negative clamping
V
18 N
0.2
V
I
18
= 1 mA
2
Threshold value
V
18 S
40
50
mV
2
Suppression of
transformer ringing
t
UL
3.0
3.4
3.8
µ
s
2
Input current
I
18
0
4
µ
A
V
18
= 0
Push-Pull Output Stage
Saturation voltages:
Pin 15 sourcing
Pin 15 sinking
Pin 15 sinking
V
Sat 0
V
Sat V
V
Sat V
1.5
1.0
1.4
2.0
1.2
1.8
V
V
V
I
15
= 0.1 A
I
15
= + 0.1 A
I
15
= + 0.5 A
1
1
1
Output Slew Rate
Rising edge
+ d
V
15
/
d
t
70
V/
µ
s
2
Falling edge
d
V
15
/d
t
100
V/
µ
s
2
Reduction of Control Voltage
Current to reduce the
control voltage
I
1
50
µ
A
V
17
= 1.1 V
Characteristics (cont'd)
T
A
= 25 °C;
V
S
= 10 V
Parameter
Symbol
Limit Values
Unit
Test Condition
Test
Circuit
min.
typ.
max.
Semiconductor Group
13
SPH 4692
Protection Circuit
Undervoltage protection
for
V
16
: voltage at
pin 15 =
V
15 min
if
V
16
<
V
16 min
V
16 min
7.0
7.25
7.5
V
2
Undervoltage protection
for
V
16
: voltage at
pin 15 =
V
15 min
if
V
16
>
V
16 max
V
16 max
15.5
16
16.5
V
2
Undervoltage protection
for Vac: voltage at
pin 15 =
V
15 min
if
V
3
<
V
3 A
V
3 A
985
1000
1015
mV
V
2
= 0 V
1
Over temperature: at the
given chip temperature
the IC will switch
V
15
to
V
15 min
T
j
150
°C
2
Voltage at pin 3 if one of
the protection function
was triggered; (
V
3
will be
clamped until
V
16
<
V
16
A
)
V
3 Sat
0.4
0.8
V
I
3
= 750
µ
A
1
Current drain during
burst operation
I
16
8
mA
V
3
= V
2
= 0 V
1
Characteristics (cont'd)
T
A
= 25 °C;
V
S
= 10 V
Parameter
Symbol
Limit Values
Unit
Test Condition
Test
Circuit
min.
typ.
max.
Semiconductor Group
14
SPH 4692
Power MOSFET
Static Ratings
Drain source breakdown
voltage
V
BR DSS
600
V
V
GS
= 0 V;
I
D
= 0.25 mA
Gate threshold voltage
controlled by
TDA 4605-3
V
GS th
2.1
3.0
4.0
V
V
GS
=
V
DS
;
I
D
= 1 mA
Zero gate voltage drain
current
I
DSS
0.1
1.0
µ
A
T
j
= 25 °C
V
DS
= 600 V
V
GS
= 0 V
Zero gate voltage drain
current
I
DSS
10
100
µ
A
T
j
= 125 °C
V
DS
= 600 V
V
GS
= 0 V
Drain source on-state
resistance
R
DS ON
2.6
3.0
Dynamic Ratings
Forward
transconductance
g
fs
2.1
3.0
S
V
DS
= 2 x
I
D
x
R
DS (ON) max
I
D
= 2.0 A
Input capacitance
C
Iss
600
900
pF
V
GS
= 0 V
V
DS
= 25 V
f
= 1 MHz
Output capacitance
C
Oss
65
100
pF
V
GS
= 0 V
V
DS
= 25 V
f
= 1 MHz
Reverse transfer
capacitance
C
rs
25
40
pF
V
GS
= 0 V
V
DS
= 25 V
f
= 1 MHz
Turn-on delay time
t
d ON
10
15
ns
V
CC
= 300 V
V
GS
= 10 V
I
D
= 2.3 A
R
GS
= 50
Characteristics (cont'd)
T
A
= 25 °C;
V
S
= 10 V
Parameter
Symbol
Limit Values
Unit
Test Condition
Test
Circuit
min.
typ.
max.
Semiconductor Group
15
SPH 4692
Rise time
t
r
50
70
ns
V
CC
= 30 V
V
GS
= 10 V
I
D
= 2.3 A
R
GS
= 50
Turn-off delay time
t
d OFF
70
95
ns
V
CC
= 30 V
V
GS
= 10 V
I
D
= 2.3 A
R
GS
= 50
Fall time
t
f
40
55
ns
V
CC
= 30 V
V
GS
= 10 V
I
D
= 2.3 A
R
GS
= 50
Reverse Diode
Continuous reverse
drain current
I
S
0.52
A
Pulsed reverse drain
current
I
SM
3.2
A
Diode forward
V
SD
1.0
1.4
V
V
GS
= 0 V
I
F
= 2.8 A
Reverse recovery time
t
rr
350
ns
V
R
= 100 V
I
F
= 2.8 A
d
I
F
/d
t
= 100 A
/µ
s
Reverse recovery
charge
Q
rr
2.5
µ
C
V
R
= 100 V
I
F
= 2.8 A
d
I
F
/d
t
= 100 A
/µ
s
Characteristics (cont'd)
T
A
= 25 °C;
V
S
= 10 V
Parameter
Symbol
Limit Values
Unit
Test Condition
Test
Circuit
min.
typ.
max.
Semiconductor Group
16
SPH 4692
Test Circuit 1
Test Circuit 2
Semiconductor Group
17
SPH 4692
Application Circuit
Semiconductor Group
18
SPH 4692
Diagrams
Semiconductor Group
19
SPH 4692
Semiconductor Group
20
SPH 4692
Start-Up Hysteresis
Semiconductor Group
21
SPH 4692
Operation in Test Circuit 2
Semiconductor Group
22
SPH 4692
Start-Up Current as a Function of the
Ambient Temperature
Overload Point Correction as a Function of
the Voltage at Pin 3
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