Part Number LH543601

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LH543601

256

2 Bidirectional FIFO

FEATURES

Fast Cycle Times: 20/25/30/35 ns

Pin-Compatible and Functionally-Compatible
0.7

-Technology Replacement for Sharp LH5420

Two 256

36-bit FIFO Buffers

Full 36-bit Word Width

Selectable 36/18/9-bit Word Width on Port B

Independently-Synchronized (`Fully-Asynchronous')
Operation of Port A and Port B

`Synchronous' Enable-Plus-Clock Control at
Both Ports

R/W, Enable, Request, and Address Control Inputs
are Sampled on the Rising Clock Edge

Synchronous Request/Acknowledge `Handshake'
Capability; Use is Optional

Device Comes Up Into a Known Default State at
Reset; Programming is Allowed, but is not Required

Asynchronous Output Enables

Five Status Flags per Port: Full, Almost-Full,
Half-Full, Almost-Empty, and Empty

Almost-Full Flag and Almost-Empty Flag are
Programmable

Mailbox Registers with Synchronized Flags

Data-Bypass Function

Data-Retransmit Function

Automatic Byte Parity Checking

8 mA-I

High-Drive Three-State Outputs with

Built-In Series Resistor

TTL/CMOS-Compatible I/O

Space-Saving PQFP and TQFP Packages

PQFP to PGA Package Conversion

FUNCTIONAL DESCRIPTION

The LH543601 contains two FIFO buffers, FIFO #1

and FIFO #2. These operate in parallel, but in opposite
directions, for bidirectional data buffering. FIFO #1 and
FIFO #2 each are organized as 256 by 36 bits. The
LH543601 is ideal either for wide unidirectional applica-
tions or for bidirectional data applications; component
count and board area are reduced.

The LH543601 has two 36-bit ports, Port A and Port B.

Each port has its own port-synchronous clock, but the two
ports may operate asynchronously relative to each other.
Data flow is initiated at a port by the rising edge of the
appropriate clock; it is gated by the corresponding edge-
sampled enable, request, and read/write control signals.
At the maximum operating frequency, the clock duty cycle
may vary from 40% to 60%. At lower frequencies, the
clock waveform may be quite asymmetric, as long as the
minimum pulse-width conditions for clock-HIGH and
clock-LOW remain satisfied; the LH543601 is a fully-static
part.

Conceptually, the port clocks CK

and CK

are free-

running, periodic `clock' waveforms, used to control other
signals which are edge-sensitive. However, there actually
is not any absolute requirement that these `clock' wave-
forms

must

be periodic. An `asynchronous' mode of

operation is possible, in one or both directions, inde-
pendently, if the appropriate enable and request inputs
are continuously asserted, and enough aperiodic `clock'
pulses of suitable duration are generated by external logic
to cause all necessary actions to occur.

A synchronous request/acknowledge handshake

facility is provided at each port for FIFO data access. This
request/ acknowledge handshake resolves FIFO full and
empty boundary conditions, when the two ports are op-
erated asynchronously relative to each other.

FIFO status flags monitor the extent to which each

FIFO buffer has been filled. Full, Almost-Full, Half-Full,
Almost-Empty, and Empty flags are included for

each

FIFO. The Almost-Full and Almost-Empty flags are pro-
grammable over the entire FIFO depth, but are automat-
ically initialized to eight locations from the respective FIFO
boundaries at reset. A data block of 256 or fewer words
may be retransmitted any desired number of times.

NOTE:
1. For PQFP-to-PGA conversion for thru-hole board designs, Sharp

recommends ITT Pomona Electronics' SMT/PGA Generic
Converter model #5853.

This converter maps the LH543601

132-pin PQFP to a generic 13

13, 132-pin PGA (100-mil

pitch). For more information, contact Sharp or ITT Pomona
Electronics at 1500 East Ninth Street, Pomona, CA 91766,
(909) 469-2900.

FUNCTIONAL DESCRIPTION (cont'd)

Two mailbox registers provide a separate path for

passing control words or status words between ports.
Each mailbox has a New-Mail-Alert Flag, which is syn-
chronized to the reading port's clock. This mailbox func-
tion facilitates the synchronization of data transfers
between asynchronous systems.

Data-bypass mode allows Port A to directly transfer

data to or from Port B at reset. In this mode, the device
acts as a registered transceiver under the control of
Port A. For instance, a master processor on Port A can
use the data bypass feature to send or receive initializa-

tion or configuration information directly, to or from a
peripheral device on Port B, during system startup.

A word-width-select option is provided on Port B for

36-bit, 18-bit, or 9-bit data access. This feature allows
word-width matching between Port A and Port B, with no
additional logic needed. It also ensures maximum utiliza-
tion of bus bandwidths.

A Byte Parity Check Flag at each port monitors data

integrity. Control-Register bit 0 (zero) selects the parity
mode, odd or even. This bit is initialized for odd data parity
at reset; but it may be reprogrammed for even parity, or
back again to odd parity, as desired.

116

115
114
113
112

111

110
109
108
107
106
105
104
103
102

101

100

99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84

19
20
21
22

23
24
25
26
27
28
29
30
31
32

33
34

36
37
38
39

41
42
43
44
45
46
47
48

CCO

10A

SSO

10B

11B

CCO

SSO

CCO

SSO

CCO

49
50

CCO

24A

25A

26A

SSO

27A

28A

29A

30A

31A

32A

33A

34A

35A

35B

34B

33B

32B

31B

30B

29B

28B

27B

26B

25B

CCO

SSO

CCO

SSO

CCO

Pin 1

Pin 132

131

130

129

128

127

126

125

124

123

122

121

120

119

118

117

12A

13A

14A

SSO

15A

16A

17A

R/W

ACK

MBF

18A

19A

20A

21A

22A

REQ

SSO

11A

12B

13B

14B

SSO

15B

16B

17B

REQ

R/W

18B

19B

20B

21B

22B

SSO

MBF

ACK

543601-30

TOP VIEW

CHAMFERED

EDGE

Figure 1. Pin Connections for 132-Pin PQFP Package

(Top View)

PIN CONNECTIONS

LH543601

256

2 Bidirectional FIFO

108
107
106
105
104
103
102
101
100

99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18

19
20
21
22
23
24
25
26
27
28
29
30
31

24A

25A

27A

28A

30A

31A

33A

34B

33B

31B

30B

28B

27B

32
33

128

127

CCO

10A

SSO

CCO

SSO

NC
D

SSO

CCO

SSO

10B

144

143

142

141

140

139

138

137

136

135

134

133

132

131

130

129

126

125

124

123

122

121

120

119

118

117

116

115

114

113

112

23A

22A

21A

SSO

19A

18A

ACK

REQ

R/W

17A

15A

SSO

14A

13A

24B

23B

SSO

22B

20B

R/W

REQ

ACK

MBF

16B

SSO

17B

15B

14B

TOP VIEW

MBF

543601-38

34
35
36

CCO

11B

CCO

75
74
73

111

110

12A

11A

109

13B

12B

CCO

26A

SSO

29A

CCO

32A

SSO

34A

35A

SSO

32B

CCO

29B

SSO

26B

25B

21B

19B

18B

20A

16A

35B

144-PIN TQFP

Figure 2. Pin Connections for 144-Pin TQFP Package

(Top View)

256

2 Bidirectional FIFO

LH543601

PIN LIST

SIGNAL

NAME

PQFP

PIN NO.

TQFP

PIN NO.

126

125

124

123

121

120

119

118

17A

117

16A

116

15A

115

14A

113

13A

112

12A

111

11A

110

10A

106

105

104

102

101

100

10B

11B

12B

13B

14B

15B

SIGNAL

NAME

PQFP

PIN NO.

TQFP

PIN NO.

16B

17B

MBF

ACK

REQ

R/W

18B

19B

20B

21B

22B

23B

24B

25B

26B

27B

28B

29B

30B

31B

32B

33B

34B

35B

100

35A

101

34A

102

33A

103

32A

105

31A

106

30A

107

29A

109

SIGNAL

NAME

PQFP

PIN NO.

TQFP

PIN NO.

28A

110

27A

111

26A

113

25A

114

24A

115

23A

117

143

22A

118

142

21A

119

141

20A

120

140

19A

122

138

18A

123

137

MBF

124

136

125

135

126

134

ACK

127

133

REQ

129

131

130

R/W

131

129

132

128

122

SSO

114

109

108

CCO

107

SSO

103

CCO

SSO

CCO

SSO

CCO

SSO

CCO

SSO

CCO

NOTE:

PINS

COMMENTS

Supply internal logic. Connected to each other.

CCO

Supply output drivers only. Connected to each
other.

PINS

COMMENTS

Supply internal logic. Connected to each other.

SSO

Supply output drivers only. Connected to each
other.

LH543601

256

2 Bidirectional FIFO

RESET

LOGIC

PORT A

I/O

PORT A

SYNCH-

RONOUS

CONTROL

LOGIC

READ

POINTER

WRITE

POINTER

FIXED AND

PROGRAMMABLE

STATUS FLAGS

FIFO #1

MEMORY ARRAY

256 x 36

MAILBOX

READ

POINTER

WRITE

POINTER

FIFO #2

MEMORY ARRAY

256 x 36

PORT B

I/O

, WS

- D

35A

ACK

REQ

R/W

- D

35B

ACK

REQ

R/W

COMMAND

PORT AND
REGISTER

PARITY

CHECKING

RESOURCE

REGISTERS

PARITY

CHECKING

COMMAND

PORT AND
REGISTER

MAILBOX

BYPASS

MBF

PORT B

SYNCH-

RONOUS

CONTROL

LOGIC

FIXED AND

PROGRAMMABLE

STATUS FLAGS

543601-6

Figure 3b. Detailed LH543601 Block Diagram

FIFO 1

PORT A

I/O

FIFO 2

PORT B

I/O

WRITE

READ

WRITE

READ

PORT A

CONTROL

PORT B

CONTROL

543601-36

Figure 3a. Simplified LH543601 Block Diagram

256

2 Bidirectional FIFO

LH543601

PIN DESCRIPTIONS

PIN

PIN TYPE

DESCRIPTION

GENERAL

, V

Power, Ground

Reset

PORT A

Port A Free-Running Clock

R/W

Port A Edge-Sampled Read/Write Control

Port A Edge-Sampled Enable

, A

Port A Edge-Sampled Address Pins

Port A Level-Sensitive Output Enable

REQ

Port A Request/Enable

FIFO #2 Retransmit

35A

I/O/Z

Port A Bidirectional Data Bus

FIFO #1 Full Flag (Write Boundary)

FIFO #1 Programmable Almost-Full Flag (Write Boundary)

FIFO #1 Half-Full Flag

FIFO #2 Programmable Almost-Empty Flag (Read Boundary)

FIFO #2 Empty Flag (Read Boundary)

MBF

New-Mail-Alert Flag for Mailbox #2

Port A Parity Flag

ACK

Port A Acknowledge

PORT B

Port B Free-Running Clock

R/W

Port B Edge-Sampled Read/Write Control

Port B Edge-Sampled Enable

Port B Edge-Sampled Address Pin

Port B Level-Sensitive Output Enable

, WS

Port B Word-Width Select

REQ

Port B Request/Enable

FIFO #1 Retransmit

35B

I/O/Z

Port B Bidirectional Data Bus

FIFO #2 Full Flag (Write Boundary)

FIFO #2 Programmable Almost-Full Flag (Write Boundary)

FIFO #2 Half-Full Flag

FIFO #1 Programmable Almost-Empty Flag (Read Boundary)

FIFO #1 Empty Flag (Read Boundary)

MBF

New-Mail-Alert Flag for Mailbox #1

Port B Parity Flag

ACK

Port B Acknowledge

NOTE:
1.

I = Input, O = Output, Z = High-Impedance, V = Power Voltage Level

LH543601

256

2 Bidirectional FIFO

ABSOLUTE MAXIMUM RATINGS

PARAMETER

RATING

Supply Voltage to V

Potential

0 .5 V to 7 V

Signal Pin Voltage to V

Potential

0 .5 V to V

+ 0.5 V

DC Output Current

40 mA

Storage Temperature Range

6 5

C to 150

Power Dissipation (Package Limit)

2 Watts (Quad Flat Pack)

NOTES:

Stresses greater than those listed under `Absolute Maximum Ratings' may cause
permanent damage to the device. This is a stress rating for transient conditions only.
Functional operation of the device at these or any other conditions outside those indicated
in the `Operating Range' of this specification is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect reliability.

Outputs should not be shorted for more than 30 seconds. No more than one output should be
shorted at any time.

Negative undershoot of 1.5 V in amplitude is permitted for up to 10 ns, once per cycle.

OPERATING RANGE

SYMBOL

PARAMETER

MIN

MAX

UNIT

Temperature,
Ambient

Supply Voltage

4.5

5.5

Supply Voltage

Logic LOW
Input Voltage

0 .5

0.8

Logic HIGH
Input Voltage

2.2

Vcc +

0.5

NOTE:
1.

Negative undershoot of 1.5 V in amplitude is permitted
for up to 10 ns, once per cycle.

DC ELECTRICAL CHARACTERISTICS (Over Operating Range)

SYMBOL

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Input Leakage Current

= 5.5 V, V

= 0 V To V

I/O Leakage Current

, 0 V

OUT

Logic LOW Output Voltage

= 8.0 mA

0.4

Logic HIGH Output Voltage

= 8 .0 mA

2.4

Average Supply Current

1, 2

Measured at f

= max

180

280

CC2

Average Standby Supply
Current

1, 3

All Inputs = V

IHMIN

(Clocks idle)

CC3

Power-Down Supply
Current

All Inputs = V

0.2 V (Clocks idle)

0.002

0.4

CC4

Power-Down Supply
Current

1, 3

All Inputs = V

0.2 V

(Clocks at fcc = max)

NOTES:
1.

, I

CC2

, I

CC3

, and I

CC4

are dependent upon actual output loading, and I

and I

CC4

are also dependent on cycle rates. Specified values are

with outputs open (for I

: C

= 0 pF); and, for I

and I

CC4

, operating at minimum cycle times.

(MAX.) using worst case conditions and data pattern. I

(TYP.) using V

= 5 V and and `average' data pattern.

CC2

(TYP.) and I

CC4

(TYP.) using V

= 5 V and T

= 25

543601-39

TO ASSOCIATED

INPUT BUFFER,

IF ANY (SEE NOTE)

FROM PORT

INTERNAL
DATA BUS

(OR CONTROL

GATE)

nA/B

(OR FLAG)

NOTE: Output-only pins have no
associated input buffer.

Figure 4. Structure of Series Resistor

Input/Output Interface

256

2 Bidirectional FIFO

LH543601

AC TEST CONDITIONS

PARAMETER

RATING

Input Pulse Levels

to 3 V

Input Rise and Fall Times
(10%

90%)

5 ns

Output Reference Levels

1.5 V

Input Timing Reference Levels

1.5 V

Output Load, Timing Tests

Figure 5

CAPACITANCE

1,2

PARAMETER

RATING

(Input Capacitance)

8 pF

OUT

(Output Capacitance)

8 pF

NOTES:
1.

Sample tested only.

Capacitances are maximum values at 25

C, measured at 1.0MHz,

with V

= 0 V.

DEVICE

UNDER

TEST

+5 V

30 pF

470

240

INCLUDES JIG AND SCOPE CAPACITANCES

543601-7

Figure 5. Output Load Circuit

LH543601

256

2 Bidirectional FIFO

AC ELECTRICAL CHARACTERISTICS

= 5 V

10%, T

= 0

C to 70

SYMBOL

DECRIPTION

20

25

30

35

UNITS

MIN

MAX

MIN

MAX

MIN

MAX

MIN

MAX

Clock Cycle Frequency

28.5

MHz

Clock Cycle Time

Clock HIGH Time

Clock LOW Time

Data Setup Time

Data Hold Time

Enable Setup Time

10.4

Enable Hold Time

RWS

Read/Write Setup Time

10.4

RWH

Read/Write Hold Time

RQS

Request Setup Time

RQH

Request Hold Time

Address Setup Time

Address Hold Time

Data Output Access Time

12.8

ACK

Acknowledge Access Time

Output Hold Time

2.0

Output Enable Time, OE LOW to D

Low-Z

1.5

2.0

3.0

Output Disable Time, OE HIGH to
D

High-Z

Clock to EF Flag Valid (Empty Flag)

17.6

Clock to FF Flag Valid (Full Flag)

17.6

Clock to HF Flag Valid (Half-Full)

17.6

Clock to AE Flag Valid (Almost-
Empty)

Clock to AF Flag Valid (Almost-Full)

MBF

Clock to MBF Flag Valid (Mailbox
Flag)

Data to Parity Flag Valid

13.6

Reset/Retransmit Pulse Width

32/20

40/25

52/30

65/35

RSS

Reset/Retransmit Setup Time

RSH

Reset/Retransmit Hold Time

Reset LOW to Flag Valid

FRL

First Read Latency

FWL

First Write Latency

Bypass Data Setup

Bypass Data Hold

Bypass Data Access

NOTES:

Timing measurements performed at `AC Test Condition' levels.

Values are guaranteed by design; not currently production tested.

RSS

and/or t

RSH

need not be met unless a rising edge of CK

occurs while EN

is being asserted, or else a rising edge of CK

occurs while

is being asserted.

FRL

is the minimum first-write-to-first-read delay, following an empty condition, which is required to assure valid read data.

FWL

is the minimum first-read-to-first-write delay, following a full condtion, which is required to assure successful writing of data.

256

2 Bidirectional FIFO

LH543601

OPERATIONAL DESCRIPTION

Reset

The device is reset whenever the asynchronous Reset

(RS) input is taken LOW, and at least one rising edge and
one falling edge of both CK

and CK

occur while RS is

LOW. A reset operation is required after power-up, before
the first write operation may occur. The LH543601 is fully
ready for operation after being reset. No device program-
ming is required if the default states described below are
acceptable.

A reset operation initializes the read-address and

write-address pointers for FIFO #1 and FIFO #2 to those
FIFO's first physical memory locations. If the respective
outputs are enabled, the initial contents of these first
locations appear at the outputs. FIFO and mailbox status
flags are updated to indicate an empty condition. In
addition, the programmable-status-flag offset values are
initialized to eight. Thus, the AE

/AE

flags get asserted

within eight locations of an empty condition, and the
AF

/AF

flags likewise get asserted within eight locations

of a full condition, for FIFO #1/FIFO #2 respectively.

Bypass Operation

During reset (whenever RS is LOW) the device acts

as a registered transceiver, bypassing the internal FIFO
memories. Port A acts as the master port. A write or read
operation on Port A during reset transfers data directly to
or from Port B. Port B is considered to be the slave, and
cannot perform write or read operations independently on
its own during reset.

The direction of the bypass data transmission is deter-

mined by th R/W

control input, which does not get

overridden by the RS input. Here, a `write' operation
means passing data from Port A to Port B, and a `read'
operation means passing data from Port B to Port A.

The bypass capability may be used to pass initializa-

tion or configuration data directly between a master proc-
essor and a peripheral device during reset.

Address Modes

Address pins select the device resource to be

accessed by each port. Port A has three resource-regis-
ter-select inputs, A

, A

, and A

, which select between

FIFO access, mailbox-register access, control-register
access (write only), and programmable flag-offset-value-
register access. Port B has a single address input, A

to select between FIFO access or mailbox-register ac-
cess.

The status of the resource-register-select inputs is

sampled at the rising edge of an enabled clock (CK

). Resource-register select-input address definitions

are summarized in Table 1.

FIFO Write

Port A writes to FIFO #1, and Port B writes to FIFO #2.

A write operation is initiated on the rising edge of a clock

(CK

or CK

) whenever: the appropriate enable (EN

) is held HIGH; the appropriate request (REQ

REQ

) is held HIGH; the appropriate Read/Write control

(R/W

or R/W

) is held LOW; the FIFO address is

selected for the address inputs (A

or A

); and

the prescribed setup times and hold times are observed
for all of these signals. Setup times and hold times must
also be observed on the data-bus pins (D

35A

35B

Normally, the appropriate Output Enable signal (OE

or OE

) is HIGH, to disable the outputs at that port, so

that the data word present on the bus from external
sources gets stored. However, a `loopback' mode of
operation also is possible, in which the data word supplied
by the outputs of one internal FIFO is `turned around' at
the port and read back into the other FIFO. In this mode,
the outputs at the port are not disabled. To remain within
specification for all timing parameters, the Clock Cycle
Frequency must be reduced slightly below the value
which otherwise would be permissible for that speed
grade of LH543601.

When a FIFO full condition is reached, write operations

are locked out. Following the first read operation from a
full FIFO, another memory location is freed up, and the
corresponding Full Flag is deasserted (FF = HIGH). The
first write operation should begin no earlier than a First
Write Latency (t

FWL

) after the first read operation from a

full FIFO, to ensure that correct read data are retrieved.

FIFO Read

Port A reads from FIFO #2, and Port B reads from FIFO

#1. A read operation is initiated on the rising edge of
a clock (CK

or CK

) whenever: the appropriate enable

(EN

or EN

) is held HIGH; the appropriate request

(REQ

o r REQ

) is held HIGH; the appropri ate

Read/Write control (R/W

or R/W

) is held HIGH;

the FIFO address is selected for the address inputs
(A

or A

); and the prescribed setup times and

hold times are observed for all of these signals. Read data

Table 1. Resource-Register Addresses

RESOURCE

PORT A

FIFO

Mailbox

, AE

, AF

, AE

Flag Offsets

Control Register (Parity Mode)

Flag Offset Register

RESOURCE

PORT B

FIFO

Mailbox

LH543601

256

2 Bidirectional FIFO

becomes valid on the data-bus pins (D

35A

35B

) by a time t

after the rising clock (CK

) edge, provided that the data outputs are enabled.

and OE

are assertive-LOW, asynchronous, Out-

put Enable control input signals. Their effect is only to
enable or disable the output drivers of the respective port.
Disabling the outputs does

not disable a read operation;

data transmitted to the corresponding output register will
remain available later, when the outputs again are en-
abled, unless it subsequently is overwritten.

When an empty condition is reached, read operations

are locked out until a valid write operation(s) has loaded
additional data into the FIFO. Following the first write to
an empty FIFO, the corresponding empty flag (EF) will be
deasserted (HIGH). The first read operation should begin
no earlier than a First Read Latency (t

FRL

) after the first

write to an empty FIFO, to ensure that correct read data
words are retrieved.

Dedicated FIFO Status Flags

Six dedicated FIFO status flags are included for Full

(FF

and FF

), Half-Full (HF

and HF

), and Empty (EF

and EF

). FF

, HF

, and EF

indicate the status of FIFO

#1; and FF

, HF

, and EF

indicate the status of FIFO #2.

A Full Flag is asserted following the first subsequent

rising clock edge for a write operation which fills the FIFO.
A Full Flag is deasserted following the first subsequent
falling clock edge for a read operation to a full FIFO. A
Half-Full Flag is updated following the first subsequent
rising clock edge of a read or write operation to a FIFO
which changes its `half-full' status. An Empty Flag is
asserted following the first subsequent rising clock edge
for a read operation which empties the FIFO. An Empty
Flag is deasserted following the falling clock edge for a
write operation to an empty FIFO.

Programmable Status Flags

Four programmable FIFO status flags are provided,

two for Almost-Full (AF

and AF

), and two for Almost-

Empty (AE

and AE

). Thus, each port has two program-

mable flags to monitor the status of the two internal FIFO
buffer memories. The offset values for these flags are
initialized to eight locations from the respective FIFO
boundaries during reset, but can be reprogrammed over
the entire FIFO depth.

An Almost-Full Flag is asserted following the first sub-

sequent rising clock edge after a write operation which
has partially filled the FIFO up to the `almost-full' offset
point. An Almost-Full Flag is deasserted following the first
subsequent falling clock edge after a read operation
which has partially emptied the FIFO down past the
`almost-full' offset point. An Almost-Empty Flag is as-
serted following the first subsequent rising clock edge
after a read operation which has partially emptied the
FIFO down to the `almost-empty' offset point. An Almost-
Empty Flag is deasserted following the first subsequent

falling clock edge after a write operation which has par-
tially filled the FIFO up past the `almost-empty' offset
point.

Flag offsets may be written or read through the Port A

data bus. All four programmable FIFO status flag offsets
can be set simultaneously through a single 36-bit status
word; or, each programmable flag offset can be set
individually, through one of four eight-bit status words.
Table 3 illustrates the data format for flag-programming
words .

Also, Table 4 defines the meaning of each of the five

flags, both the dedicated flags and the programmable
flags, for the LH543601.

WARNING: Control inputs which may affect the compu-
tation of flag values at a port generally should not change
while the clock for that port is HIGH, since some updating
of flag values takes place on the

falling edge of the clock.

Mailbox Operation

Two mailbox registers are provided for passing system

hardware or software control/status words between ports.
Each port can read its own mailbox and write to the other
port's mailbox. Mailbox access is performed on the rising
edge of the controlling FIFO's clock, with the mailbox
address selected and the enable (EN

or EN

) HIGH.

That is, writing to Mailbox Register #1, or reading from
Mailbox Register #2, is synchronized to CK

; and writing

to Mailbox Register #2, or reading from Mailbox Register
#1, is synchronized to CK

The R/W

A/B

and OE

A/B

pins control the direction and

availability of mailbox-register accesses. Each mailbox
register has its own New-Mail-Alert Flag (MBF

and

MBF

), which is synchronized to the reading port's clock.

These New-Mail-Alert Flags are status indicators only,
and cannot inhibit mailbox-register read or write operations.

Request Acknowledge Handshake

A synchronous request-acknowledge handshake fea-

ture is provided for each port, to perform boundary syn-
chronization between asynchronously-operated ports.
The use of this feature is optional. When it is used, the
Request input (REQ

A/B

) is sampled at a rising clock edge.

With REQ

A/B

HIGH, R/W

A/B

determines whether a FIFO

read operation or a FIFO write operation is being re-
quested. The Acknowledge output (ACK

A/B

) is updated

during the following clock cycle(s). ACK

A/B

meets the

setup and hold time requirements of the Enable input
(EN

or EN

). Therefore, ACK

A/B

may be tied back to the

enable input to directly gate FIFO accesses, at a slight
decrease in maximum operating frequency.

The assertion of ACK

A/B

signifies that REQ

A/B

was

asserted. However, ACK

A/B

does not depend logically on

A/B

; and thus the assertion of ACK

A/B

does

not prove

that a FIFO write access or a FIFO read access actually
took place. While REQ

A/B

and EN

A/B

are being held

HIGH, ACK

A/B

may be considered as a synchronous,

predictive boundary flag. That is, ACK

A/B

acts as a syn-

OPERATIONAL DESCRIPTION (cont'd)

256

2 Bidirectional FIFO

LH543601

chronized predictor of the Almost-Full Flag AF for write
operations, or as a synchronized predictor of the Almost-
Empty Flag AE for read operations.

Outside the `almost-full' region and the `almost-empty'

region, ACK

A/B

remains continuously HIGH whenever

REQ

A/B

is held continuously HIGH. Within the `almost-full'

region or the `almost-empty' region, ACK

A/B

occurs only

on every

third cycle, to prevent an overrun of the FIFO's

actual full or empty boundaries and to ensure that the t

FWL

(first write latency) and t

FRL

(first read latency) specifica-

tions are satisfied before ACK

A/B

is received.

The `almost-full region' is defined as `that region, where

the Almost-Full Flag is being asserted'; and the `almost-
empty region' as `that region, where the Almost-Empty
Flag is being asserted.' Thus, the extent of these `almost'
regions depends on how the system has programmed the
offset values for the Almost-Full Flags and the Almost-
Empty Flags. If the system has

not programmed them,

then these offset values remain at their default values,
eight in each case.

If a write attempt is unsuccessful because the corre-

sponding FIFO is full, or if a read attempt is unsuccessful
because the corresponding FIFO is empty, ACK

A/B

not

asserted in response to REQ

A/B

If the REQ/ACK handshake is not used, then the

REQ

A/B

input may be used as a second enable input, at

a possible minor loss in maximum operating speed. In this
case, the ACK

A/B

output may be ignored.

WARNING: Whether or not the REQ/ACK handshake is
being used, the REQ

A/B

input for a port

must be asserted

for that port to function at all for FIFO, mailbox, or
data-bypass operation.

Data Retransmit

A retransmit operation resets the read-address pointer of

the corresponding FIFO (#1 or #2) back to the first FIFO
physical memory location, so that data may be reread. The
write pointer is not affected. The status flags are updated;
and a block of up to 256 data words, which previously had
been written into and read from a FIFO, can be retrieved.
The block to be retransmitted is bounded by the first FIFO
memory location, and the FIFO memory location addressed
by the write pointer. FIFO #1 retransmit is initiated by
strobing the RT

pin LOW. FIFO #2 retransmit is initiated by

strobing the RT

pin LOW. Read and write operations to a

FIFO should be stopped while the corresponding Retrans-
mit signal is being asserted.

Parity Checking

The Parity Check Flags, PF

and PF

, are asserted

(LOW) whenever there is a parity error in the data word
present on the Port A data bus or the Port B data bus
respectively. The inputs to the parity-evaluation logic
come directly (via isolation transistors) from the data-bus
bonding

pads, in each case. Thus, PF

and PF

provide

parity-error indications for whatever 36-bit words are
present at Port A and Port B respectively, regardless of
whether those words originated within the LH543601 or
in the external system.

The four bytes of a 36-bit data word are grouped as D

, D

, and D

. The parity of each

nine-bit byte is individually checked, and the four single-bit
parity indications are logically inclusive-ORed and inverted,
to produce the Parity-Flag output. Parity checking is initial-
ized for odd parity at reset, but can be reprogrammed for
even parity or for odd parity during operation. Control-Reg-
ister bit 00 (zero) selects the parity mode, odd or even.
(See Table 3.)

All nine bits of each byte are treated alike by the parity

logic. The byte parity over the nine bits is compared with
the Parity Mode bit in the Control Register, to generate a
byte-parity-error indication. Then, the four byte-parity-
error signals are NORed together, to compute the asser-
tive-LOW parity-flag value.

Word-Width Selection on Port B

The word width of data access on Port B is selected

by the WS

and WS

control inputs. WS

and WS

both

are tied HIGH for 36-bit access; they both are tied LOW
for single-byte access. For double-byte access, WS

tied HIGH and WS

is tied LOW. (See Table 2.)

In the single-byte-access or double-byte-access modes,

FIFO write operations on Port B essentially pack the data to
form 36-bit words, as viewed from Port A. Similarly, single-
byte or double-byte FIFO read operations on Port B essen-
tially unpack 36-bit words through a series of shift
operations. FIFO status flags are updated following the last
access which forms a complete 36-bit transfer.

Since the values for each status flag are computed by

logic directly associated with one of the two FIFO-memory
arrays, and not by logic associated with Port B,

the flag

values reflect the array fullness situation in terms of com-
plete 36-bit words, and not in terms of bytes or double bytes.

However, there is no such restriction for switching from

writing to reading, or from reading to writing, at Port B. As
long as t

RWS

, t

, and t

are satisfied, R/W

may change

state after

any single-byte or double-byte access, and not

only after a full 36-bit-word access.

Also, the word-width-matching feature continues to

operate properly in `loopback' mode.

Note that the programmable word-width-matching fea-

ture is

only supported for FIFO accesses. Mailbox and

Data Bypass operations do

not support word-width

matching between Port A and Port B. Tables 2, 3, and 4,
and Figures 6a, 6b, 7a, and 7b summarize word-width
selection for Port B.

Table 2. Port B Word-Width Selection

PORT B DATA WIDTH

36-Bit

(Reserved)

18-Bit

9-Bit

OPERATIONAL DESCRIPTION (cont'd)

LH543601

256

2 Bidirectional FIFO

Table 3. Resource-Register Programming

RESOURCE-

REGISTER

ADDRESS

RESOURCE-REGISTER CONTENTS

NORMAL FIFO OPERATION

35A

X...

...X

MAILBOX

35A

X...

...X

, AE

, AF

, AE

FLAG OFFSETS REGISTER (36-BIT MODE)

35A

34A

. . . D

27A

26A

25A

. . . D

18A

17A

16A

. . . D

Offset

CONTROL REGISTER: (WRITE-ONLY) PARITY EVEN/ODD

35A

D0A

X...

...X

Parity Mode

8-BIT AE

FLAG OFFSET REGISTER

35A

. . . D

X...

...X

Offset

8-BIT AF

FLAG OFFSET REGISTER

35A

. . . D

X...

...X

Offset

8-BIT AE

FLAG OFFSET REGISTER

35A

. . . D

X...

...X

Offset

8-BIT AF

FLAG OFFSET REGISTER

35A

. . . D

X...

...X

Offset

NOTES:
1.

All four programmable-flag-offset values are initialized to eight (8) during a reset operation.

Odd parity = HIGH; even parity = LOW. The parity mode is initialized to odd during a reset operation.

256

2 Bidirectional FIFO

LH543601

Table 4. Flag Definition Table

FLAG

VALID READ CYCLES REMAINING

VALID WRITE CYCLES REMAINING

FLAG = LOW

FLAG = HIGH

FLAG = LOW

FLAG = HIGH

MIN

MAX

MIN

MAX

MIN

MAX

MIN

MAX

256

255

256

256-p

256

255-p

p + 1

256

129

256

128

127

128

256

q + 1

256

256-q

256

255-q

256

255

NOTES:
1.

q = Programmable-Almost-Empty Offset value. (Default value: q = 8.)

p = Programmable-Almost-Full Offset value. (Default value: p = 8.)

LH543601

256

2 Bidirectional FIFO

18-Bit Data Streams

36-Bit Data Stream

Bits 18-35
(2nd Halfword)

Bits 18-35

(2nd Halfword)

Bits 0-17

(1st Halfword)

Bits 0-17
(1st Halfword)

2nd Halfword, then 1st Halfword

1st Halfword, then 2nd Halfword

35A

18A

17A

35B

18B

17B

PORT

543601-32

Figure 6a. 36-to-18 Funneling Through FIFO #1

9-Bit Data Streams

36-Bit Data Stream

Bits 27-35
(4th Byte)

4th Byte, then 1st Byte, then 2nd Byte, then 3rd Byte

35A

27A

26A

18A

35B

27B

26B

18B

PORT

17A

17B

Bits 18-26
(3rd Byte)

Bits 9-17
(2nd Byte)

Bits 0-8
(1st Byte)

3rd Byte, then 4th Byte, then 1st Byte, then 2nd Byte

2nd Byte, then 3rd Byte, then 4th Byte, then 1st Byte

1st Byte, then 2nd Byte, then 3rd Byte, then 4th Byte

543601-34

Figure 6b. 36-to-9 Funneling Through FIFO #1

PORT B WORD-WIDTH SELECTION

NOTES:

The heavy black borders on register segments indicate the main
data path, suitable for most applications. Alternate paths feature
a different ordering of bytes within a word, at Port B.

The funneling process does not change the ordering of bits within
a byte. Halfwords (Figure 6a) or bytes (Figure 6b) are trans-
ferred in parallel form from Port A to Port B.

The word-width setting may be changed during system operation;
however, two clock intervals should be allowed for these signals
to settle, before again attempting to read D

35B

, and three

dummy words should be passed through initially. Also, incom-
plete data words may occur, when the word width is changed
from shorter to longer at an inappropriate point in the data block
passing through the FIFO.

256

2 Bidirectional FIFO

LH543601

18-Bit Data Stream

36-Bit Data Stream

Bits 18-35

(2nd Halfword)

Bits 0-17
(1st Halfword)

1st Halfword, then 2nd Halfword

35A

18A

17A

35B

18B

17B

PORT

543601-33

Figure 7a. 18-to-36 Defunneling Through FIFO #2

9-Bit Data Stream

36-Bit Data Stream

Bits 27-35
(4th Byte)

35A

27A

26A

18A

35B

27B

26B

18B

PORT

17A

17B

Bits 18-26
(3rd Byte)

Bits 9-17
(2nd Byte)

Bits 0-8
(1st Byte)

1st Byte, then 2nd Byte, then 3rd Byte, then 4th Byte

543601-35

Figure 7b. 9-to-36 Defunneling Through FIFO #2

PORT B WORD-WIDTH SELECTION

NOTES:

The heavy black borders on register segments indicate the only
data paths used. The other byte segments of Port B do not par-
ticipate in the data path during defunneling.

The defunneling process does not change the ordering of bits
within a byte. Halfwords (Figure 7a) or bytes (Figure 7b) are
transferred in parallel form from Port B to Port A.

The word-width setting may be changed during system operation;
however, two clock intervals should be allowed for these signals
to settle, before again attempting to send data, and three
dummy words should be passed through initially. Also, incom-
plete data words may occur, when the word width is changed
from shorter to longer at an inappropriate point in the data block
passing through the FIFO.

LH543601

256

2 Bidirectional FIFO

TIMING DIAGRAMS

HF, AF, FF, MBF

EF, AE

RSS

RSH

RSS

RSH

RSS

NOTES:
1. RS overrides all other input signals, except for R/W

, EN

, and REQ

. It operates

asynchronously. RS operates whether or not EN

and/or EN

are asserted. However,

at least one rising edge and one falling edge of both CK

and CK

must occur while

RS is being asserted (is LOW), with timing as defined by t

RSS

and t

RSH

2. Otherwise, t

RSS

, t

RSH

need not be met unless the rising edge of CK

and/or CK

occurs while that clock is enabled.
3. The parity-check even/odd selection (Control Register bit 00) is initialized to odd byte
parity at reset (HIGH).
4. The AE and AF flag offsets are initialized to eight locations from the boundary at reset.

543601-26

REQ

RQS

RQH

REQ

RQS

RQH

RQS

RQH

RQS

RQH

Figure 8. Reset Timing

256

2 Bidirectional FIFO

LH543601

TIMING DIAGRAMS (cont'd)

R/W

RWH

RWS

RSS

RSH

BYPASS IN

BYPASS DATA OUT

BYPASS

OUT

BYPASS

PREVIOUS DATA

NOTES:
1. t

RSS

, t

RSH

need not be met unless the rising edge of CK

or CK

occurs while that clock is enabled.

2. Port A is considered the master port for bypass operation. Thus, CK

, R/W

, EN

, and REQ

control

the transmission of data between ports at reset.

- D

35B

- D

35A

RWS

RWH

543601-27

REQ

RQH

RQS

RQH

Figure 9. Data Bypass Timing

LH543601

256

2 Bidirectional FIFO

TIMING DIAGRAMS (cont'd)

DATA

READ FROM

FIFO #2

WRITE TO

FIFO #1

DATA OUT

NOTES:
1. The Port A Parity Error Flag (PF

) reflects the parity status of data present on the data bus.

2. The status of OE

does not gate read or write operations.

3. If OE

is left LOW during a write operation, then the previous data held in the output latch is

written back into FIFO #1.

R/W

- D

35A

RWH

RWS

RWH

RWS

DATA IN

VALID PF

543601-24

RQS

RQH

REQ

RQS

RQH

Figure 10. Port A FIFO Read/Write

256

2 Bidirectional FIFO

LH543601

TIMING DIAGRAMS (cont'd)

R/W

DATA

READ FROM

FIFO #1

WRITE TO

FIFO #2

DATA OUT

DATA IN

VALID PF

NOTES:
1. The Port B Parity Error Flag (PF

) reflects the parity status of data present on the data bus.

2. The status of OE

does not gate read or write operations.

3. If OE

is left LOW during a write operation, then the previous data held in the output latch is

written back into FIFO #2.

- D

35B

RWH

RWS

RWH

RWS

543601-25

REQ

RQH

RQS

RQH

RQS

Figure 11. Port B FIFO Read/Write

LH543601

256

2 Bidirectional FIFO

TIMING DIAGRAMS (cont'd)

R/W

MBF

MAILBOX IN

WRITE TO

MAILBOX #1

READ FROM

MAILBOX #2

MBF

MAXIMUM OF 2 CK

CYCLES LATENCY

MAILBOX OUT

NOTES:
1. Both edges of MBF

are synchronized to the Port A clock, CK

2. Both edges of MBF

are synchronized to the Port B clock, CK

3. There is a maximum of two CK

clock cycles of synchronization latency before MBF

is asserted to indicate valid new mailbox data.
4. The status of mailbox flags does not prevent mailbox read or write operations.

35A

RWH

RWS

RWH

RWS

MBF

543601-22

REQ

RQS

RQH

RQS

RQH

Figure 12. Port A Mailbox Access

256

2 Bidirectional FIFO

LH543601

TIMING DIAGRAMS (cont'd)

MAILBOX IN

WRITE TO

MAILBOX #2

READ FROM

MAILBOX #1

MBF

MAXIMUM OF 2 CK

CYCLES LATENCY

MAILBOX OUT

NOTES:
1. Both edges of MBF

are synchronized to the Port A clock, CK

2. Both edges of MBF

are synchronized to the Port B clock, CK

3. There is a maximum of two CK

clock cycles of synchronization latency before MBF

is asserted to indicate valid new mailbox data.
4. The status of mailbox flags does not prevent mailbox read or write operations.

R/W

MBF

- D

35B

RWH

RWS

RWH

RWS

MBF

543601-23

REQ

RQS

RQH

RQS

RQH

Figure 13. Port B Mailbox Access

LH543601

256

2 Bidirectional FIFO

TIMING DIAGRAMS (cont'd)

R/W

FLAG DATA IN

FLAG DATA OUT

LOAD FLAG

POSITIONS

READ FLAG

POSITIONS

, AE

, AF

NOTES:
1. For valid flag address codes and data formats, see Table 3.
2. If flag status is altered by flag programming, the updated flags will be valid within a time t

RF.

3. The Control Register may be loaded as shown here, with A

, A

= HLL. However, it

is not available for reading back.

- D

35A

RWH

RWS

RWH

RWS

543601-18

REQ

RQS

RQH

RQS

RQH

Figure 14. Flag Programming

256

2 Bidirectional FIFO

LH543601

TIMING DIAGRAMS (cont'd)

543601-1

(EF

)

CK (CK )

EN (EN )

CK (CK )

B A

R/W (R/W )

REQ

(REQ

)

NOTES:
1. A

and A

all are held HIGH for FIFO access at Port A.

is held HIGH for FIFO access at Port B.

2. Parameters without parentheses apply to FIFO #2 operation.
Parameters with parentheses apply to FIFO #1 operation.
3. Assertion of the Empty Flags is controlled by rising clock edges,
whereas deassertion of the Empty Flags is controlled by falling
clock edges.

RWH

RWS

RWH

RWS

RQS

RQH

EN (EN )

RQS

RQH

REQ

(REQ

)

Figure 15. Empty Flag Timing

LH543601

256

2 Bidirectional FIFO

(AE

)

CK (CK )

EN (EN )

CK (CK )

R/W (R/W )

RWH

RWS

RWH

RWS

543601-2

NOTES:
1. A

and A

all are held HIGH for FIFO access at Port A.

is held HIGH for FIFO access at Port B.

2. Parameters without parentheses apply to FIFO #2 operation.
Parameters with parentheses apply to FIFO #1 operation.
3. Assertion of the Almost-Empty Flags is controlled by rising clock
edges, whereas deassertion of the Almost-Empty Flags is controlled
by falling clock edges.

RQH

RQS

REQ (REQ )

EN (EN )

REQ (REQ )

RQH

RQS

Figure 16. Almost-Empty Flag Timing

TIMING DIAGRAMS (cont'd)

256

2 Bidirectional FIFO

LH543601

TIMING DIAGRAMS (cont'd)

(FF

)

CK (CK )

EN (EN )

CK (CK )

R/W (R/W )

EN (EN )

RWH

RWS

RWH

RWS

543601-3

NOTES:
1. A

and A

all are held HIGH for FIFO access at Port A.

is held HIGH for FIFO access at Port B.

2. Parameters without parentheses apply to FIFO #1 operation.
Parameters with parentheses apply to FIFO #2 operation.
3. Assertion of the Full Flags is controlled by rising clock edges,
whereas deassertion of the Full Flags is controlled by falling
clock edges.

RQS

RQH

REQ

(REQ

)

REQ

(REQ

)

RQS

RQH

Figure 17. Full Flag Timing

LH543601

256

2 Bidirectional FIFO

TIMING DIAGRAMS (cont'd)

(AF

)

CK (CK )

EN (EN )

CK (CK )

R/W (R/W )

RWH

RWS

RWH

RWS

543601-4

NOTES:
1. A

and A

all are held HIGH for FIFO access at Port A.

is held HIGH for FIFO access at Port B.

2. Parameters without parentheses apply to FIFO #1 operation.
Parameters with parentheses apply to FIFO #2 operation.
3. Assertion of the Almost-Full Flags is controlled by rising clock edges,
whereas deassertion of the Almost-Full Flags is controlled by falling
clock edges.

RQS

RQH

REQ

(REQ

)

EN (EN )

RQS

RQH

REQ

(REQ

)

Figure 18. Almost-Full Flag Timing

256

2 Bidirectional FIFO

LH543601

TIMING DIAGRAMS (cont'd)

(HF

)

CK (CK )

EN (EN )

CK (CK )

R/W (R/W )

EN (EN )

RWH

RWS

RWH

RWS

543601-5

NOTES:
1. A

and A

all are held HIGH for FIFO access at Port A.

is held HIGH for FIFO access at Port B.

2. Parameters without parentheses apply to FIFO #1 operation.
Parameters with parentheses apply to FIFO #2 operation.
3. Both assertion and deassertion of the Half-Full Flags are controlled
entirely by rising clock edges, rather than by falling clock edges.

RQS

RQH

REQ

(REQ

)

RQS

RQH

REQ

(REQ

)

Figure 19. Half-Full Flag Timing

LH543601

256

2 Bidirectional FIFO

R/W

RSH

RSS

RWS

NOTES:

1. t

RSS

and t

RSH

need not be met unless a rising edge of CK

or CK

occurs while that clock is enabled.

2. t

RSS

is the time needed to deassert RT

before returning to a normal FIFO cycle.

3. t

RSH

is the time needed before asserting RT

after a normal FIFO cycle.

4. Read and write operations to FIFO #2 should be disabled while RT

is being asserted.

543601-20

RQS

RQH

RQS

RQH

RQS

REQ

RQS

RQH

RQS

RQH

RQS

Figure 20. FIFO #2 Retransmit

TIMING DIAGRAMS (cont'd)

256

2 Bidirectional FIFO

LH543601

TIMING DIAGRAMS (cont'd)

R/W

RSS

RSH

RWS

NOTES:

1. t

RSS

and t

RSH

need not be met unless a rising edge of CK

or CK

occurs while that clock is enabled.

2. t

RSS

is the time needed to deassert RT

before returning to a normal FIFO cycle.

3. t

RSH

is the time needed before asserting RT

after a normal FIFO cycle.

4. Read and write operations to FIFO #1 should be disabled while RT

is being asserted.

RSH

543601-21

RQS

RQH

REQ

RQS

RQH

RQS

REQ

RQS

RQH

RQS

RQH

RQS

Figure 21. FIFO #1 Retransmit

LH543601

256

2 Bidirectional FIFO

TIMING DIAGRAMS (cont'd)

R/W

PREVIOUS DATA

FRL

NOTES:
1. A

, A

, and A

are all held HIGH for FIFO access.

2. OE

is held HIGH.

3. OE

is held LOW.

4. t

FRL

(First Read Latency) - The first read following an empty condition

may begin no earlier than t

FRL

after the first write to an empty FIFO,

to ensure that valid read data is retrieved.

- D

35A

- D

35B

RWH

RWS

RWH

RWS

RWH

RWS

RWH

RWS

543601-16

RQS

RQH

REQ

RQS

RQH

RQS

RQH

REQ

RQS

RQH

Figure 22. FIFO #1 Write and Read Operation in

Near-Empty Region

256

2 Bidirectional FIFO

LH543601

TIMING DIAGRAMS (cont'd)

R/W

FRL

NOTES:
1. A

, A

, and A

are all held HIGH for FIFO access.

2. OE

is held HIGH.

3. OE

is held LOW.

4. t

FRL

(First Read Latency) - The first read following an empty condition

may begin no earlier than t

FRL

after the first write to an empty FIFO,

to ensure that valid read data is retrieved.

- D

35B

- D

35A

RWH

RWS

RWH

RWS

RWH

RWS

RWH

RWS

PREVIOUS DATA

543601-17

RQS

RQH

REQ

RQS

RQH

REQ

RQS

RQH

RQS

Figure 23. FIFO #2 Write and Read Operation in

Near-Empty Region

LH543601

256

2 Bidirectional FIFO

TIMING DIAGRAMS (cont'd)

R/W

PREVIOUS DATA

FWL

NOTES:
1. A

and A

all are held HIGH for FIFO access at Port A.

is held HIGH for FIFO access at Port B.

2. OE

is held HIGH.

3. OE

is held LOW.

4. t

FWL

(First Write Latency) - The first write following a full condition

may begin no earlier than t

FWL

after the first read from a full FIFO,

to ensure that valid write data is written.

- D

35A

- D

35B

RWH

RWS

RWH

RWS

RWH

RWS

RWH

RWS

543601-14

RQS

RQH

REQ

RQS

RQH

RQS

RQH

REQ

RQS

RQH

Figure 24. FIFO #1 Read and Write Operation in

Near-Full Region

256

2 Bidirectional FIFO

LH543601

TIMING DIAGRAMS (cont'd)

R/W

NOTES:
1. A

and A

all are held HIGH for FIFO access at Port A.

is held HIGH for FIFO access at Port B.

2. OE

is held HIGH.

3. OE

is held LOW.

4. t

FWL

(First Write Latency) - The first write following a full condition

may begin no earlier than t

FWL

after the first read from a full FIFO,

to ensure that valid write data is written.

- D

35B

- D

35A

PREVIOUS DATA

FWL

RWH

RWS

RWH

RWS

RWH

RWS

RWH

RWS

543601-15

RQS

RQH

REQ

RQS

RQH

RQS

RQH

REQ

RQS

RQH

Figure 25. FIFO #2 Read and Write Operation in

Near-Full Region

LH543601

256

2 Bidirectional FIFO

TIMING DIAGRAMS (cont'd)

R/W

WORD # n+1

WORD # n

NOTES:
1. A

is held HIGH for FIFO access.

2. OE

is held LOW.

3. WS

is held HIGH and WS

is held LOW for double-byte access.

4. Data-access time t

, after the rising edge of CK

, shown for the

first read cycle, applies similarly for all subsequent read cycles.

- D

17B

18B

- D

35B

RWS

WORD # n+2

WORD # n+1

WORD # n

WORD # n+2

BITS

0-17

BITS

18-35

BITS

0-17

BITS

18-35

BITS

0-17

BITS

18-35

BITS

0-17

BITS

18-35

BITS

0-17

BITS

18-35

543601-13

RQS

REQ

Figure 26. Port B Double-Byte FIFO #1 Read Access for

36-to-18 Funneling

256

2 Bidirectional FIFO

LH543601

R/W

WORD # n

WORD # n+1

WORD # n+2

NOTES:
1. A

is held HIGH for FIFO access.

2. OE

is held HIGH.

3. WS

is held HIGH and WS

is held LOW for double-byte access.

4. Data-setup time t

and data-hold time t

, before and after

the rising edge of CK

, shown for the first write cycle, apply

similarly for all subsequent write cycles.

- D

17B

RWS

BITS

0-17

BITS

18-35

BITS

0-17

BITS

18-35

BITS

0-17

BITS

18-35

543601-12

RQS

REQ

Figure 27. Port B Double-Byte FIFO #2 Write Access for

18-to-36 Defunneling

TIMING DIAGRAMS (cont'd)

LH543601

256

2 Bidirectional FIFO

TIMING DIAGRAMS (cont'd)

R/W

BITS

0-8

WORD # n+1

WORD # n

NOTES:
1. A

is held HIGH for FIFO access.

2. OE

is held LOW.

3. WS

and WS

both are held LOW for single-byte access.

4. Data-access time t

, after the rising edge of CK

, shown for the

first read cycle, applies similarly for all subsequent read cycles.

BITS

9-17

BITS

18-26

BITS

27-35

BITS

0-8

BITS

9-17

BITS

18-26

BITS

27-35

BITS

0-8

BITS

9-17

BITS

18-26

BITS

27-35

BITS

0-8

BITS

9-17

BITS

18-26

BITS

27-35

BITS

0-8

BITS

9-17

BITS

18-26

BITS

27-35

27B

- D

35B

18B

- D

26B

- D

17B

- D

RWS

WORD # n+1

WORD # n

WORD # n+1

WORD # n

WORD # n+1

WORD # n

543601-11

RQS

REQ

Figure 28. Port B Single-Byte FIFO #1 Read Access for

36-to-9 Funneling

256

2 Bidirectional FIFO

LH543601

TIMING DIAGRAMS (cont'd)

R/W

BITS

0-8

BITS

9-17

BITS

18-26

BITS

27-35

WORD # n

WORD # n+1

NOTES:
1. A

is held HIGH for FIFO access.

2. OE

is held HIGH.

3. WS

and WS

both are held LOW for single-byte access.

4. Data-setup time t

and data-hold time t

, before and after

the rising edge of CK

, shown for the first write cycle, apply

similarly for all subsequent write cycles.

BITS

0-8

BITS

9-17

- D

RWS

543601-10

RQS

REQ

Figure 29. Port B Single-Byte FIFO #2 Write Access for

9-to-36 Defunneling

LH543601

256

2 Bidirectional FIFO

543601-8

RQS

ACK

(CK )

(R/W )

(REQ )

(ACK )

(AF

)

R/W

REQ

ACK

RWS

Indicates where a write would take place, if ACK were tied to EN.

NOTES:
1. For a FIFO access to occur, REQ and EN must be held HIGH for the required setup and hold times.
2. ACK can be tied directly to EN to directly gate FIFO accesses.

3. REQ must be maintained HIGH throughout the entire clock cycle for ACK to be generated.
4. When the REQ/ACK handshake is not used, ACK can be ignored,
and REQ may be tied HIGH or used as a second enable.
5. Parameters without parentheses apply to Port A. Parameters with parentheses apply to Port B.

Starting at the third cycle after entering the
'almost-full' region, acknowledge
occurs on every third cycle to prevent overrun
of the full condition.

Outside the 'almost-full' region,
acknowledge is continuous
for a continuous request.

Figure 30. Write Request/Acknowledge Handshake

TIMING DIAGRAMS (cont'd)

256

2 Bidirectional FIFO

LH543601

TIMING DIAGRAMS (cont'd)

RQS

ACK

(CK )

(R/W )

(REQ )

(ACK )

(AE

)

R/W

REQ

ACK

RWS

Starting at the third cycle after entering the
'almost-empty' region, acknowledge
occurs on every third cycle to prevent underrun
of the empty condition.

Outside the 'almost-empty' region,
acknowledge is continuous
for a continuous request.

Indicates where a read would take place, if ACK were tied to EN.

NOTES:
1. For a FIFO access to occur, REQ and EN must be held HIGH for the required setup and hold times.
2. ACK can be tied directly to EN to directly gate FIFO accesses.

543601-9

Figure 31. Read Request/Acknowledge Handshake

LH543601

256

2 Bidirectional FIFO

PACKAGE DIAGRAMS

132 PQFP

DIMENSIONS IN MM [INCHES]

MAXIMUM LIMIT

MINIMUM LIMIT

132PQFP (PQFP132-P-S950)

28.02 [1.103]
27.86 [1.097]

0.635
[0.025] TYP
NON-ACCUM

4.57 [0.180]
4.06 [0.160]

0.51 [0.020]
MIN.

24.21 [0.953]
24.05 [0.947]

28.02 [1.103]
27.86 [1.097]

27.69 [1.090]
27.18 [1.070]

SECTION

0.10 [0.004]

0.25 [0.010] TYP.

0.51 [0.020] MIN.

0.15 [0.006]

- 8

CHAMFER

TOP VIEW

24.21 [0.953]
24.05 [0.947]

132-pin PQFP

256

2 Bidirectional FIFO

LH543601

DIMENSIONS IN MM [INCHES]

MAXIMUM LIMIT

MINIMUM LIMIT

144TQFP (TQFP-144-P-2020)

0.50 [0.020]

TYP.

0.20 [0.008]
0.09 [0.004]

20.0 [0.787]

BASIC

144TQFP

1.45 [0.057]
1.35 [0.053]

DETAIL

20.0

[0.787]
BASIC

1.60 [0.063]

REF. MAX

0.15 [0.006]
0.05 [0.002]

22.0

[0.866]
BASIC

0.27 [0.010]
0.17 [0.007]

22.0 [0.866]

BASIC

0.75 [0.030]
0.47 [0.019]

1.00

[0.039]

REF.

144-pin TQFP

LH543601

256

2 Bidirectional FIFO

ORDERING INFORMATION

20
25
30
35

Cycle Times (ns)

M 144-Pin, Thin Quad Flat Package (TQFP144-P-2020)
P 132-Pin, Plastic Quad Flat Package (PQFP132-P-S950)

LH543601

Device Type

Package

- ##

Speed

256 x 36 x 2 Bidirectional FIFO

Example: LH543601P-20 (256 x 36 x 2 Bidirectional FIFO, 20 ns, 132-Lead, Plastic Quad Flat Package)

543601-37

256

2 Bidirectional FIFO

LH543601