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Part Number SK100EL90W

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HIGH-PER.ORMANCE PRODUCTS
1
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Revision 1/May 09, 2002
PRELIMINARY
SK10/100EL90W
Triple ECL to PECL/LVPECL and
LVECL to PECL/LVPECL Translator
Description
.eatures
.unctional Block Diagram
Pin Names
The SK10/100EL90W is a triple ECL to PECL/LVPECL and
LVECL to PECL/LVPECL translator. It is fully compatible
with MC100EL90 and MC100LVEL90. The SK10/
100EL90W provides a V
BB
output for single-ended use
or DC bias for AC coupling to the device. V
BB
is an output
pin and should be used as a bias for the EL90W as its
current source/sink capability is limited. Whenever used,
the V
BB
output pin should be bypassed to V
CC
via a 0.01
µF capacitor.
To accomplish levels of translation, the EL90W requires
three power rails, V
CC
, V
EE
and GND. Please refer to the
Function Table below for more details. V
CC
supply should
be connected to the positive supply, and V
EE
should be
connected to the negative supply.
The GND pins are connected to the system ground plane.
Both V
CC
and V
EE
pins should be bypassed to ground via
a 0.01 µF capacitor. Under open input conditions, the D*
input will be biased at V
EE
/2, and the D input will be pulled
to V
EE
. This condition will force the Q output to low,
ensuring stability.
·
Extended Supply Voltage Range (V
EE
= ­5.5V to
­3.0V and V
CC
= 3.0V to 5.5V)
·
High Bandwidth Output Transition
·
500 ps Propagation Delay
·
V
BB
Output
·
Internal Input Pulldown Resistors
·
New Differential Input Common Mode Range
·
Fully Compatible with MC100EL90 and
MC100LVEL90
·
ESD Protection of >4000V
·
Industrial Temperature Range: ­40
o
C to +85
o
C
·
Available in 20-lead SOIC Package
Function Table
n
i
P
n
o
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t
c
n
u
F
*
n
D
,
n
D
s
t
u
p
n
I
L
C
E
V
L
/
L
C
E
l
a
i
t
n
e
r
e
f
f
i
D
*
n
Q
,
n
Q
s
t
u
p
t
u
O
L
C
E
P
V
L
/
L
C
E
P
l
a
i
t
n
e
r
e
f
f
i
D
V
B
B
t
u
p
t
u
O
e
g
a
t
l
o
V
e
c
n
e
r
e
f
e
R
L
C
E
V
L
/
L
C
E
n
o
i
t
c
n
u
F
E
E
V
C
C
V
L
C
E
P
-
o
t
-
L
C
E
V
L
V
3
.
3
-
V
0
.
5
+
L
C
E
P
V
L
-
o
t
-
L
C
E
V
L
V
3
.
3
-
V
3
.
3
+
L
C
E
P
-
o
t
-
L
C
E
V
0
.
5
-
V
0
.
5
+
L
C
P
E
V
L
-
o
t
-
L
C
E
V
0
.
5
-
V
3
.
3
+
VCC
D0
D1
D1*
VBB
D2
D2*
VEE
D0*
VBB
VCC
Q0
Q1
Q1*
GND
Q2
Q2*
VCC
Q0*
GND
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
ECL
PECL
ECL
PECL
ECL
PECL
2
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HIGH-PER.ORMANCE PRODUCTS
SK10/100EL90W
Revision 1/May 09, 2002
PRELIMINARY
Package Information
PIN Descriptions
20 Pin SOIC Package
e
A
A1
­T
18X
SEATING
PLANE
C
L
h
x 45
°
B
D
H
E
10X
20X
20
11
0.010 (0.25) M
T
A
S
B
S
0.010 (0.25)
M
BM
NOTES:
1.
Dimensions and tolerances per ASME Y14.5M,
1994.
2.
Controlling dimension: millimeters.
3.
Dimensions D and E do not include mold protrusion.
4.
Maximum mold protrusion 0.15 per side.
5.
Dimension B does not include Dambar protrusion.
Allowable Dambar protrusion shall be 0.13 total in
excess of B dimension at maximum material
condition.
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o
7
o
3
www.semtech.com
HIGH-PER.ORMANCE PRODUCTS
SK10/100EL90W
PRELIMINARY
Revision 1/May 09, 2002
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A
m
SK10/100EL90W PECL/LVPECL Output DC Electrical Characteristics (Notes 1, 2)
(V
EE
= ­5.5V to ­3.0V; V
CC
= +3.0V to +5.5V; V
OUT
loaded 50
to V
CC
­ 2.0V)
SK10/100EL90W ECL/LVECL Input DC Electrical Characteristics (Notes 1, 2, 6)
(V
EE
= ­5.5V to ­3.0V; V
CC
= +3.0V to +5.5V ; V
OUT
loaded 50
to V
CC
­ 2.0V)
DC Characteristics
4
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HIGH-PER.ORMANCE PRODUCTS
SK10/100EL90W
Revision 1/May 09, 2002
PRELIMINARY
0
4
-
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AC Characteristics
SK10/100EL90W AC Electrical Characteristics
Notes:
1.
10EL circuits are designed to meet the DC specifications shown in the table after thermal equilibrium has
been established. The circuit is in a test socket or mounted on a printed circuit board and transverse
airflow greater than 500 lfpm is maintained. Outputs are terminated through a 50
resistor to
VCC­2.0V.
2.
100K circuits are designed to meet the DC specification shown in the table where transverse
airflow greater than 500 lfpm is maintained.
3.
Duty cycle skew is the difference between T
PLH
and T
PHL
propagation delay through a device.
4.
Minimum input swing for which parameters guaranteed.
5.
CMR range is referenced to the most positive side of the differential input signal. Normal operation is
obtained if the high level falls within the specified range and the peak-to-peak voltage lies between
VPP
(min)
and 1V. The lower end of the CMR range varies 1:1 with VEE and is equal to VEE + 1.2V.
6.
For standard ECL DC specifications, refer to the ECL Logic Family Standard DC Specifications Data
Sheet.
7.
For part ordering description, see HPP Part Ordering Information Data Sheet.
(V
EE
= ­5.5V to ­3.0V; V
CC
= +3.0V to +5.5V ; V
OUT
loaded 50
to V
CC
­ 2.0V)
5
www.semtech.com
HIGH-PER.ORMANCE PRODUCTS
SK10/100EL90W
PRELIMINARY
Revision 1/May 09, 2002
Ordering Information
e
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D
Division Headquarters
10021 Willow Creek Road
San Diego, CA 92131
Phone: (858) 695-1808
FAX: (858) 695-2633
Marketing Group
1111 Comstock Street
Santa Clara, CA 95054
Phone: (408) 566-8776
FAX: (408) 566-8759
Semtech Corporation
High-Performance Products Division
Contact Information
AN1002 - Interfacing Between ECL / LVECL / PECL / LVPECL - to - TTL / LVTTL / CMOS / LVCMOS
AN1003 - Termination Techniques for ECL / LVECL / PECL / LVPECL Devices
AN1004 - Interfacing Between LVDS and ECL / LVECL / PECL / LVPECL
AN1005 - Using ECL / LVECL Devices as PECL / LVPECL
AN1006 - Designing with 10K and 100K ECL / PECL Devices
Application Notes