SMFDV032

SmartMedia

Document Title

32M x 8 Bit SmartMedia

Card

Revision History

Revision No

0.0

0.1

0.2

0.3

Remark

Preliminary

Final

History

Initial issue( 16MB Dual Chip )

- Compared to SMFV032(32MB Single Chip)

1. Valid block number(Min.)

SMFDV032 : 2013 blocks SMFV032 : 2018 blocks

2. Input/output capacitance & input capacitance(Max.)

SMFDV032 : 30 pF SMFV032 : 70 pF
Changed specifications from 16MB to 32MB

Data Sheet 1999
1) Changed t

Parameter : 7

s(Max.)

2) Changed Nop : Main Array 1 cycle(Max.)

2 cycles(Max.)

3) Added CE don't care mode during the data-loading and reading

1) Changed voltage-density model marking method on SmartMedia

Draft Date

Nov 11th 1998

Jan 14th 1999

April 10th 1999

June 7th 1999

The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the

right to change the specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions about device. If you
have any questions, please contact the SAMSUNG branch office near your office.

ITEM

SMFV016

SMFDV032

Valid Block Number(Min.)

1004 Blocks

2013 Blocks

Sequential Read Mode

Supported only
within a block

Input/output & input
Capacitance

10pF

30pF

Device Code

73H

75H

Program Icc2(mA)

Typ : 10, Max : 20 Typ : 15, Max : 25

Erase Icc3(mA)

Typ : 10, Max : 20 Typ : 15, Max : 25

SMFDV032

SmartMedia

32M x 8 Bit SmartMedia

Card

The SMFDV032 is a 32M(33,554,432)x8bit NAND Flash Mem-

ory with a spare 1,024K(1,048,576)x8bit. Its NAND cell pro-
vides the most cost-effective solution for the solid state mass

storage market. A program operation programs the 528-byte

page in typically 200

s and an erase operation can be per-

formed in typically 2ms on a 16K-byte block. Data in the page

can be read out at 50ns cycle time per byte. The I/O pins serve

as the ports for address and data input/output as well as com-
mand inputs. The on-chip write controller automates all pro-

gram and erase functions including pulse repetition, where

required, and internal verify and margining of data. Even the

write-intensive systems can take advantage of the

SMFDV032

s extended reliability of 1,000,000 program/erase

cycles by providing either ECC(Error Correcting Code) or real
time mapping-out algorithm. These algorithms have been

implemented in many mass storage applications and also the

spare 16 bytes of a page combined with the other 512 bytes

can be utilized by system-level ECC.

The SMFDV032 is an optimum solution for large nonvolatile

storage applications such as solid state file storage, digital
voice recorder, digital still camera and other portable applica-

tions requiring non-volatility.

GENERAL DESCRIPTION

FEATURES

·Single 2.7V~3.6V Supply
·Organization
- Memory Cell Array : (32M + 1,024K)bit x 8bit
- Data Register : (512 + 16)bit x8bit
·Automatic Program and Erase
- Page Program : (512 + 16)Byte
- Block Erase : (16K + 512)Byte
·528-Byte Page Read Operation
- Random Access : 10

s(Max.)

- Serial Page Access : 50ns(Min.)
·Fast Write Cycle Time
- Program time : 200

s(typ.)

- Block Erase time : 2ms(typ.)
·Command/Address/Data Multiplexed I/O port
·Hardware Data Protection
- Program/Erase Lockout During Power Transitions
·Reliable CMOS Floating-Gate Technology
- Endurance : 1M Program/Erase Cycles
- Data Retention : 10 years
·Command Register Operation

·22pad SmartMedia

(SSFDC)

SmartMedia

CARD(SSFDC)

NOTE : Connect all V

and V

pins of each device to common power supply outputs.

Do not leave V

or V

disconnected.

Pin Name

Pin Function

I/O0 ~ I/O7

Data Input/Outputs

CLE

Command Latch Enable

ALE

Address Latch Enable

Chip Enable

Read Enable

Write Enable

Write Protect

GND

Ground

R/B

Ready/Busy output

Power(2.7V~3.6V)

Ground

N.C

No Connection

PIN DESCRIPTION

I/O

GND

R/B

I/O

ALE

CLE

22 PAD SmartMedia

3V 32MB

SMFDV032

SmartMedia

512B column

16 Byte Column

Figure 1. FUNCTIONAL BLOCK DIAGRAM

Figure 2. ARRAY ORGANIZATION

NOTE : Column Address : Starting Address of the Register.

00h Command(Read) : Defines the starting address of the 1st half of the register.

01h Command(Read) : Defines the starting address of the 2nd half of the register.

* A

is initially set to "Low" or "High" by the 00h or 01h Command.

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

1st Cycle

2nd Cycle

3rd Cycle

X-Buffers

Y-Gating

256M + 8M Bit

Command

2nd half Page Register & S/A

NAND Flash

ARRAY

(512 + 16)Byte x 65536

Y-Gating

1st half Page Register & S/A

I/O Buffers & Latches

Latches
& Decoders

Y-Buffers
Latches
& Decoders

Register

Control Logic

& High Voltage

Generator

Global Buffers

Output

Driver

- A

Command

CE
RE
WE

CLE ALE WP

I/0 0

I/0 7

1st half Page Register

(=256 Bytes)

2nd half Page Register

(=256 Bytes)

64K Row
(=2048 Block)

512 Byte

8 bit

16 Byte

1 Block(=32 Row)
(16K + 512) Byte

I/O 0 ~ I/O 7

1 Page = 528 Bytes
1 Block = 528 B x 32 Pages
= (16K + 512) Bytes
1 Device = 528B x 32Pages x 2048 Blocks
= 264 Mbits

Column Address

Row Address

(Page Address)

Page Register

SMFDV032

SmartMedia

PRODUCT INTRODUCTION

The SMFDV032 is a 264Mbit(276,824,064 bit) memory organized as 65,536 rows by 528 columns. Spare sixteen columns are
located from column address of 512 to 527. A 528-byte data register is connected to memory cell arrays accommodating data trans-
fer between the I/O buffers and memory during page read and page program operations. The memory array is made up of 16 cells
that are serially connected to form a NAND structure. Each of the 16 cells resides in a different page. A block consists of the 32
pages formed by two NAND structures, totaling 8448 NAND structures of 16 cells. The array organization is shown in Figure 2. The
program and read operations are executed on a page basis, while the erase operation is executed on a block basis. The memory
array consists of 2048 separately erasable 16K-byte blocks. It indicates that the bit by bit erase operation is prohibited on the
SMFDV032.

The SMFDV032 has addresses multiplexed into 8 I/O's. This scheme dramatically reduces pin counts and allows systems upgrades
to future densities by maintaining consistency in system board design. Command, address and data are all written through I/O's by
bringing WE to low while CE is low. Data is latched on the rising edge of WE. Command Latch Enable(CLE) and Address Latch
Enable(ALE) are used to multiplex command and address respectively, via the I/O pins. All commands require one bus cycle except
for Block Erase command which requires two cycles: one cycle for erase-setup and another for erase-execution after block address
loading. The 32M byte physical space requires 25 addresses, thereby requiring three cycles for byte-level addressing: column
address, low row address and high row address, in that order. Page Read and Page Program need the same three address cycles
following the required command input. In Block Erase operation, however, only the two row address cycles are used. Device opera-
tions are selected by writing specific commands into the command register. Table 1 defines the specific commands of the
SMFDV032.

Table 1. COMMAND SETS

NOTE : 1. The 00H command defines starting address of the 1st half of registers.

The 01H command defines starting address of the 2nd half of registers.

After data access on the 2nd half of register by the 01h command, the status pointer is

automatically moved to the 1st half register(00h) on the next cycle.

Function

1st. Cycle

2nd. Cycle

Acceptable Command during Busy

Sequential Data Input

80h

00h/01h

(1)

50h

Read ID

90h

Reset

FFh

Page Program

10h

Block Erase

60h

D0h

Read Status

70h

SMFDV032

SmartMedia

PIN DESCRIPTION

Command Latch Enable(CLE)

The CLE input controls the path activation for commands sent to the command register. When active high, commands are latched
into the command register through the I/O ports on the rising edge of the WE signal.

Address Latch Enable(ALE)

The ALE input controls the path activation for address and input data to the internal address/data register.
Addresses are latched on the rising edge of WE with ALE high, and input data is latched when ALE is low.

Chip Enable(CE)

The CE input is the device selection control. When CE goes high during a read operation the device is returned to standby mode.
However, when the device is in the busy state during program or erase, CE high is ignored, and does not return the device to
standby mode.

Write Enable(WE)

The WE input controls writes to the I/O port. Commands, address and data are latched on the rising edge of the WE pulse.

Read Enable(RE)

The RE input is the serial data-out control, and when active drives the data onto the I/O bus. Data is valid t

REA

after the falling edge

of RE which also increments the internal column address counter by one.

I/O Port : I/O 0 ~ I/O 7

The I/O pins are used to input command, address and data, and to output data during read operations. The I/O pins float to high-z
when the chip is deselected or when the outputs are disabled.

Write Protect(WP)

The WP pin provides inadvertent write/erase protection during power transitions. The internal high voltage generator is reset when
the WP pin is active low.

Ready/Busy(R/B)

The R/B output indicates the status of the device operation. When low, it indicates that a program, erase or random read operation is
in process and returns to high state upon completion. It is an open drain output and does not float to high-z condition when the chip
is deselected or when outputs are disabled.

Part Number SMFDV032