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Part Number S3x75xx

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S3C7524/C7528/P7528/C7534/C7538/P7538
PRODUCT OVERVIEW
1-1
1
PRODUCT OVERVIEW
The S3C7524/C7528/C7534/C7538 single-chip CMOS microcontroller has been designed for high-performance
using SAM 47 (Samsung Arrangeable Microcontrollers). SAM 47, Samsung's newest 4-bit CPU core is notable
for its low energy consumption and low operating voltage.
You can select from two ROM sizes: 4K or 8K bytes
Except for the difference in ROM size, the features and functions of the S3C7524 and the S3C7528, the
S3C7534 and the S3C7538 are identical.
With it's DTMF generator, watchdog timer function, and versatile 8-bit timer/counters, theS3C7524/C7528
/C5304/C5308 offers an excellent design solution for a wide variety of telecommunication applications.
Up to 35 pins of the available 42-pin SDIP or 44-pin QFP package for the S3C7524/C7528, and up to 23 pins of
the available 30-pin SDIP or 32-pin SOP package for the S3C7534/C7538 can be assign to I/O. Six vectored
interrupts for S3C7524/C7528 and four vectored interrupts for S3C7534/C7538 provide fast response to internal
and external events. In addition, the S3C7524/C7528/C7534/C7538 's advanced CMOS technology provides for
low power consumption and a wide operating voltage range.
OTP
The S3C7524/C7528 microcontroller is also available in OTP (One Time Programmable) version, S3P7528. The
S3C7534/C7538 microcontroller is also available in OTP (One Time Programmable) version, S3P7538. The
S3P7528/P7538 microcontroller has an on-chip 8K-byte one-time-programable EPROM instead of masked ROM.
The S3P7528 is comparable to S3C7524/C7528, both in function and in pin configuration. Also, the S3P7538 is
comparable to the S3C7534/C7538, both in function and in pin configuration.
PRODUCT OVERVIEW
S3C7524/C7528/P7528/C7534/C7538/P7538
1-2
FEATURES SUMMARY
Memory
·
768
×
4-bit RAM
·
4,096
×
8-bit ROM (S3C7524/C7534)
8,192
×
8-bit ROM (S3C7528/C7538)
35 I/O Pins
·
Input only: 4 pins (S3C7524/C7528)
1 pins (S3C7534/C7538)
·
I/O: 23 pins (S3C7524/C7528)
14 pins (S3C7534/C7538)
·
N-channel open-drain I/O: 8 pins
Memory-Mapped I/O Structure
·
Data memory bank 15
DTMF Generator
·
16 dual-tone frequencies for tone dialing
8-Bit Basic Timer
·
Programmable interval timer
·
Watchdog timer
Two 8-Bit Timer/Counters
·
Programmable 8-bit timer
·
External event counter function
·
Arbitrary clock frequency output
Watch Timer
·
Real-time and interval time measurement
·
Four frequency outputs to the BUZ pin
Bit Sequential Carrier
·
Supports 8-bit serial data transfer in arbitrary
format
Interrupts
·
3 external interrupt vectors (S3C7524/C7528)
1 external interrupt vectors (S3C7534/C7538)
·
3 internal interrupt vectors
·
2 quasi-interrupts
Power-Down Modes
·
Idle: Only CPU clock stops
·
Stop: System clock stops
Oscillation Sources
·
Crystal, or ceramic for main system clock
·
Main system clock frequency: 0.4­6.0 MHz
(typical)
·
CPU clock divider circuit (by 4, 8, or 64)
Instruction Execution Times
·
0.95, 1.91, and 15.3
µ
s at 4.19 MHz
·
1.12, 2.23, 17.88
µ
s at 3.58 MHz
·
0.67, 1.33, 10.7
µ
s at 6.0 MHz
Operating Temperature
·
­ 40
°
C to 85
°
C
Operating Voltage Range
·
2.0 V to 5.5 V
Package Types
·
42 SDIP, 44 QFP (S3C7524/C7528)
·
30 SDIP, 32 SOP (S3C7534/C7538)
S3C7524/C7528/P7528/C7534/C7538/P7538
PRODUCT OVERVIEW
1-3
BLOCK DIAGRAM
P6.0­P6.3 /
KS0­KS3
ARITHMETIC
AND
LOGIC UNIT
INTERRUPT
CONTROL
BLOCK
STACK
POINTER
PROGRAM
COUNTER
PROGRAM
STATUS WORD
FLAGS
INSTRUCTION DECODER
CLOCK
RESET
Xin
Xout
INTERNAL
INTERRUPTS
P8.0­P8.3
P5.0­P5.3
P4.0 / BTCO
P4.1
-
P4.3
P7.0­P7.3 /
KS4­KS7
P9.0­P9.2
DTMF
INT0, INT1, INT2, INT4
8-BIT
TIMER/
COUNTER 0
8-BIT
TIMER/
COUNTER 1
I/O PORT 6
I/O PORT 7
P2.0 / TCLO0
P2.1 / TCLO1
P2.2 / CLO
P2.3 / BUZ
P3.0 / TCL0
P3.1 / TCL1
P3.2
P3.3
I/O PORT 4
I/O PORT 5
DTMF
GENERATOR
P1.0 / INT0
P1.1 / INT1
P1.2 / INT2
P1.3 / INT4
INPUT
PORT 1
768 x 4-BIT
DATA
MEMORY
PROGRAM MEMORY
S3C7524/C7534: 4 KBytes
S3C7528/C7538: 8 KBytes
I/O PORT 9
I/O PORT 8
I/O PORT 2
I/O PORT 3
BASIC
TIMER
WATCH
TIMER
WATCH-DOG
TIMER
NOTE: S3C7534/C7538 does not use P1.1/INT1, P1.2/INT2, P1.3/INT3, P3.2, P3.3, INT1, INT2,
INT4, P8.0-P8.3, and P9.0-P9.2.
Figure 1­1. S3C7524/C7528 Simplified Block Diagram
PRODUCT OVERVIEW
S3C7524/C7528/P7528/C7534/C7538/P7538
1-4
PIN ASSIGNMENTS
P1.0 / INT0
P1.1 / INT1
P1.2 / INT2
P1.3 / INT4
P2.0 / TCLO0
P2.1 / TCLO1
P2.2 / CLO
P2.3 / BUZ
P3.0 / TCL0
P3.1 / TCL1
VDD
VSS
XOUT
XIN
TEST
P4.0 / BTCO
P4.1
RESET
P3.2
P3.3
P4.2
P9.2
P9.1
P9.0
DTMF
P7.3 / KS7
P7.2 / KS6
P7.1 / KS5
P7.0 / KS4
P6.3 / KS3
P6.2 / KS2
P6.1 / KS1
P6.0 / KS0
P5.3
P5.2
P5.1
P5.0
P8.3
P8.2
P8.1
P8.0
P4.3
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
S3C7524/C7528
(42-SDIP-600)
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
Figure 1­2. S3C7524/C7528 Pin Assignment Diagrams (42­SDIP)
S3C7524/C7528/P7528/C7534/C7538/P7538
PRODUCT OVERVIEW
1-5
RESET
P3.2
P3.3
P4.2
NC
P4.3
P8.0
P8.1
P8.2
P8.3
P5.0
1
2
3
4
5
6
7
8
9
10
11
P7.3 / KS7
P7.2 / KS6
P7.1 / KS5
P7.0 / KS4
P6.3 / KS3
P6.2 / KS2
P6.1 / KS1
P6.0 / KS0
P5.3
P5.2
P5.1
P2.2 / CLO
P2.3 / BUZ
P3.0 / TCL0
P3.1 / TCL1
VDD
VSS
XOUT
XIN
TEST
P4.0 / BTCO
P4.1
KS57C5204/C5208
(44-QFP-1010B)
12
1
3
1
4
1
5
1
6
1
7
1
8
1
9
20
21
22
33
32
31
30
29
28
27
26
25
24
23
4
4
43
42
41
40
3
9
38
37
36
35
34
P2.1 / TCLO1
P2.0 / TCLO0
P1.3 / INT4
P1.2 / INT2
P1.1 / INT1
P1.0 / INT0
NC
P9.2
P9.1
P9.0
DTMF
Figure 1­3. S3C7524/C7528 Pin Assignment Diagrams (44­QFP)
PRODUCT OVERVIEW
S3C7524/C7528/P7528/C7534/C7538/P7538
1-6
VSS
XOUT
XIN
TEST
P4.0 / BTCO
P4.1
RESET
P4.2
P4.3
P5.0
P5.1
P5.2
P5.3
P6.0 / KS0
P6.1 / KS1
VDD
P3.1 / TCL1
P3.0 / TCL0
P2.3 / BUZ
P2.2 / CLO
P2.1 / TCLO1
P2.0 / TCLO0
P1.0 / INT0
DTMF
P7.3 / KS7
P7.2 / KS6
P7.1 / KS5
P7.0 / KS4
P6.3 / KS3
P6.2 / KS2
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
(30-SDIP-400)
S3C7534/C7538
Figure 1­4. S3C7534/C7538 Pin Assignment Diagrams (30­SDIP)
VSS
XOUT
XIN
TEST
P4.0 / BTCO
P4.1
RESET
P4.2
NC
P4.3
P5.0
P5.1
P5.2
P5.3
P6.0 / KS0
P6.1 / KS1
VDD
P3.1 / TCL1
P3.0 / TCL0
P2.3 / BUZ
P2.2 / CLO
P2.1 / TCLO1
P2.0 / TCLO0
P1.0 / INT0
NC
DTMF
P7.3 / KS7
P7.2 / KS6
P7.1 / KS5
P7.0 / KS4
P6.3 / KS3
P6.2 / KS2
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
(32-SOP-405A)
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
S3C7534/C7538
Figure 1­5. S3C7534/C7538 Pin Assignment Diagrams (32­SOP)
S3C7524/C7528/P7528/C7534/C7538/P7538
PRODUCT OVERVIEW
1-7
PIN DESCRIPTIONS
Table 1-1. S3C7524/C7528 Pin Descriptions
Pin
Name
Pin
Type
Reset
Value
Description
Pin
Number
Share
Pin
Circuit
Type
P1.0
P1.1
P1.2
P1.3
I
I
4-bit input port.
1-bit and 4-bit read and test is possible.
Each pull-up resistors are assignable by software.
1 (39)
2 (40)
3 (41)
4 (42)
INT0
INT1
INT2
INT4
A-4
P2.0
P2.1
P2.2
P2.3
I/O
I
4-bit I/O port.
1-bit and 4-bit read/write and test is possible.
Individual pins are software configurable as input or
output.
5 (43)
6 (44)
7 (1)
8 (2)
TCLO0
TCLO1
CLO
BUZ
D-2
P3.0
P3.1
P3.2
P3.3
4-bit pull-up resistors are software assignable to input
pins and are automatically disabled for output pins.
Ports 2 and 3 can be paired to enable 8-bit data
transfer.
9 (3)
10 (4)
19 (13)
20 (14)
TCL0
TCL1
D-4
P4.0
P4.1
P4.2
P4.3
P5.0­P5.3
I/O
I
4-bit I/O ports.
1-bit and 4-bit read/write and test is possible.
Individual pins are software configurable as input or
output.
4-bit pull-up resistors are software assignable to input
pins and are automatically disabled for output pins.
N-channel open-drain or push-pull output can be
selected by software (1-bit unit)
Ports 4 and 5 can be paired to support 8-bit data
transfer.
16 (10)
17 (11)
21 (15)
22 (17)
27­30
(22­25)
BTCO
E-2
P6.0­P6.3
P7.0­P7.3
I/O
I
4-bit I/O ports.
1-bit or 4-bit read/write and test is possible.
Individual pins are software configurable as input or
output.
4-bit pull-up resistors are software assignable to input
pins and are automatically disabled for output pins.
Ports 6 and 7 can be paired to enable 8-bit data
transfer.
31­34
(26­29)
35­38
(30­33)
KS0­KS3
KS4­KS7
D-4
P8.0­P8.3
P9.0­P9.2
I/O
I
4-bit I/O port.
1-bit or 4-bit read/write and test is possible.
Individual pins are software configurable as input or
output.
4-bit pull-up resistors are software assignable to input
pins and are automatically disabled for output pins.
Ports 8 and 9 can be paired to enable 8-bit data
transfer.
23­26
(18­21)
40­42
(35­37)
­
D-2
PRODUCT OVERVIEW
S3C7524/C7528/P7528/C7534/C7538/P7538
1-8
Table 1-1. S3C7524/C7528 Pin Descriptions (Continued)
Pin
Name
Pin
Type
Reset
Value
Description
Pin
Number
Share
Pin
Circuit
Type
DTMF
O
­
DTMF output.
39 (34)
­
G-6
BTCO
I/O
I
Basic timer clock output
16 (10)
P4.0
E-2
INT0
INT1
I
I
External interrupts. The triggering edge for INT0 and
INT1 is selectable.
1 (39)
2 (40)
P1.0
P1.1
A-3
INT2
I
I
Quasi-interrupt with detection of rising edges
3 (41)
P1.2
A-3
INT4
I
I
External interrupt with detection of rising and falling
edges.
4 (42)
P1.3
A-3
TCLO0
I/O
I
Timer/counter 0 clock output
5 (43)
P2.0
D-2
TCLO1
I/O
I
Timer/counter 1 clock output
6 (44)
P2.1
D-2
CLO
I/O
I
Clock output
7 (1)
P2.2
D-2
BUZ
I/O
I
2 kHz, 4 kHz, 8 kHz, or 16 kHz frequency output at
the watch timer clock frequency of 4.19 MHz for
buzzer sound
8 (2)
P2.3
D-2
TCL0
I/O
I
External clock input for timer/counter 0
9 (3)
P3.0
D-4
TCL1
I/O
I
External clock input for timer/counter 1
10 (4)
P3.1
D-4
KS0­KS3
KS4­KS7
I/O
I
Quasi-interrupt inputs with falling edge detection
31­34
(26­29)
35­38
(30­33)
P6.0­
P6.3
P7.0­
P7.3
D-4
V
DD
­
­
Power supply
11 (5)
­
­
V
SS
­
­
Ground
12 (6)
­
­
RESET
­
­
RESET
signal
18 (12)
­
B
X
in
X
out
­
­
Crystal, or ceramic oscillator signal for main system
clock. (For external clock input, use X
in
and input
X
in
's reverse phase to X
out
)
14 (8)
13 (7)
­
­
TEST
­
­
Test signal input
15 (9)
­
­
NC
­
­
No connection
(16, 38)
­
­
NOTE: Parentheses indicate pin number for 44 QFP package.
S3C7524/C7528/P7528/C7534/C7538/P7538
PRODUCT OVERVIEW
1-9
Table 1-2. S3C7534/C7538 Pin Descriptions
Pin
Name
Pin
Type
Description
Pin
Number
Share
Pin
Circuit
Type
P1.0
I
1-bit input port.
1-bit and 4-bit read and test is possible.
Each bit pull-up resistors are assignable.
23 (25)
INT0
A-4
P2.0
P2.1
P2.2
P2.3
I/O
4-bit I/O port.
1-bit and 4-bit read/write and test is possible.
Each individual pin can be assignable as input or
output. 4-bit pull-up resisters are software
assignable to input pins and are automatically
disabled for output pins.
24 (26)
25 (27)
26 (28)
27 (29)
TCLO0
TCLO1
CLO
BUZ
D-2
P3.0
P3.1
Ports 2 and 3 can be paired to enable 8-bit data
transfer.
28 (30)
29 (31)
TCL0
TCL1
D-4
P4.0
P4.1
P4.2
P4.3
P5.0­P5.3
I/O
4-bit I/O ports.
1-bit and 4-bit read/write and test is possible.
Each individual pin can be assignable as input or
output. 4-bit pull-up resisters are software
assignable to input pins and are automatically
disabled for output pins.
The N-channel open-drain or push-pull output
can be selected by software (1-bit unit).
Ports 4 and 5 can be paired to enable 8-bit data
transfer.
5 (5)
6 (6)
8 (8)
9 (10)
10­13
(11­14)
BTCO
E-2
P6.0­P6.3
P7.0­P7.3
I/O
4-bit I/O ports.
1-bit and 4-bit read/write and test is possible.
Each individual pin can be assignable as input or
output. 4-bit pull-up resisters are software
assignable to input pins and are automatically
disabled for output pins.
Ports 6 and 7 can be paired to enable 8-bit data
transfer.
14­17
(15­18)
18­21
(19­22)
KS0­KS3
KS4­KS7
D-4
PRODUCT OVERVIEW
S3C7524/C7528/P7528/C7534/C7538/P7538
1-10
Table 1-1. S3C7534/C7538 Pin Descriptions (Continued)
Pin
Name
I/O
Type
Description
Pin
Number
Share
Pin
Circuit
Type
DTMF
O
DTMF output.
22 (23)
­
G-6
INT0
I
External interrupt input.
The triggering edge for INT0 is selectable.
23 (25)
P1.0
A-3
TCLO0
I/O
Timer/counter 0 clock output
24 (26)
P2.0
D-2
TCLO1
I/O
Timer/counter 1 clock output
25 (27)
P2.1
D-2
CLO
I/O
Clock output
26 (28)
P2.2
D-2
BUZ
I/O
2 kHz, 4 kHz, 8 kHz, or 16 kHz frequency output at the
watch timer clock frequency of 4.19 MHz for buzzer
sound
27 (29)
P2.3
D-2
TCL0
I/O
External clock input for timer/counter 0
28 (30)
P3.0
D-4
TCL1
I/O
External clock input for timer/counter 1
29 (31)
P3.1
D-4
BTCO
I/O
Basic timer clock output
5 (5)
P4.0
E-2
V
DD
­
Power supply
30 (32)
­
­
V
SS
­
Ground
1 (1)
­
­
X
in
X
out
­
Crystal, or ceramic oscillator signal for main system
clock. (For external clock input, use X
in
and input X
in
's
reverse phase to X
out
)
3 (3)
2 (2)
­
­
NC
­
No connection
(9, 24)
­
­
TEST
­
Test signal input
4 (4)
­
­
RESET
­
RESET
signal
7 (7)
­
B
KS0­KS3
KS4­KS7
I/O
Quasi-interrupt inputs with falling edge detection
14­17
(15­18)
18­21
(19­22)
P6.0­
P6.3
P7.0­
P7.3
D-4
NOTE: Parentheses indicate the pin number for 32-SOP package.
S3C7524/C7528/P7528/C7534/C7538/P7538
PRODUCT OVERVIEW
1-11
PIN CIRCUIT DIAGRAMS
V
DD
P
-
CHANNEL
IN
N
-
CHANNEL
Figure 1­6. Pin Circuit Type A
SCHMITT TRIGGER
V
DD
PULL-UP
RESISTOR
IN
Figure 1­7. Pin Circuit Type B
P
-
CHANNEL
RESISTOR
ENABLE
VDD
PULL-UP
RESISTOR
SCHMITT TRIGGER
IN
Figure 1­8. Pin Circuit Type A-4
DATA
OUTPUT
DISABLE
OUT
VDD
P
-
CHANNEL
N
-
CHANNEL
Figure 1­9. Pin Circuit Type C
PRODUCT OVERVIEW
KS57C5204/C5208/P5208/C5304/C5308/P5308 MICROCONTROLLER
1-12
P-CHANNEL
PULL-UP
RESISTOR
RESISTOR
ENABLE
DATA
OUTPUT
DISABLE
I/O
VDD
CIRCUIT
TYPE C
Figure 1­10. Pin Circuit Type D-2
P-CHANNEL
PULL-UP
RESISTOR
RESISTOR
ENABLE
DATA
OUTPUT
DISABLE
SCHMITT TRIGER
I/O
VDD
CIRCUIT
TYPE C
Figure 1­11. Pin Circuit Type D-4
DATA
OUTPUT
DISABLE
VDD
P-CHANNEL
PULL-UP
RESISTOR
ENABLE
N-CHANNEL
PNE
VDD
PULL-UP
RESISTOR
I/O
Figure 1­12. Pin Circuit Type E-2
OUTPUT
DISABLE
DTMF OUT
Figure 1­13. Pin Circuit Type G-6
S3C7524/C7528/P7528/C7534/C7538/P7538
ELECTRICAL DATA
13­1
13
ELECTRICAL DATA
In this section, information on S3C7524/C7528 electrical characteristics is presented as tables and graphics. The
information is arranged in the following order:
Standard Electrical Characteristics
-- Absolute maximum ratings
-- D.C. electrical characteristics
-- System clock oscillator characteristics
-- I/O capacitance
-- A.C. electrical characteristics
-- Operating voltage range
Miscellaneous Timing Waveforms
-- A.C timing measurement point
-- Clock timing measurement at X
in
and X
out
-- TCL timing
-- Input timing for
RESET
-- Input timing for external interrupts
-- Serial data transfer timing
Stop Mode Characteristics and Timing Waveforms
-- RAM data retention supply voltage in stop mode
-- Stop mode release timing when initiated by
RESET
-- Stop mode release timing when initiated by an interrupt request
ELECTRICAL DATA
S3C7524/C7528/P7528/C7534/C7538/P7538
13­2
Table 13-1. Absolute Maximum Ratings
(T
A
= 25
°
C)
Parameter
Symbol
Conditions
Rating
Units
Supply Voltage
V
DD
­
­ 0.3 to + 6.5
V
Input Voltage
V
I1
All I/O ports
­ 0.3 to V
DD
+ 0.3
V
Output Voltage
V
O
­
­ 0.3 to V
DD
+ 0.3
V
Output Current High
I
OH
One I/O port active
­ 15
mA
All I/O ports active
­ 35
Output Current Low
I
OL
One I/O port active
+ 30 (Peak value)
mA
+ 15
(note)
All I/O ports active
+ 100 (Peak value)
+ 60
(note)
Operating Temperature
T
A
­
­ 40 to + 85
°
C
Storage Temperature
T
stg
­
­ 65 to + 150
°
C
NOTE: The values for output current low ( I
OL
) are calculated as peak value
×
Duty .
Table 13-2. D.C. Electrical Characteristics
(T
A
= ­ 40
°
C to + 85
°
C, V
DD
= 2.0 V to 5.5 V)
Parameter
Symbol
Conditions
Min
Typ
Max
Units
Input high
voltage
V
IH1
All input pins except those
specified below for V
IH2
­ V
IH3
0.7 V
DD
­
V
DD
V
V
IH2
Ports 1, 3, 6, 7, and
RESET
0.8 V
DD
V
DD
V
IH3
X
in
and X
out
V
DD
­ 0.1
V
DD
Input low
voltage
V
IL1
All input pins except those
specified below for V
IL2
­V
IL3
­
­
0.3 V
DD
V
V
IL2
Ports 1, 3, 6, 7, and
RESET
0.2 V
DD
V
IL3
X
in
and X
out
0.1
S3C7524/C7528/P7528/C7534/C7538/P7538
ELECTRICAL DATA
13­3
Table 13-2. D.C. Electrical Characteristics (Continued)
(T
A
= ­ 40
°
C to + 85
°
C, V
DD
= 2.0 V to 5.5 V)
Parameter
Symbol
Conditions
Min
Typ
Max
Units
Output high
voltage
V
OH
I
OH
= ­ 1 mA
Ports except 1
V
DD
­ 1.0
­
­
V
Output low
voltage
V
OL1
V
DD
= 4.5 V to 5.5 V
I
OL
= 15 mA, Ports 4 and 5 only
­
0.4
2
V
V
DD
= 2.0 to 5.5 V, I
OL
= 1.6mA
­
­
0.4
V
OL2
V
DD
= 4.5 V to 5.5 V
I
OL
= 4 mA, all out ports except 4,5
­
­
2
V
V
DD
= 2.0 to 5.5 V, I
OL
= 1.6mA
­
­
0.4
Input high
leakage current
I
LIH1
V
I
= V
DD
All input pins except those specified
below
­
­
3
µA
I
LIH2
V
I
= V
DD
X
in
and X
out
20
Input low
leakage current
I
LIL1
V
I
= 0
V
All input pins except below and
RESET
­
­
­ 3
µA
I
LIL2
V
I
= 0 V
X
i
n
and X
out
only
­ 20
Output high
leakage current
I
LOH
V
O
= V
DD
All out pins
­
­
3
µA
Output low
leakage current
I
LOL
V
O
= 0 V
X
in
and X
out
only
­
­
­ 3
µA
Pull-up resistor
R
L1
V
DD
= 5 V; V
I
= 0 V
except
RESET
25
47
100
k
V
DD
= 3 V
50
95
200
R
L2
V
DD
= 5 V; V
I
= 0 V;
RESET
100
220
400
V
DD
= 3 V
200
450
800
ELECTRICAL DATA
S3C7524/C7528/P7528/C7534/C7538/P7538
13­4
Table 13-2. D.C. Electrical Characteristics (Concluded)
(T
A
= ­ 40
°
C to + 85
°
C, V
DD
= 2.0 V to 5.5 V)
Parameter
Symbol
Conditions
Min
Typ
Max
Units
Supply
current
(1)
I
DD1
(DTMF on)
Run mode; V
DD
= 5 V
±
10%
(2)
3.58 MHz crystal oscillator,
C1 = C2 = 22 pF
­
2.9
5.0
mA
V
DD
= 3 V ± 10%
1.6
3.0
I
DD2
Run mode; V
DD
= 5 V
±
10%
6.0 MHz
­
2.6
8.0
mA
(DTMF off)
crystal oscillator, C1 = C2 = 22 pF
3.58 MHz
1.8
4.0
V
DD
= 3 V ± 10%
6.0 MHz
1.8
4.0
3.58 MHz
1.2
2.3
I
DD
3
Idle mode; = V
DD
= 5 V
±
10%
6.0 MHz
­
0.7
2.5
mA
crystal oscillator, C1 = C2 = 22 pF
3.58 MHz
0.6
1.8
V
DD
= 3 V ± 10%
6.0 MHz
0.3
1.5
3.58 MHz
0.2
1.0
I
DD4
Stop mode; V
DD
= 5 V ± 10%
­
0.01
3
µA
Stop mode; V
DD
= 3 V ± 10%
0.01
2
Row tone level
V
ROW
V
DD
= 5 V ± 10%
V
DD
= 3 V ± 10%
V
DD
= 2 V
RL = 5k
­ 16.0 ­ 14.0 ­ 11.0
dBV
Ratio of column
to row tone
dB
CR
V
DD
= 5 V ± 10%
V
DD
= 3 V ± 10%
V
DD
= 2 V
RL = 5k
1
2
3
Distortion
(Dual tone)
THD
V
DD
= 5 V ± 10%
V
DD
= 3 V ± 10%
V
DD
= 2 V
RL = 5k
, 1MHz band
­
­
5
%
NOTES
1.
D.C. electrical values for Supply Current (I
DD1
to I
DD3
) do not include current drawn through internal pull-up registers.
2.
For D.C. electrical values, the power control register (PCON) must be set to 0011B.
S3C7524/C7528/P7528/C7534/C7538/P7538
ELECTRICAL DATA
13­5
Table 13-3. Main System Clock Oscillator Characteristics
(T
A
= ­ 40
°
C + 85
°
C, V
DD
= 2.0 V to 5.5 V)
Oscillator
Clock
Configuration
Parameter
Test Condition
Min
Typ
Max
Units
Ceramic
Oscillator
Xin
Xout
C1
C2
Oscillation frequency
(1)
V
DD
= 2.7 V to 5.5 V
0.4
­
6.0
MHz
V
DD
= 2.0 V to 5.5 V
0.4
­
4.2
Stabilization time
(2)
V
DD
= 3 V
­
­
4
ms
Crystal
Oscillator
Xin
Xout
C1
C2
Oscillation frequency
(1)
V
DD
= 2.7 V to 5.5 V
0.4
­
6.0
MHz
V
DD
= 2.0 V to 5.5 V
0.4
­
4.2
Stabilization time
(2)
V
DD
= 3 V
­
­
10
ms
External
Clock
Xin
Xout
X
in
input frequency
(1)
V
DD
= 2.7 V to 5.5 V
0.4
­
6.0
MHz
V
DD
= 2.0 V to 5.5V
0.4
­
4.2
X
in
input high and low
level width (t
XH
, t
XL
)
­
83.3
­
1250
ns
NOTES
1.
Oscillation frequency and X
in
input frequency data are for oscillator characteristics only.
2.
Stabilization time is the interval required for oscillating stabilization after a power-on occurs, or when stop mode is
terminated.
ELECTRICAL DATA
S3C7524/C7528/P7528/C7534/C7538/P7538
13­6
Table 13-4. Input/Output Capacitance
(T
A
= 25
°
C, V
DD
=
0 V )
Parameter
Symbol
Condition
Min
Typ
Max
Units
Input
Capacitance
C
IN
f = 1 MHz; Unmeasured pins
are returned to V
SS
­
­
15
pF
Output
Capacitance
C
OUT
­
­
15
pF
I/O Capacitance
C
IO
­
­
15
pF
Table 13-5. A.C. Electrical Characteristics
(T
A
= ­ 40
°
C to + 85
°
C, V
DD
= 2.0 V to 5.5 V)
Parameter
Symbol
Conditions
Min
Typ
Max
Units
Instruction Cycle
Time
(1)
t
CY
V
DD
= 2.7 V to 5.5 V
0.67
­
64
µs
V
DD
= 2.0 V to 5.5 V
0.95
TCL0, TCL1 Input
Frequency
f
TI0
,
f
TI1
V
DD
= 2.7 V to 5.5 V
0
­
1.5
MHz
V
DD
= 2.0 V to 5.5V
1
MHz
TCL0, TCL1 Input
High, Low Width
t
TIH0
,
t
TIL0
t
TIH1
,
t
TIL1
V
DD
= 2.7 V to 5.5 V
0.48
­
­
µs
V
DD
= 2.0 V to 5.5 V
1.8
Interrupt Input
High, Low Width
t
INTH
, t
INTL
INT0, INT1, INT2, INT4,
KS0­KS7
10
­
­
µs
RESET
Input Low
Width
t
RSL
Input
10
­
­
µs
S3C7524/C7528/P7528/C7534/C7538/P7538
ELECTRICAL DATA
13­7
CPU CLOCK = oscillator frequency x 1/n (n = 4, 8, 64)
SUPPLY VOLTAGE (V)
1.05 MHz
1.5 MHz
15.625 kHz
CPU CLOCK
1
2
3
4
5
6
7
6 MHz
4.2 MHz
2.7 V
Main Osc. Freq.
Figure 13-1. Standard Operating Voltage Range
Table 13-6. RAM Data Retention Supply Voltage in Stop Mode
(T
A
= ­ 40
°
C to + 85
°
C)
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
Data retention supply voltage
V
DDDR
­
1.5
­
5.5
V
Data retention supply current
I
DDDR
V
DDDR
= 1.5 V
­
0.1
10
µA
Release signal set time
t
SREL
­
0
­
­
µs
Oscillator stabilization wait
time
(1)
t
WAIT
Released by
RESET
Released by interrupt
­
2
17
/fx
(2)
­
ms
ms
NOTES
1.
During oscillator stabilization wait time, all CPU operations must be stopped to avoid instability during oscillator start-up.
2.
Use the basic timer mode register (BMOD) interval timer to delay execution of CPU instructions during the wait time.
ELECTRICAL DATA
S3C7524/C7528/P7528/C7534/C7538/P7538
13­8
TIMING WAVEFORMS
t
SREL
t
WAIT
V
DD
RESET
EXECUTION OF
STOP INSTRUCTION
V
DDDR
DATA RETENTION MODE
STOP MODE
INTERNAL RESET
OPERATION
IDLE MODE
OPERATING
MODE
Figure 13-2. Stop Mode Release Timing When Initiated By
RESET
RESET
V
DD
EXECUTION OF
STOP INSTRUCTION
V
DDDR
DATA RETENTION MODE
STOP MODE
t
WAIT
t
SREL
IDLE MODE
NORMAL
OPERATING
MODE
POWER-DOWN MODE TERMINATING SIGNAL
(INTERRUPT REQUEST)
Figure 13-3. Stop Mode Release Timing When Initiated By Interrupt Request
S3C7524/C7528/P7528/C7534/C7538/P7538
ELECTRICAL DATA
13­9
Timing Waveforms (continued)
0.8
V
DD
0.2
V
DD
0.8
V
DD
0.2
V
DD
MEASUREMENT
POINTS
Figure 13-4. A.C. Timing Measurement Points (Except for X
in
)
Xin
t
XL
t
XH
1 / f x
V
DD
-
0.1 V
0.1 V
Figure 13-5. Clock Timing Measurement at X
in
TCL
t
TIL
t
TIH
1 / f TI
0.8 V
DD
0.2 V
DD
Figure 13-6. TCL Timing
ELECTRICAL DATA
S3C7524/C7528/P7528/C7534/C7538/P7538
13­10
t
RSL
RESET
0.2
V
DD
Figure 13-7. Input Timing for
RESET
RESET
Signal
INT0, 1, 2, 4
K0 to K7
t
INTL
tINTH
0.8 VDD
0.2 VDD
Figure 13-8. Input Timing for External Interrupts and Quasi-Interrupts
S3C7524/C7528/P7528/C7534/C7538/P7538
MECHANICAL DATA
14­1
14
MECHANICAL DATA
This section contains the following information about the device package:
-- Package dimensions in millimeters
-- Pad diagram
-- Pad/pin coordinate data table
NOTE: Dimensions are in millimeters.
39.50 MAX
39.10
± 0.20
0.50 ±
0.10
1.78
(1.77)
0.51 MIN
3.30
± 0.30
3.50
±
0.20
5.08 MAX
42-SDIP-600
0-15
1.00 ±
0.10
0.25
+ 0.10- 0.05
15.24
14.00
±
0
.20
#42
#22
#21
#1
Figure 14-1. 42-SDIP-600 Package Dimensions
MECHANICAL DATA
S3C7524/C7528/P7528/C7534/C7538/P7538
14­2
44-QFP-1010B
#44
NOTE: Dimensions are in millimeters.
10.00
± 0.20
13.20
± 0.30
10.00
± 0.20
13.20
± 0.30
#1
0.35
+ 0.10
- 0.05
0.80
0.10 MAX
0.80 ± 0.20
0.05 MIN
2.05
± 0.10
2.30 MAX
0.15
+ 0.10
- 0.05
0-8
0.15 MAX
(1.00)
Figure 14-2. 44-QFP-1010B Package Dimensions
S3C7524/C7528/P7528/C7534/C7538/P7538
MECHANICAL DATA
14­3
NOTE: Dimensions are in millimeters.
27.88 MAX
27.48
± 0.20
(1.30)
30-SDIP-400
8.94
±
0
.20
#30
#1
0.56 ±
0.10
1.12 ±
0.10
3.81
±
0.20
5.21 MAX
1.778
0.51 MIN
3.30
± 0.30
#16
#15
0-15
0.25
+ 0.10- 0.05
10.16
Figure 14-3. 30-SDIP-400 Package Dimensions
MECHANICAL DATA
S3C7524/C7528/P7528/C7534/C7538/P7538
14­4
32-SOP-450A
20.30 MAX
19.90
± 0.20
#17
#16
0-8
0.25
+ 0.10
- 0.05
11.43
8.34
±
0.20
0.90
±
0.20
0.05 MIN
2.00
±
0.10
2.20 MAX
0.10 MAX
1.27
NOTE: Dimensions are in millimeters.
12.00
±
0
.30
#32
#1
(0.43)
0.40
± 0.10
Figure 14-4. 32-SOP-450A Package Dimensions
S3C7524/C7528/P7528/C7534/C7538/P7538
S3P7528/P7538 OTP
15­1
15
S3P7528/P7538 OTP
OVERVIEW
The S3P7528/P7538 single-chip CMOS microcontroller is the OTP (One Time Programmable)
version of the
S3C7524/C7528/C7534/C7538 microcontroller. It has an on-chip EPROM instead of masked ROM. The EPROM
is accessed by a serial data format.
The S3P7528/P7538 is fully compatible with the S3C7528/C7538, both in function and in pin configuration.
Because of its simple programming requirements, the S3P7528/P7538 is ideal for use as an evaluation chip for
the S3C7528/C7538.
P1.0 / INT0
P1.1 / INT1
P1.2 / INT2
P1.3 / INT4
P2.0 / TCLO0
P2.1 / TCLO1
P2.2 / CLO
P2.3 / BUZ
SDAT / P3.0 / TCL0
SCLK / P3.1 / TCL1
VDD / VDD
VSS / VSS
XOUT
XIN
VPP / TEST
P4.0 / BTCO
P4.1
RESET
RESET / RESET
P3.2
P3.3
P4.2
P9.2
P9.1
P9.0
DTMF
P7.3 / KS7
P7.2 / KS6
P7.1 / KS5
P7.0 / KS4
P6.3 / KS3
P6.2 / KS2
P6.1 / KS1
P6.0 / KS0
P5.3
P5.2
P5.1
P5.0
P8.3
P8.2
P8.1
P8.0
P4.3
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
NOTE: The bold words indicate OTP pin names.
S3P7528
(42-SDIP-600)
Figure 15-1. S3P7528 Pin Assignments (42-SDIP)
S3P7528/P7538 OTP
S3C7524/C7528/P7528/C7534/C7538/P7538
15­2
VSS / V SS
XOUT
XIN
VPP / TEST
P4.0 / BTCO
P4.1
RESET
RESET / RESET
P4.2
NC
P4.3
P5.0
P5.1
P5.2
P5.3
P6.0 / KS0
P6.1 / KS1
VDD / VDD
P3.1 / TCL1 / SCLK
P3.0 / TCL0 / SDAT
P2.3 / BUZ
P2.2 / CLO
P2.1 / TCLO1
P2.0 / TCLO0
P1.0 / INT0
NC
DTMF
P7.3 / KS7
P7.2 / KS6
P7.1 / KS5
P7.0 / KS4
P6.3 / KS3
P6.2 / KS2
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
(32-SOP-405A)
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
KS57P5308
Figure 15-2. S3P7528 Pin Assignments (44-QFP)
S3C7524/C7528/P7528/C7534/C7538/P7538
S3P7528/P7538 OTP
15­3
VSS / VSS
XOUT
XIN
VPP / TEST
P4.0 / BTCO
P4.1
RESET
RESET / RESET
P4.2
P4.3
P5.0
P5.1
P5.2
P5.3
P6.0 / KS0
P6.1 / KS1
VDD / VDD
P3.1 / TCL1 / SCLK
P3.0 / TCL0 / SDAT
P2.3 / BUZ
P2.2 / CLO
P2.1 / TCLO1
P2.0 / TCLO0
P1.0 / INT0
DTMF
P7.3 / KS7
P7.2 / KS6
P7.1 / KS5
P7.0 / KS4
P6.3 / KS3
P6.2 / KS2
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
(30-SDIP-400)
S3C7538
Figure 15-3. S3P7538 Pin Assignments (30-SDIP)
S3P7528/P7538 OTP
S3C7524/C7528/P7528/C7534/C7538/P7538
15­4
VSS / V SS
XOUT
XIN
VPP / TEST
P4.0 / BTCO
P4.1
RESET
RESET / RESET
P4.2
NC
P4.3
P5.0
P5.1
P5.2
P5.3
P6.0 / KS0
P6.1 / KS1
VDD / VDD
P3.1 / TCL1 / SCLK
P3.0 / TCL0 / SDAT
P2.3 / BUZ
P2.2 / CLO
P2.1 / TCLO1
P2.0 / TCLO0
P1.0 / INT0
NC
DTMF
P7.3 / KS7
P7.2 / KS6
P7.1 / KS5
P7.0 / KS4
P6.3 / KS3
P6.2 / KS2
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
(32-SOP-405A)
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
S3P7538
Figure 15-4. S3P7538 Pin Assignments (32-SOP)
S3C7524/C7528/P7528/C7534/C7538/P7538
S3P7528/P7538 OTP
15­5
Table 15-1. S3P7528 Pin Descriptions Used to Read/Write the EPROM
Main Chip
During Programming
Pin Name
Pin Name
Pin No.
I/O
Function
P3.0
SDAT
9 (3)
I/O
Serial data pin. Output port when reading and
input port when writing. Can be assigned as a
Input / push-pull output port.
P3.1
SCLK
10 (4)
I/O
Serial clock pin. Input only pin.
TEST
V
PP
(TEST)
15 (9)
I
Power supply pin for EPROM cell writing
(indicates that OTP enters into the writing mode).
When 12.5 V is applied, OTP is in writing mode
and when 5 V is applied, OTP is in reading mode.
(Option)
RESET
RESET
18 (12)
I
Chip initialization
V
DD
/ V
SS
V
DD
/ V
SS
11/12
(5/6)
I
Logic power supply pin. V
DD
should be tied to +5
V during programming.
NOTE: Parentheses indicate pin numbers of 44 QFP package.
Table 15-2. S3P7538 Pin Descriptions Used to Read/Write the EPROM
Main Chip
During Programming
Pin Name
Pin Name
Pin No.
I/O
Function
P3.0
SDAT
28 (30)
I/O
Serial data pin. Output port when reading and
input port when writing. Can be assigned as a
Input / push-pull output port.
P3.1
SCLK
29 (31)
I/O
Serial clock pin. Input only pin.
TEST
V
PP
(TEST)
4 (4)
I
Power supply pin for EPROM cell writing
(indicates that OTP enters into the writing mode).
When 12.5 V is applied, OTP is in writing mode
and when 5 V is applied, OTP is in reading mode.
(Option)
RESET
RESET
7 (7)
I
Chip initialization
V
DD
/ V
SS
V
DD
/ V
SS
30/1
(32/1)
I
Logic power supply pin. V
DD
should be tied to +5
V during programming.
NOTE: Parentheses indicate pin numbers of 32 SDIP package.
S3P7528/P7538 OTP
S3C7524/C7528/P7528/C7534/C7538/P7538
15­6
Table 15-3. Comparison of S3P7528 and S3C7528 Features
Characteristic
S3P7528
S3C7528
Program Memory
8 K byte EPROM
8 K byte mask ROM
Operating Voltage (V
DD
)
2.0 V to 5.5 V
2.0 V to 5.5 V
OTP Programming Mode
V
DD
= 5 V, V
PP
(TEST) = 12.5 V
­
Pin Configuration
42 SDIP / 44 QFP
42 SDIP / 44 QFP
EPROM Programmability
User Program 1 time
Programmed at the factory
Table 15-4. Comparison of S3P7538 and S3C7538 Features
Characteristic
S3P7538
S3C7538
Program Memory
8 K byte EPROM
8 K byte mask ROM
Operating Voltage (V
DD
)
2.0 V to 5.5 V
2.0 V to 5.5 V
OTP Programming Mode
V
DD
= 5 V, V
PP
(TEST) = 12.5 V
­
Pin Configuration
30 SOP / 32 SOP
30 SOP / 32 SOP
EPROM Programmability
User Program 1 time
Programmed at the factory
OPERATING MODE CHARACTERISTICS
When 12.5 V is supplied to the V
PP
(TEST) pin of the S3P7528, the EPROM programming mode is entered. The
operating mode (read, write, or read protection) is selected according to the input signals to the pins listed in
Table 15-3 below.
Table 15-5. Operating Mode Selection Criteria
V
DD
Vpp
(TEST)
REG/
MEM
MEM
Address
(A15-A0)
R/
W
W
Mode
5 V
5 V
0
0000H
1
EPROM read
12.5V
0
0000H
0
EPROM program
12.5V
0
0000H
1
EPROM verify
12.5V
1
0E3FH
0
EPROM read protection
NOTE: "0" means Low level; "1" means High level.
S3C7524/C7528/P7528/C7534/C7538/P7538
S3P7528/P7538 OTP
15­7
START
Address= First Location
V
DD
=5V, V
PP
=12.5V
x = 0
Program One 1ms Pulse
Increment X
x = 10
Verify 1 Byte
Last Address
V
DD
= V
PP
= 5 V
Compare All Byte
Device Passed
Increment Address
Verify Byte
Device Failed
PASS
FAIL
NO
FAIL
YES
FAIL
NO
Figure 15-5. OTP Programming Algorithm
S3P7528/P7538 OTP
S3C7524/C7528/P7528/C7534/C7538/P7538
15­8
NOTES