S3C7324/P7324
PRODUCT OVERVIEW
1-1
1
PRODUCT OVERVIEW
OVERVIEW
The S3C7324 single-chip CMOS microcontroller has been designed for high performance using Samsung's
newest 4-bit CPU core, SAM47 (Samsung Arrangeable Microcontrollers).
With features such as LCD direct drive capability, 4-channel A/D converter, 24-bit AM/FM frequency counter and
watch timer, the S3C7324 offers an excellent design solution for a wide variety of applications that require LCD
functions and audio applications.
Up to 32 pins of the 64-pin QFP package, it can be dedicated to I/O. Five vectored interrupts provide fast
response to internal and external events. In addition, the S3C7324 's advanced CMOS technology provides for
low power consumption and a wide operating voltage range.
OTP
The S3C7324 microcontroller is also available in OTP (One Time Programmable) version, S3P7324 . The
S3P7324 microcontroller has an on-chip 4-Kbyte one-time-programmable EPROM instead of masked ROM. The
S3P7324 is comparable to S3C7324, both in function and in pin configuration.
PRODUCT OVERVIEW
S3C7324/P7324
1-2
FEATURES
Memory
-- 256
×
4-bit RAM
-- 4096
×
8-bit ROM
I/O Pins
-- Input only: 8 pins
-- I/O: 16 pins
-- Output only: 8 pins sharing with segment driver
outputs
LCD Controller/Driver
-- Maximum 14-digit LCD direct drive capability
-- 28 segment and 4 common pins
-- Display modes: Static, 1/2 duty (1/2 bias)
1/3 duty (1/2 or 1/3 bias), 1/4 duty (1/3 bias)
-- Internal resistor circuit for LCD bias
8-Bit Basic Timer
-- Programmable interval timer
-- Watchdog timer
8-Bit Timer
-- Programmable 8-bit timer
Watch Timer
-- Real-time and interval time measurement
-- Four frequency outputs to BUZ pin
-- Clock source generation for LCD
24-Bit Frequency Counter (FC)
-- Level = 300mVpp (Min.)
-- AMF input range = 0.5 MHz to 10 MHz
-- FMF input range = 30 MHz to 150 MHz
A/D Converter
-- 4-channels with 8-bit resolution
-- 17
µ
s (Min.) conversion speed
Bit Sequential Carrier
-- Support 16-bit serial data transfer in arbitrary
format
Interrupts
-- Two internal vectored interrupts
-- Three external vectored interrupts
-- Two quasi-interrupts
Memory-Mapped I/O Structure
-- Data memory bank 15
Two Power-Down Modes
-- Idle mode (only CPU clock stops)
-- Stop mode (main system clock stops)
-- Subsystem clock stops
Oscillation Sources
-- Crystal, ceramic, or RC for main system clock
-- Crystal or external oscillator for subsystem clock
-- Main system clock frequency: 4.19 MHz (typical)
-- Subsystem clock frequency: 32.768 kHz
-- CPU clock divider circuit (by 4, 8, or 64)
Instruction Execution Times
-- 0.95, 1.91, 15.3 µs at 4.19 MHz (main)
-- 122 µs at 32.768 kHz (subsystem)
Operating Temperature
-- 40
°
C to 85
°
C
Operating Voltage Range
-- 1.8 V to 5.5 V at 3 MHz
-- 3.0 V to 5.5 V at FC mode
Package Type
-- 64-pin QFP
S3C7324/P7324
PRODUCT OVERVIEW
1-3
BLOCK DIAGRAM
Arithmetic
and
Logic Unit
Interrupt
Control
Block
Instruction
Register
Program
Counter
Program
Status Word
Stack
Pointer
Instruction Decoder
Internal
Interrupts
Clock
I/O Port 1
Input
Port 2
Input
Port 3
A/D
Converter
I/O
Port 4, 5
I/O Port 6
256 x 4-Bit
Data
Memory
4-Kbyte
Program
Memory
Basic
Timer
Watch
Timer
Freq.
Counter
8-Bit
Timer
LCD Driver/
Countroller
Output
Port 8,9
P1.0/INT0
P1.1/INT1
P1.2/INT2
P1.3/INT3
P2.0
P2.1
P2.2/FMF
P2.3/AMF
P3.0/ADC0
P3.1/ADC1
P3.2/ADC2
P3.3/ADC3
P4.0-P4.3
P5.0-P5.3
P6.0/BUZ
P6.1/KS0
P6.2/KS1
P6.3/KS2
FMF
COM0-COM3
AMF
SEG0-SEG19
P8.0-P8.3/
SEG27-SEG24
P9.0-P9.3/
SEG23-SEG20
RESET
XI
N
X
OUT
XT
IN
XT
OUT
Watchdog
Timer
Figure 1-1. S3C7324 Simplified Block Diagram
PRODUCT OVERVIEW
S3C7324/P7324
1-4
PIN ASSIGNMENTS
SEG9
SEG10
SEG11
SEG12
SEG13
SEG14
SEG15
SEG16
SEG17
SEG18
SEG19
P9.3/ SEG20
P9.2/ SEG21
P9.1/SEG22
P9.0/ SEG23
P8.3/ SEG24
P8.2/ SEG25
P8.1/SEG26
P8.0/ SEG27
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
64
63
62
61
60
59
58
57
56
55
54
53
52
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
S3C7324
(Top View)
P2.0
P2.1
P2.2/FMF
P2.3/AMF
P3.0/ADC0
P3.1/ADC1
P3.2/ADC2
P3.3/ADC3
V
DD
V
SS
X
OUT
X
IN
TEST
XT
IN
XT
OUT
RESET
P1.0/INT0
P1.1/INT1
P1.2/INT2
P1.3/INT4
P4.0
P4.1
P4.2
P4.3
P5.0
P5.1
P5.2
P5.3
P6.0/BUZ
P6.1/KS0
P6.2/KS1
P6.3/KS2
COM0
COM1
COM2
COM3
SEG0
SEG1
SEG2
SEG3
SEG4
SEG5
SEG6
SEG7
SEG8
Figure 1-2. S3C7324 64-QFP Pin Assignment
S3C7324/P7324
PRODUCT OVERVIEW
1-5
PIN DESCRIPTIONS
Table 1-1. S3C7324 Pin Descriptions
Pin Name
Pin
Type
Description
Number
Share
Pin
Reset
Value
Circuit
Type
P1.0
P1.1
P1.2
P1.3
I/O
4-bit I/O port.
1-bit or 4-bit read, write, and test are
possible. Each pin can be specified as
input or output port. Pull-up resistors can
be configured by software.
17
18
19
20
INT0
INT1
INT2
INT4
Input
D-4
P2.0
P2.1
P2.2
P2.3
I
4-bit input port. 1-bit and 4-bit read and
test are possible.
Pull-up resistors can be configured by
software.
1
2
3
4
FMF
AMF
Input
A-4
A-4
B-4
B-4
P3.0
P3.1
P3.2
P3.3
I
4-bit input port.
1-bit and 4-bit read and test are possible
Pull-up resistors can be configured by
software.
5
6
7
8
ADC0
ADC1
ADC2
ADC3
Input
F-13
P4.0P4.3
P5.0P5.3
I/O
4-bit I/O ports. N-channel open-drain
output up to 5 V. 1-bit and 4-bit read,
write, and test are possible. Ports 4 and
5 can be paired to support 8-bit data.
Pull-up resistors can be configured by
software.
2124
2528
Input
E-2
P6.0
P6.1
P6.2
P6.3
I/O
1-bit and 4-bit read, write, and test are
possible. Each pin can be specified as
input or output port. Pull-up resistors can
be configured by software.
29
30
31
32
BUZ
KS0
KS1
KS2
Input
D-2
D-4
D-4
D-4
SEG0SEG19
O
LCD segment signal output
6041
Output
H-16
P8.0P8.3
P9.0P9.3
O
4-bit output ports. 1-bit and 4-bit write
and test are possible. Ports 8 and 9 can
be paired to support 8-bit data.
3336
3740
SEG27
SEG20
Output
H-16
COM0COM3
O
LCD common signal output
6461
Output
H-16
V
DD
Main power supply
9
V
SS
Main ground
10
X
OUT
, X
IN
Crystal, ceramic, or RC oscillator pins for
main system clock. (For external clock
input, use X
IN
and input X
IN
's reverse
phase to X
OUT
)
11,12
XT
OUT
, XT
IN
Crystal oscillator pin for a subsystem
clock. (For external clock input, use XT
IN
and input XT
IN
's reverse phase to
XT
OUT
)
15,14
PRODUCT OVERVIEW
S3C7324/P7324
1-6
Table 1-1. S3P7324 Pin Descriptions (Continued)
Pin Name
Pin
Type
Description
Number
Share
Pin
Reset
Value
Circuit
Type
SEG20SEG27
O
LCD segment signal output
4033
P9.0P9.3
P8.0P8.3
Output
H-16
ADC0ADC3
I
ADC input ports
58
P3.0P3.3
Input
F-13
FMF
AMF
I
External FM/AM frequency inputs
3
4
P2.2
P2.3
Input
B-4
INT4
I
External interrupt input with detection of
rising or falling edges.
20
P1.3
Input
A-4
INT2
I
Quasi-interrupt with detection of rising
edge signals.
19
P1.2
Input
A-4
INT1
INT0
I
External interrupt. The triggering edges
for INT0 and INT1 are able to be
selected. Only INT0 is synchronized with
the system clock.
18
17
P1.1
P1.0
Input
A-4
BUZ
O
2, 4, 8, or 16 kHz frequency output for
buzzer sound with 4.19 MHz main
system clock.
29
P6.0
Input
D-2
KS0KS2
I
Quasi-interrupt input with falling edge
detection.
3032
P6.1P6.3
Input
D-4
RESET
I
System reset signal
16
Input
B
TEST
System test pin(must be connected to
V
SS)
13
NOTE: Pull-up resistors for all I/O ports automatically disabled if they are configured to output mode.
S3C7324/P7324
PRODUCT OVERVIEW
1-7
PIN CIRCUIT DIAGRAMS
V
DD
P-CHANNEL
IN
N-CHNNEL
Figure 1-3. Pin Circuit Type A
V
DD
In
Pull-up
Enable
Figure 1-4. Pin Circuit Type A-4
IN
V
DD
Figure 1-5. Pin Circuit Type B
Pull-down
Enable
Feedback
Enable
Type A
Figure 1-6. Pin Circuit Type B-4
PRODUCT OVERVIEW
S3C7324/P7324
1-8
V
DD
Data
Output
Disable
Out
Figure 1-7. Pin Circuit Type C
Pull-up
Enable
Data
Output
Disable
I/O
V
DD
Circuit
TYPE C
Figure 1-8. Pin Circuit Type D-2
Pull-up
Enable
Data
Output
Disable
I/O
V
DD
Circuit
TYPE C
Figure 1-9. Pin Circuit Type D-4
Data
Output
Disable
V
DD
PNE
Pull-up
Enable
I/O
V
DD
Figure 1-10. Pin Circuit Type E-2
S3C7324/P7324
PRODUCT OVERVIEW
1-9
V
DD
ADCEN
In
Data
To ADC
Pull-up Enable
ADC Select
Figure 1-11. Pin Circuit Type F-13
PRODUCT OVERVIEW
S3C7324/P7324
1-10
V
LC0
V
LC1
SEG/COM
and Port Data
V
LC2
V
DD
Out
Figure 1-12. Pin Circuit Type H-16
S3C7324/P7324
ELECTRICAL DATA
15-1
15
ELECTRICAL DATA
OVERVIEW
In this section, information on S3C7324 electrical characteristics is presented as tables and graphics. The
information is arranged in the following order:
Standard Electrical Characteristics
-- Absolute maximum ratings
-- D.C. electrical characteristics
-- Main system clock oscillator characteristics
-- Subsystem clock oscillator characteristics
-- I/O capacitance
-- A.C. electrical characteristics
-- Operating voltage range
Miscellaneous Timing Waveforms
-- A.C timing measurement point
-- Clock timing measurement at X
IN
-- Clock timing measurement at XT
IN
-- Input timing for
RESET
-- Input timing for external interrupts
Stop Mode Characteristics and Timing Waveforms
-- RAM data retention supply voltage in stop mode
-- Stop mode release timing when initiated by
RESET
-- Stop mode release timing when initiated by an interrupt request
ELECTRICAL DATA
S3C7324/P7324
15-2
Table 15-1. Absolute Maximum Ratings
(T
A
= 25
°
C)
Parameter
Symbol
Conditions
Rating
Units
Supply Voltage
V
DD
0.3 to + 6.5
V
Input Voltage
V
IN
All I/O ports
0.3 to V
DD
+ 0.3
Output Voltage
V
O
0.3 to V
DD
+ 0.3
Output Current High
I
OH
One I/O port active
15
mA
All I/O ports active
30
Output Current Low
I
OL
One I/O port active
+ 30 (Peak value)
+ 15
(note)
Total value for ports 1, 4, 5 and 6
+ 100 (Peak value)
+ 60
(note)
Operating Temperature
T
A
40 to + 85
°
C
Storage Temperature
T
stg
65 to + 150
NOTE: The values for Output Current Low ( I
OL
) are calculated as Peak Value
×
Duty .
Table 15-2. D.C. Electrical Characteristics
(T
A
= 40
°
C to + 85
°
C, V
DD
= 1.8 V to 5.5 V)
Parameter
Symbol
Conditions
Min
Typ
Max
Units
Input high
voltage
V
IH1
All input pins except those
specified below
0.7 V
DD
V
DD
V
V
IH2
P1, P3,
RESET
, P2.0
-
1 and
P6.1
-
3
0.8 V
DD
V
DD
V
IH3
X
IN
, X
OUT
, XT
IN
, and XT
OUT
V
DD
0.1
V
DD
Input low
voltage
V
IL1
All input pins except those
specified below
0.3 V
DD
V
V
IL2
P1, P3,
RESET
, P2.0
-
1 and
P6.1
-
3
0.2 V
DD
V
IL3
X
IN
, X
OUT
, XT
IN
, and XT
OUT
0.1
Output high
voltage
V
OH1
V
DD
= 4.5 V to 5.5 V
I
OH
= 1 mA
Ports 1, 4, 5, and 6
V
DD
1.0
V
V
OH2
V
DD
= 4.5 V to 5.5 V
I
OH
= 100 µA Port 8 and 9
V
DD
2.0
S3C7324/P7324
ELECTRICAL DATA
15-3
Table 15-2. D.C. Electrical Characteristics (Continued)
(T
A
= 40
°
C to + 85
°
C, V
DD
= 1.8 V to 5.5 V)
Parameter
Symbol
Conditions
Min
Typ
Max
Units
Output low
voltage
V
OL1
V
DD
= 4.5 V to 5.5 V
I
OL
= 15 mA, Ports 1, 4, 5, and 6
0.4
2
V
V
OL2
V
DD
= 4.5 V to 5.5 V
I
OL
= 100
µ
A ; Ports 8and 9
1
Input high
leakage
current
(note)
I
LIH1
V
IN
= V
DD
All input pins
3
µ
A
Input low
leakage
current
(note)
I
LIL1
V
IN
= 0 V
All input pins
3
Output high
leakage
current
(note)
I
LOH1
V
OUT
= V
DD
All output pins
3
Output low
leakage
current
(note)
I
LOL
V
OUT
= 0 V
All output pins
3
Pull-up
resistor
R
L1
V
IN
= 0 V; V
DD
= 5 V
Ports 1, 2, 3, 4, 5, and 6
20
40
80
K
V
DD
= 3 V
30
95
200
R
L2
V
IN
= 0 V; V
DD
= 5 V
RESET
100
230
400
V
DD
= 3 V
200
480
800
NOTE: Except for X
IN
, X
OUT
, XT
IN
, and XT
OUT
ELECTRICAL DATA
S3C7324/P7324
15-4
Table 15-2. D.C. Electrical Characteristics (Continued)
(T
A
= 40
°
C to + 85
°
C, V
DD
= 1.8 V to 5.5 V)
Parameter
Symbol
Conditions
Min
Typ
Max
Units
LCD voltage
dividing
resistor
R
LCD
T
A =
25
ø
C
60
84
130
K
COM output
R
COM
V
DD
= 5 V
-
3
6
impedance
V
DD
= 3 V
5
15
SEG output
R
SEG
V
DD
= 5 V
3
6
impedance
V
DD
= 3 V
5
15
COM output
voltage
deviation
V
DC
VDD = 5 V (V
LC0
-COMi)
Io =
±
15uA (I = 03)
±
45
±
90
mV
SEG output
voltage
deviation
V
DS
V
DD
= 5 V (V
LC0
-SEGi)
Io =
±
15uA (I = 027)
±
45
±
90
Oscillator
feedback
resistor
R
OSC1
V
DD
= 5.0 V; T
A
= 25; X
IN
= V
DD
,
X
OUT
= 0 V
300
600
1500
K
R
OSC2
V
DD
= 5.0 V; T
A
= 25; XT
IN
= V
DD
,
XT
OUT
= 0 V
1230
2630
4000
S3C7324/P7324
ELECTRICAL DATA
15-5
Table 15-2. D.C. Electrical Characteristics (Concluded)
(T
A
= 40
°
C to + 85
°
C, V
DD
= 1.8 V to 5.5 V)
Parameter
Symbol
Conditions
Min
Typ
Max
Units
Supply
Current
(1)
I
DD1
Main operating:
FC enable
PCON = 0011B, SCMOD = 0000B
Crystal oscillator
C1 = C2 = 22 pF
V
DD
= 5 V
±
10%
4.19 MHz
5.2
10
mA
I
DD2
(2)
Main operating:
6.0 MHz
3.5
8
PCON = 0011B, SCMOD = 0000B
Crystal oscillator
C1 = C2 = 22 pF
V
DD
= 5 V
±
10%
4.19 MHz
2.5
5.5
V
DD
= 3 V
±
10%
6.0 MHz
1.6
4
4.19 MHz
1.2
3
I
DD3
(2)
Main idle mode
(3)
:
6.0 MHz
1.0
2.5
PCON = 0111B,
SCMOD =0000B
Crystal oscillator
C1 = C2 = 22 pF
V
DD
= 5 V
±
10%
4.19 MHz
0.9
2.0
V
DD
= 3 V
±
10%
6.0 MHz
0.5
1.0
4.19 MHz
0.4
0.8
I
DD4
(2)
Sub operating mode:
PCON = 0011B, SCMOD = 1001B
V
DD
= 3 V
±
10%
32 kHz crystal oscillator
15
30
uA
I
DD5
(2)
Sub idle mode:
PCON = 0111B, SCMOD = 1001B
V
DD
= 3 V
±
10%
32 kHz crystal oscillator
6
15
I
DD6(2)
Stop mode:
CPU = fxt/4, SCMOD = 1101B
V
DD
= 5 V
±
10%
0.5
3
I
DD7
(2)
Stop mode:
CPU = fx/4, SCMOD = 0100B
V
DD
= 5 V
±
10%
NOTES:
1.
Supply current does not include current drawn through internal pull-up resistors and LCD voltage dividing resistors.
2.
AMF or FMF is a normal input mode.
3.
Data includes the power consumption for sub-system clock oscillation.
ELECTRICAL DATA
S3C7324/P7324
15-6
Table 15-3. Main System Clock Oscillator Characteristics
(T
A
= 40
°
C + 85
°
C, V
DD
= 1.8 V to 5.5 V)
Oscillator
Clock
Configuration
Parameter
Test Condition
Min
Typ
Max
Units
Ceramic
Oscillator
X
IN
X
OUT
C1
C2
Oscillation frequency
(1)
0.4
6.0
MHz
Stabilization time
(2)
Stabilization occurs
when V
DD
is equal to
the minimum oscillator
voltage range.
4
ms
Crystal
Oscillator
C1
C2
X
IN
X
OUT
Oscillation frequency
(1)
0.4
6.0
MHz
Stabilization time
(2)
V
DD
= 2.7 V to 5.5 V
10
ms
V
DD
= 1.8 V to 2.7 V
30
External
Clock
X
IN
X
OUT
X
IN
input frequency
(1)
0.4
6.0
MHz
X
IN
input high and low
level width (t
XH
, t
XL
)
83.3
ns
RC
Oscillator
R
X
IN
X
OUT
Frequency
(1)
V
DD
= 5 V
R = 15 K
, V
DD
= 5 V
R = 25 K
, V
DD
= 3 V
0.4
-
2.0
1.0
2.5
MHz
NOTES:
1.
Oscillation frequency and X
IN
input frequency data are for oscillator characteristics only.
2.
Stabilization time is the interval required for oscillator stabilization after a power-on occurs, or when stop mode is
terminated.
S3C7324/P7324
ELECTRICAL DATA
15-7
Table 15-4. Subsystem Clock Oscillator Characteristics
(T
A
= 40
°
C + 85
°
C, V
DD
= 1.8 V to 5.5 V)
Oscillator
Clock
Configuration
Parameter
Test Condition
Min
Typ
Max
Units
Crystal
Oscillator
XT
IN
XT
OUT
C1
C2
Oscillation frequency
(1)
32
32.768
35
kHz
Stabilization time
(2)
V
DD
= 2.7 V to 5.5 V
1.0
2
s
V
DD
= 1.8 V to 2.7 V
10
External
Clock
XT
IN
XT
OUT
XT
IN
input frequency
(1)
32
100
kHz
XT
IN
input high and
low level width (t
XTL
,
t
XTH
)
5
15
µ
s
NOTES:
1.
Oscillation frequency and XT
IN
input frequency data are for oscillator characteristics only.
2.
Stabilization time is the interval required for oscillator stabilization after a power-on occurs.
ELECTRICAL DATA
S3C7324/P7324
15-8
Table 15-5. Input/Output Capacitance
(T
A
= 25
°
C, V
DD
=
0 V )
Parameter
Symbol
Condition
Min
Typ
Max
Units
Input
capacitance
C
IN
f
CLK
= 1 MHz; Unmeasured
pins are returned to V
SS
15
pF
Output
capacitance
C
OUT
15
pF
I/O capacitance
C
IO
15
pF
Table 15-6. A.C. Electrical Characteristics
(T
A
= 40
°
C to + 85
°
C, V
DD
= 1.8 V to 5.5 V)
Parameter
Symbol
Conditions
Min
Typ
Max
Units
Instruction cycle
t
CY
V
DD
= 2.7 V to 5.5 V
0.67
64
µ
s
time
(1)
V
DD
= 1.8 V to 5.5 V
1.3
64
Interrupt input
t
INTH
, t
INTL
INT0
(2)
µ
s
high, low width
INT1, INT2, INT4, KS0KS2
10
RESET
Input Low
Width
t
RSL
Input
10
µ
s
NOTES:
1.
Unless otherwise specified, Instruction Cycle Time condition values assume a main system clock/4 (fx/4) source.
2.
Minimum value for INT0 is based on a clock of 2t
CY
or 128/fxx as assigned by the IMOD0 register setting.
Table 15-6. A.C. Electrical Characteristics (continued)
(T
A
= 10
°
C to + 70
°
C, V
DD
= 3.5 V to 5.5 V)
Parameter
Symbol
Conditions
Min
Typ
Max
Units
A/D converting
Resolution
8
8
8
bits
Absolute accuracy
±
2
LSB
AD conversion
time
t
CON
17
34/fxx
(note)
µ
s
Analog input
voltage
V
IAN
V
SS
V
DD
V
Analog input
impedance
R
AN
2
1000
M
NOTE: fxx stands for the system clock (fx or fxt).
S3C7324/P7324
ELECTRICAL DATA
15-9
Table 15-6. A.C. Electrical Characteristics (continued)
(T
A
= 40
°
C to + 85
°
C, V
DD
= 3.0 V to 5.5 V)
Parameter
Symbol
Conditions
Min
Typ
Max
Units
Input voltage
(peak to peak)
V
IN
AMF/FMF mode, sine
wave input
0.3
V
DD
V
Frequency
f
AMF
AMF mode, sine wave
input; V
IN
= 300mV
P-P
0.5
10
MHz
f
FMF
FMF mode, sine wave
input; V
IN
= 300mV
P-P
30
150
CPU CLOCK = 1/n x oscillator frequency (n = 4, 8, 64)
1
SUPPLY VOLTAGE (V)
250 kHz
500 kHz
15.6 kHz
CPU CLOCK
750 kHz
1.0475 MHz
1.5 MHz
2
3
4
5
6
7
Main OSC. Freq.
3 MHz
4.19 MHz
6 MHz
400 kHz
When FC operates, operating voltage range is 3.0 V to 5.5 V.
Figure 15-1. Standard Operating Voltage Range
Table 15-7. RAM Data Retention Supply Voltage in Stop Mode
(T
A
= 40
°
C to + 85
°
C)
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
Data retention supply voltage
V
DDDR
Normal operation
1.8
5.5
V
Data retention supply current
I
DDDR
V
DDDR
= 1.8 V
0.1
1
µ
A
ELECTRICAL DATA
S3C7324/P7324
15-10
TIMING WAVEFORMS
t
SREL
t
WAIT
V
DD
RESET
EXECUTION OF
STOP INSTRUCTION
V
DDDR
DATA RETENTION MODE
STOP MODE
INTERNAL RESET
OPERATION
IDLE MODE
OPERATING
MODE
Figure 15-2. Stop Mode Release Timing When Initiated by
RESET
RESET
V
DD
EXECUTION OF
STOP INSTRUCTION
V
DDDR
DATA RETENTION MODE
STOP MODE
t
WAIT
t
SREL
IDLE MODE
NORMAL
OPERATING
MODE
POWER-DOWN MODE TERMINATING SIGNAL
(INTERRUPT REQUEST)
Figure 15-3. Stop Mode Release Timing When Initiated by an Interrupt Request
S3C7324/P7324
ELECTRICAL DATA
15-11
0.8
V
DD
0.2
V
DD
0.8
V
DD
0.2
V
DD
MEASUREMENT
POINTS
Figure 15-4. A.C. Timing Measurement Points (Except for X
in
and XT
in
)
Xin
t
XL
t
XH
1 / fx
V
DD
0.1 V
0.1 V
Figure 15-5. Clock Timing Measurement at X
in
XTin
t
XTL
t
XTH
1 / fxt
V
DD
0.1 V
0.1 V
Figure 15-6. Clock Timing Measurement at XT
in
ELECTRICAL DATA
S3C7324/P7324
15-12
RESET
tRSL
0.2 VDD
Figure 15-7. Input Timing for
RESET
RESET
Signal
INT0, 1, 2, 4
KS0 to KS2
t
INTL
tINTH
0.8 VDD
0.2 VDD
Figure 15-8. Input Timing for External Interrupts and Quasi-Interrupts
S3C7324/P7324
MECHANICAL DATA
16-1
16
MECHANICAL DATA
OVERVIEW
The S3C7324 microcontroller is available in a 64-pin QFP package (Samsung: 64-QFP-1420F).
Package dimensions are shown in Figure 16-1.
NOTE: Dimensions are in millimeters.
17.90 ± 0.3
14.00 ± 0.2
(1.00
)
64-QFP-1420F
23.90 ± 0.3
#64
(1.00)
#1
0.40
+0.10
- 0.05
± 0.15MAX
0.80
± 0.20
2.65
± 0.10
0.05~0.25
3.00 MAX
0.15
+0.10
- 0.05
0-8°
0.10 MAX
0.80
± 0.20
1.00
20.00 ± 0.2
Figure 16-1. 64-QFP-1420F Package Dimensions
S3C7324/P7324
S3P7324 OTP
17-1
17
S3P7324 OTP
OVERVIEW
The S3P7324 single-chip CMOS microcontroller is the OTP (One Time Programmable)
version of the
S3C7324microcontroller. It has an on-chip EPROM instead of masked ROM. The EPROM is accessed by a serial
data format.
The S3P7324 is fully compatible with the S3C7324, both in function and in pin configuration. Because of its
simple programming requirements, the S3P7324 is ideal for use as an evaluation chip for the S3C7324.
S3P7324 OTP
S3C7324/P7324
17-2
SEG9
SEG10
SEG11
SEG12
SEG13
SEG14
SEG15
SEG16
SEG17
SEG18
SEG19
P9.3/ SEG20
P9.2/ SEG21
P9.1/SEG22
P9.0/ SEG23
P8.3/ SEG24
P8.2/ SEG25
P8.1/SEG26
P8.0/ SEG27
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
64
63
62
61
60
59
58
57
56
55
54
53
52
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
S3P7324
(Top View)
P2. 0
P2.1
P2.2/FMF
P2.3/AMF
P3.0/ADC0
P3.1/ADC1
SDAT/P3.2/ADC2
SCLK /P3.3/ADC3
V
DD
/V
DD
V
SS
/V
SS
X
OUT
X
IN
V
PP
/TEST
XT
IN
XT
OUT
RESET
RESET
/
RESET
P1.0/INT0
P1.1/INT1
P1.2/INT2
P1.3/INT4
P4.0
P4.1
P4.2
P4.3
P5.0
P5.1
P5.2
P5.3
P6.0/BUZ
P6.1/KS0
P6.2/KS1
P6.3/KS2
COM0
COM1
COM2
COM3
SEG0
SEG1
SEG2
SEG3
SEG4
SEG5
SEG6
SEG7
SEG8
Figure 17-1. S3P7324 Pin Assignments (64-QFP)
S3C7324/P7324
S3P7324 OTP
17-3
Table 17-1. Pin Descriptions Used to Read/Write the EPROM
Main Chip
During Programming
Pin Name
Pin Name
Pin No.
I/O
Function
P3.2
SDAT
7
I/O
Serial data pin. Output port when reading and
input port when writing. Can be assigned as a
Input or push-pull output port.
P3.3
SCLK
8
I/O
Serial clock pin. Input only pin.
TEST
V
PP
(TEST)
13
I
Power supply pin for EPROM cell writing
(indicates that OTP enters into the writing mode).
When 12.5 V is applied, OTP is in writing mode
and when 5 V is applied, OTP is in reading mode.
RESET
RESET
16
I
Chip initialization
V
DD
/ V
SS
V
DD
/ V
SS
9/10
I
Logic power supply pin. V
DD
should be tied to +5
V during programming.
Table 17-2. Comparison of S3P7324 and S3C7324 Features
Characteristic
S3P7324
S3C7324
Program Memory
4K bytes EPROM
4K bytes mask ROM
Operating Voltage (V
DD
)
2.0 V to 5.5 V at 4.19 MHz
1.8 V to 5.5 V at 3 MHz
2.0 V to 5.5 V at 4.19 MHz
1.8 V to 5.5 V at 3 MHz
OTP Programming Mode
V
DD
= 5 V, V
PP
(TEST) = 12.5 V
Pin Configuration
64 QFP
64 QFP
EPROM Programmability
User Program 1 time
Programmed at the factory
OPERATING MODE CHARACTERISTICS
When 12.5 V is supplied to the V
PP
(TEST) pin of the S3P7324, the EPROM programming mode is entered. The
operating mode (read, write, or read protection) is selected according to the input signals to the pins listed in
Table 17-3 below.
Table 17-3. Operating Mode Selection Criteria
V
DD
V
PP
(TEST)
REG/
MEM
Address
(A15-A0)
R/
W
W
Mode
5 V
5 V
0
0000H
1
EPROM read
12.5 V
0
0000H
0
EPROM program
12.5 V
0
0000H
1
EPROM verify
12.5 V
1
0E3FH
0
EPROM read protection
NOTE: "0" means low level; "1" means high level.
S3P7324 OTP
S3C7324/P7324
17-4
Table 17-4. D.C. Electrical Characteristics
(T
A
= 40
°
C to + 85
°
C, V
DD
= 1.8 V to 5.5 V)
Parameter
Symbol
Conditions
Min
Typ
Max
Units
Input high
voltage
V
IH1
All input pins except those
specified below
0.7 V
DD
V
DD
V
V
IH2
P1, P3,
RESET
, P2.0
-
1 and
P6.1
-
3
0.8 V
DD
V
DD
V
IH3
X
IN
, X
OUT
, XT
IN
, and XT
OUT
V
DD
0.1
V
DD
Input low
voltage
V
IL1
All input pins except those
specified below
0.3 V
DD
V
V
IL2
P1, P3,
RESET
, P2.0
-
1 and
P6.1
-
3
0.2 V
DD
V
IL3
X
IN
, X
OUT
, XT
IN
, and XT
OUT
0.1
Output high
voltage
V
OH1
V
DD
= 4.5 V to 5.5 V
I
OH
= 1 mA
Ports 1, 4, 5, and 6
V
DD
1.0
V
V
OH2
V
DD
= 4.5 V to 5.5 V
I
OH
= 100 µA Port 8 and 9
V
DD
2.0
S3C7324/P7324
S3P7324 OTP
17-5
Table 17-4. D.C. Electrical Characteristics (Continued)
(T
A
= 40
°
C to + 85
°
C, V
DD
= 1.8 V to 5.5 V)
Parameter
Symbol
Conditions
Min
Typ
Max
Units
Output low
voltage
V
OL1
V
DD
= 4.5 V to 5.5 V
I
OL
= 15 mA, Ports 1, 4, 5, and 6
0.4
2
V
V
OL2
V
DD
= 4.5 V to 5.5 V
I
OL
= 100
µ
A ; Ports 8 and 9
1
Input high
leakage
current
(note)
I
LIH1
V
IN
= V
DD
All input pins
3
µ
A
Input low
leakage
current
(note)
I
LIL1
V
IN
= 0 V
All input pins
3
Output high
leakage
current
(note)
I
LOH1
V
OUT
= V
DD
All output pins
3
Output low
leakage
current
(note)
I
LOL
V
OUT
= 0 V
All output pins
3
Pull-up
resistor
R
L1
V
IN
= 0 V; V
DD
= 5 V
Ports 1, 2, 3, 4, 5, and 6
20
40
80
K
V
DD
= 3 V
30
95
200
R
L2
V
IN
= 0 V; V
DD
= 5 V
RESET
100
230
400
V
DD
= 3 V
200
480
800
NOTE: Except for X
IN
, X
OUT
, XT
IN
, and XT
OUT
S3P7324 OTP
S3C7324/P7324
17-6
Table 17-4. D.C. Electrical Characteristics (Continued)
(T
A
= 40
°
C to + 85
°
C, V
DD
= 1.8 V to 5.5 V)
Parameter
Symbol
Conditions
Min
Typ
Max
Units
LCD voltage
dividing
resistor
R
LCD
T
A =
25
ø
C
60
84
130
K
COM output
R
COM
V
DD
= 5 V
-
3
6
impedance
V
DD
= 3 V
5
15
SEG output
R
SEG
V
DD
= 5 V
3
6
impedance
V
DD
= 3 V
5
15
COM output
voltage
deviation
V
DC
V
DD
= 5 V (V
LC0
-COMi)
Io =
±
15uA (I = 03)
±
45
±
90
mV
SEG output
voltage
deviation
V
DS
V
DD
= 5 V (V
LC0
-SEGi)
Io =
±
15uA (I = 027)
±
45
±
90
Oscillator
feedback
resistor
R
OSC1
V
DD
= 5.0 V; T
A
= 25; X
IN
= V
DD
,
X
OUT
= 0 V
300
600
1500
K
R
OSC2
V
DD
= 5.0 V; T
A
= 25; XT
IN
= V
DD
,
XT
OUT
= 0 V
1230
2630
4000
S3C7324/P7324
S3P7324 OTP
17-7
Table 17-4. D.C. Electrical Characteristics (Concluded)
(T
A
= 40
°
C to + 85
°
C, V
DD
= 1.8 V to 5.5 V)
Parameter
Symbol
Conditions
Min
Typ
Max
Units
Supply
Current
(1)
I
DD1
Main operating:
FC enable
PCON = 0011B, SCMOD = 0000B
Crystal oscillator
C1 = C2 = 22 pF
V
DD
= 5 V
±
10%
4.19 MHz
5.2
10
mA
I
DD2
(2)
Main operating:
6.0 MHz
3.5
8
PCON = 0011B, SCMOD = 0000B
Crystal oscillator
C1 = C2 = 22 pF
V
DD
= 5 V
±
10%
4.19 MHz
2.5
5.5
V
DD
= 3 V
±
10%
6.0 MHz
1.6
4
4.19 MHz
1.2
3
I
DD3
(2)
Main idle mode
(3)
:
6.0 MHz
1.0
2.5
PCON = 0111B,
SCMOD =0000B
Crystal oscillator
C1 = C2 = 22 pF
V
DD
= 5 V
±
10%
4.19 MHz
0.9
2.0
V
DD
= 3 V
±
10%
6.0 MHz
0.5
1.0
4.19 MHz
0.4
0.8
I
DD4
(2)
Sub operating mode:
PCON = 0011B, SCMOD = 1001B
V
DD
= 3 V
±
10%
32 kHz crystal oscillator
15
30
uA
I
DD5
(2)
Sub idle mode:
PCON = 0111B, SCMOD = 1001B
V
DD
= 3 V
±
10%
32 kHz crystal oscillator
6
15
I
DD6(2)
Stop mode:
CPU = fxt/4, SCMOD = 1101B
V
DD
= 5 V
±
10%
0.5
3
I
DD7
(2)
Stop mode:
CPU = fx/4, SCMOD = 0100B
V
DD
= 5 V
±
10%
NOTES:
1.
Supply current does not include current drawn through internal pull-up resistors and LCD voltage dividing resistors.
2.
AMF or FMF is a normal input mode.
3.
Data includes the power consumption for sub-system clock oscillation.
S3P7324 OTP
S3C7324/P7324
17-8
Table 17-5. Main System Clock Oscillator Characteristics
(T
A
= 40
°
C + 85
°
C, V
DD
= 1.8 V to 5.5 V)
Oscillator
Clock
Configuration
Parameter
Test Condition
Min
Typ
Max
Units
Ceramic
Oscillator
X
IN
X
OUT
C1
C2
Oscillation frequency
(1)
0.4
6.0
MHz
Stabilization time
(2)
Stabilization occurs
when V
DD
is equal to
the minimum oscillator
voltage range.
4
ms
Crystal
Oscillator
C1
C2
X
IN
X
OUT
Oscillation frequency
(1)
0.4
6.0
MHz
Stabilization time
(2)
V
DD
= 2.7 V to 5.5 V
10
ms
V
DD
= 1.8 V to 2.7 V
30
External
Clock
X
IN
X
OUT
X
IN
input frequency
(1)
0.4
6.0
MHz
X
IN
input high and low
level width (t
XH
, t
XL
)
83.3
ns
RC
Oscillator
R
X
IN
X
OUT
Frequency
(1)
V
DD
= 5 V
R = 15 K
, V
DD
= 5 V
R = 25 K
, V
DD
= 3 V
0.4
-
2.0
1.0
2.5
MHz
NOTES:
1.
Oscillation frequency and X
IN
input frequency data are for oscillator characteristics only.
2.
Stabilization time is the interval required for oscillator stabilization after a power-on occurs, or when stop mode is
terminated.
S3C7324/P7324
S3P7324 OTP
17-9
Table 17-6. Subsystem Clock Oscillator Characteristics
(T
A
= 40
°
C + 85
°
C, V
DD
= 1.8 V to 5.5 V)
Oscillator
Clock
Configuration
Parameter
Test Condition
Min
Typ
Max
Units
Crystal
Oscillator
XT
IN
XT
OUT
C1
C2
Oscillation frequency
(1)
32
32.768
35
kHz
Stabilization time
(2)
V
DD
= 2.7 V to 5.5 V
1.0
2
s
V
DD
= 1.8 V to 2.7 V
10
External
Clock
XT
IN
XT
OUT
XT
IN
input frequency
(1)
32
100
kHz
XT
IN
input high and
low level width (t
XTL
,
t
XTH
)
5
15
µ
s
NOTES:
1.
Oscillation frequency and XT
IN
input frequency data are for oscillator characteristics only.
2.
Stabilization time is the interval required for oscillator stabilization after a power-on occurs.
S3P7324 OTP
S3C7324/P7324
17-10
Table 17-7. Input/Output Capacitance
(T
A
= 25
°
C, V
DD
=
0 V )
Parameter
Symbol
Condition
Min
Typ
Max
Units
Input
capacitance
C
IN
f
CLK
= 1 MHz; Unmeasured
pins are returned to V
SS
15
pF
Output
capacitance
C
OUT
15
pF
I/O capacitance
C
IO
15
pF
Table 17-8. A.C. Electrical Characteristics
(T
A
= 40
°
C to + 85
°
C, V
DD
= 1.8 V to 5.5 V)
Parameter
Symbol
Conditions
Min
Typ
Max
Units
Instruction cycle
t
CY
V
DD
= 2.7 V to 5.5 V
0.67
64
µ
s
time
(1)
V
DD
= 1.8 V to 5.5 V
1.3
64
Interrupt input
t
INTH
, t
INTL
INT0
(2)
µ
s
high, low width
INT1, INT2, INT4, KS0KS2
10
RESET
Input Low
Width
t
RSL
Input
10
µ
s
NOTES:
1.
Unless otherwise specified, Instruction Cycle Time condition values assume a main system clock/4 (fx/4) source.
2.
Minimum value for INT0 is based on a clock of 2t
CY
or 128/fxx as assigned by the IMOD0 register setting.
Table 17-8. A.C. Electrical Characteristics (continued)
(T
A
= 10
°
C to + 70
°
C, V
DD
= 3.5 V to 5.5 V)
Parameter
Symbol
Conditions
Min
Typ
Max
Units
A/D converting
Resolution
8
8
8
bits
Absolute accuracy
±
2
LSB
AD conversion
time
t
CON
17
34/fxx
(note)
µ
s
Analog input
voltage
V
IAN
V
SS
V
DD
V
Analog input
impedance
R
AN
2
1000
M
NOTE: fxx stands for the system clock (fx or fxt).
S3C7324/P7324
S3P7324 OTP
17-11
Table 17-8. A.C. Electrical Characteristics (continued)
(T
A
= 40
°
C to + 85
°
C, V
DD
= 3.0 V to 5.5 V)
Parameter
Symbol
Conditions
Min
Typ
Max
Units
Input voltage
(peak to peak)
V
IN
AMF/FMF mode, sine
wave input
0.3
V
DD
V
Frequency
f
AMF
AMF mode, sine wave
input; V
IN
= 300mV
P-P
0.5
10
MHz
f
FMF
FMF mode, sine wave
input; V
IN
= 300mV
P-P
30
150
CPU CLOCK = 1/n x oscillator frequency (n = 4, 8, 64)
1
SUPPLY VOLTAGE (V)
250 kHz
500 kHz
15.6 kHz
CPU CLOCK
750 kHz
1.0475 MHz
1.5 MHz
2
3
4
5
6
7
Main OSC. Freq.
3 MHz
4.19 MHz
6 MHz
400 kHz
When FC operates, operating voltage range is 3.0 V to 5.5 V.
Figure 17-2. Standard Operating Voltage Range
Table 17-9. RAM Data Retention Supply Voltage in Stop Mode
(T
A
= 40
°
C to + 85
°
C)
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
Data retention supply voltage
V
DDDR
Normal operation
1.8
5.5
V
Data retention supply current
I
DDDR
V
DDDR
= 1.8 V
0.1
1
µ
A
S3P7324 OTP
S3C7324/P7324
17-12
TIMING WAVEFORMS
t
SREL
t
WAIT
V
DD
RESET
EXECUTION OF
STOP INSTRUCTION
V
DDDR
DATA RETENTION MODE
STOP MODE
INTERNAL RESET
OPERATION
IDLE MODE
OPERATING
MODE
Figure 17-3. Stop Mode Release Timing When Initiated by
RESET
RESET
V
DD
EXECUTION OF
STOP INSTRUCTION
V
DDDR
DATA RETENTION MODE
STOP MODE
t
WAIT
t
SREL
IDLE MODE
NORMAL
OPERATING
MODE
POWER-DOWN MODE TERMINATING SIGNAL
(INTERRUPT REQUEST)
Figure 17-4. Stop Mode Release Timing When Initiated by an Interrupt Request
S3C7324/P7324
S3P7324 OTP
17-13
0.8
V
DD
0.2
V
DD
0.8
V
DD
0.2
V
DD
MEASUREMENT
POINTS
Figure 17-5. A.C. Timing Measurement Points (Except for X
in
and XT
in
)
Xin
t
XL
t
XH
1 / fx
V
DD
0.1 V
0.1 V
Figure 17-6. Clock Timing Measurement at X
in
XTin
t
XTL
t
XTH
1 / fxt
V
DD
0.1 V
0.1 V
Figure 17-7. Clock Timing Measurement at XT
in
S3P7324 OTP
S3C7324/P7324
17-14
RESET
tRSL
0.2 VDD
Figure 17-8. Input Timing for
RESET
RESET
Signal
INT0, 1, 2, 4
KS0 to KS2
t
INTL
tINTH
0.8 VDD
0.2 VDD
Figure 17-9. Input Timing for External Interrupts and Quasi-Interrupts
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