S3C72F5/P72F5
PRODUCT OVERVIEW
1
PRODUCT OVERVIEW
OVERVIEW
The S3C72F5 single-chip CMOS microcontroller has been designed for high performance using Samsung's
newest 4-bit CPU core, SAM47 (Samsung Arrangeable Microcontrollers).
With an up-to-896-dot LCD direct drive capability, 8-bit and 16-bit timer/counter, and serial I/O, the S3C72F5
offers an excellent design solution for a wide variety of applications which require LCD functions.
Up to 39 pins of the 100-pin QFP package can be dedicated to I/O. Eight vectored interrupts provide fast
response to internal and external events. In addition, the S3C72F5's advanced CMOS technology provides for
low power consumption and a wide operating voltage range.
OTP
The S3C72F5 microcontroller is also available in OTP (One Time Programmable) version, S3P72F5. S3P72F5
microcontroller has an on-chip 16K-byte one-time-programable EPROM instead of masked ROM. The S3P72F5
is comparable to S3C72F5, both in function and in pin configuration.
PRODUCT OVERVIEW
S3C72F5/P72F5
12
FEATURES SUMMARY
Memory
·
544
×
4-bit RAM (excluding LCD display RAM)
·
16,384
×
8-bit ROM
39 I/O Pins
·
I/O: 35 pins
·
Input only: 4 pins
LCD Controller/Driver
·
56 segments and 16 common terminals
·
8 and 16 common selectable
·
Internal resistor circuit for LCD bias
·
All dot can be switched on/off
8-bit Basic Timer
·
4 interval timer functions
·
Watch-dog timer
8-bit Timer/Counter
·
Programmable 8-bit timer
·
External event counter
·
Arbitrary clock frequency output
·
External clock signal divider
·
Serial I/O interface clock generator
16-Bit Timer/Counter
·
Programmable 16-bit timer
·
External event counter
·
Arbitrary clock frequency output
·
External clock signal divider
8-bit Serial I/O Interface
·
8-bit transmit/receive mode
·
8-bit receive mode
·
LSB-first or MSB-first transmission selectable
·
Internal or external clock source
Memory-Mapped I/O Structure
·
Data memory bank 15
Watch Timer
·
Time interval generation: 0.5 s, 3.9 ms
at 32768 Hz
·
4 frequency outputs to BUZ pin
·
Clock source generation for LCD
Interrupts
·
Four internal vectored interrupts
·
Four external vectored interrupts
·
Two quasi-interrupts
Bit Sequential Carrier
·
Supports 16-bit serial data transfer in arbitrary
format
Power-Down Modes
·
Idle mode (only CPU clock stops)
·
Stop mode (main system oscillation stops)
·
Subsystem clock stop mode
Oscillation Sources
·
Crystal, ceramic, or RC for main system clock
·
Crystal oscillator for subsystem clock
·
Main system clock frequency: 0.4 6 MHz
·
Subsystem clock frequency: 32.768 kHz
·
CPU clock divider circuit (by 4, 8, or 64)
Instruction Execution Times
·
0.67, 1.33, 10.7 µs at 6 MHz
·
0.95, 1.91, 15.3 µs at 4.19 MHz
·
122 µs at 32.768 kHz
Operating Temperature
·
40
°
C to 85
°
C
Operating Voltage Range
·
1.8 V to 5.5 V
Package Type
·
100-pin QFP
S3C72F5/P72F5
PRODUCT OVERVIEW
BLOCK DIAGRAM
P4.0P4.3/
COM8-COM11
P5.0P5.3/
COM12-COM15
P6.0P6.3/
SEG55-SEG52/
KS4KS7
P7.0P7.3/
SEG51-SEG48
ARITHMETIC
AND
LOGIC UNIT
INTERRUPT
CONTROL
BLOCK
INSTRUCTION
REGISTER
PROGRAM
COUNTER
PROGRAM
STATUS
WORD
544 x 4-BIT
DATA
MEMORY
16 KBYTE
PROGRAM
MEMORY
I/O PORT 2
STACK
POINTER
INSTRUCTION
DECODER
CLOCK
RESET
Xin
XTin
Xout
XTout
INTERNAL
INTERRUPTS
I/O PORT 4
I/O PORT 5
I/O PORT 3
I/O PORT 7
BASIC
TIMER
WATCH
TIMER
P0.0/SCK/K0
P0.1/SO/K1
P0.2/SI/K2
P0.3/BUZ/K3
LCD
DRIVER/
CONTROLLER
SERIAL I/O
VLC1-VLC5
I/O
PORT 0
16-BIT
TIMER/
COUNTER
P8.0P8.3/
SEG47-SEG44
I/O PORT 8
I/O PORT 9
I/O PORT 6
INPUT PORT 1
P9.0P9.3/
SEG43-SEG40
P3.0/TCLO0
P3.1/TCLO1
P3.2/TCL0
P3.3/TCL1
P2.0/CLO
P2.1/LCDCK
P2.2/LCDSY
P1.0-P1.3/
INT0-INT4
8-BIT
TIMER/
COUNTER
COM0-COM7
P4.0-P5.3/
COM8-COM15
SEG0-SEG39
P9.3-P6.0/
SEG40-SEG55
Figure 1-1. S3C72F5 Simplified Block Diagram
PRODUCT OVERVIEW
S3C72F5/P72F5
14
PIN ASSIGNMENTS
SEG25
SEG26
SEG27
SEG28
SEG29
SEG30
SEG31
SEG32
SEG33
SEG34
SEG35
SEG36
SEG37
SEG38
SEG39
P9.3/SEG40
P9.2/SEG41
P9.1/SEG42
P9.0/SEG43
P8.3/SEG44
P8.2/SEG45
P8.1/SEG46
P8.0/SEG47
P7.3/SEG48
P7.2/SEG49
P7.1/SEG50
P7.0/SEG51
P6.3/SEG52/K7
P6.2/SEG53/K6
P6.1/SEG54/K5
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
SEG4
SEG3
SEG2
SEG1
SEG0
VLC5
VLC4
VLC3
VLC2
VLC1
P0.0/
SCK
/K0
P0.1/SO/K1
P0.2/SI/K2
P0.3/BUZ/K3
VDD
VSS
Xout
Xin
TEST
XTin
XTout
RESET
P1.0/INT0
P1.1/INT1
P1.2/INT2
P1.3/INT4
P2.0/CLO
P2.1/LCDCK
P2.2/LCDSY
P3.0/TCLO0
S3C72F5
(100-QFP-1420C)
SEG5
SEG6
SEG7
SEG8
SEG9
SEG10
SEG11
SEG12
SEG13
SEG14
SEG15
SEG16
SEG17
SEG18
SEG19
SEG20
SEG21
SEG22
SEG23
SEG24
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
P3.1/TCLO1
P3.2/TCL0
P3.3/TCL1
COM0
COM1
COM2
COM3
COM4
COM5
COM6
COM7
P4.0/COM8
P4.1/COM9
P4.2/COM10
P4.3/COM11
P5.0/COM12
P5.1/COM13
P5.2/COM14
P5.3/COM15
P6.0/SEG55/K4
Figure 1-2. S3C72F5 100-QFP Pin Assignment Diagram
S3C72F5/P72F5
PRODUCT OVERVIEW
PIN DESCRIPTIONS
Table 11. S3C72F5 Pin Descriptions
Pin Name
Pin Type
Description
Number
Share Pin
P0.0
P0.1
P0.2
P0.3
I/O
4-bit I/O port.
1-bit and 4-bit read/write and test are possible.
Individual pins are software configurable as input or
output.
Individual pins are software configurable as open-
drain or push-pull output.
4-bit pull-up resistors are software assignable; pull-up
resistors are automatically disabled for output pins.
11
12
13
14
SCK
/K0
SO/K1
SI/K2
BUZ/K3
P1.0
P1.1
P1.2
P1.3
I
4-bit input port.
1-bit and 4-bit read and test are possible.
4-bit pull-up resistors are assignable by software.
23
24
25
26
INT0
INT1
INT2
INT4
P2.0
P2.1
P2.2
I/O
Same as port 0 except that port 2 is 3-bit I/O port.
27
28
29
CLO
LCDCK
LCDSY
P3.0
P3.1
P3.2
P3.3
I/O
Same as port 0.
30
31
32
33
TCLO0
TCLO1
TCL0
TCL1
P4.0P4.3
P5.0P5.3
I/O
4-bit I/O ports.
1-, 4-bit or 8-bit read/write and test are possible.
Individual pins are software configurable as input or
output.
4-bit pull-up resistors are software assignable; pull-up
resistors are automatically disabled for output pins.
4245
4649
COM8
COM11
COM12
COM15
P6.0P6.3
P7.0P7.3
I/O
Same as P4, P5.
5053
5457
SEG55/K4
SEG52/K7
SEG51
SEG48
P8.0P8.3
P9.0P9.3
I/O
Same as P4, P5.
5861
6265
SEG47
SEG44
SEG43
SEG40
SCK
I/O
Serial I/O interface clock signal.
11
P0.0/K0
SO
I/O
Serial data output.
12
P0.1/K1
SI
I/O
Serial data input.
13
P0.2/K2
BUZ
I/O
2 kHz, 4 kHz, 8 kHz or 16 kHz frequency output for
buzzer signal.
14
P0.3/K3
INT0, INT1
I
External interrupts. The triggering edge for INT0 and
INT1 is selectable.
23, 24
P1.0, P1.1
PRODUCT OVERVIEW
S3C72F5/P72F5
16
Table 11. S3C72F5 Pin Descriptions (Continued)
Pin Name
Pin Type
Description
Number
Share Pin
INT2
I
Quasi-interrupt with detection of rising or
falling edges.
25
P1.2
INT4
I
External interrupt with detection of rising or
falling edges.
26
P1.3
CLO
I/O
Clock output .
27
P2.0
LCDCK
I/O
LCD clock output for display expansion.
28
P2.1
LCDSY
I/O
LCD synchronization clock output for display
expansion.
29
P2.2
TCLO0
I/O
Timer/counter 0 clock output.
30
P3.0
TCLO1
I/O
Timer/counter 1 clock output.
31
P3.1
TCL0
I/O
External clock input for timer/counter 0.
32
P3.2
TCL1
I/O
External clock input for timer/counter 1.
33
P3.3
COM0COM7
O
LCD common signal output.
3441
COM8COM11
I/O
4245
P4.0P4.3
COM12COM15
4649
P5.0P5.3
SEG0SEG39
O
LCD segment signal output.
51,
10066
SEG40SEG43
I/O
6562
P9.3P9.0
SEG44SEG47
6158
P8.3P8.0
SEG48SEG51
5754
P7.3P7.0
SEG52SEG55
5350
P6.3/K7P6.0/K4
K0K3
I/O
External interrupt. The triggering edge is
selectable.
1114
P0.0P0.3
K4K7
5053
P6.0P6.3
V
DD
Main power supply.
15
V
SS
Ground.
16
RESET
I
Reset signal.
22
V
LC1
V
LC5
LCD power supply.
106
X
in,
X
out
Crystal, Ceramic or RC oscillator pins for
system clock.
18, 17
XT
in,
XT
out
Crystal oscillator pins for subsystem clock.
20, 21
TEST
I
Test signal input. (must be connected to V
SS
)
19
NOTE: Pull-up resistors for all I/O ports are automatically disabled if they are configured to output mode.
S3C72F5/P72F5
PRODUCT OVERVIEW
Table 12. Overview of S3C72F5 Pin Data
Pin Names
Share Pins
I/O Type
Reset Value
Circuit Type
P0.1, P0.3
SO/K1, BUZ/K3
I/O
Input
E-1
P0.0, P0.2
SCK
/K0, SI/K2
I/O
Input
E-2
P1.0P1.3
INT0INT2, INT4
I
Input
A-3
P2.0P2.2
CLO, LCDCK, LCDSY
I/O
Input
E
P3.0P3.1
TCLO0, TCLO1
I/O
Input
E
P3.2P3.3
TCL0, TCL1
I/O
Input
E-1
P4.0P4.3
P5.0P5.3
COM8COM11
COM12COM15
I/O
Input
H-13
P6.0P6.3
SEG55/K4SEG52/K7
I/O
Input
H-16
P7.0P7.3
SEG51SEG48
I/O
Input
H-13
P8.0P8.3
P9.0P9.3
SEG47SEG44
SEG43SEG40
I/O
Input
H-13
COM0COM7
O
High
H-3
SEG0SEG39
O
High
H-15
V
DD
V
SS
RESET
I
B
V
LC1
V
LC5
X
in,
X
out
XT
in,
XT
out
TEST
I
PRODUCT OVERVIEW
S3C72F5/P72F5
18
PIN CIRCUIT DIAGRAMS
V
DD
P
-
CHANNEL
IN
N
-
CHANNEL
Figure 1-3. Pin Circuit Type A
P
-
CHANNEL
PULL-UP
RESISTOR
ENABLE
V
DD
PULL-UP
RESISTOR
SCHMITT TRIGGER
IN
Figure 1-4. Pin Circuit Type A-3
V
DD
PULL-UP
RESISTOR
SCHMITT TRIGGER
IN
Figure 1-5. Pin Circuit Type B
DATA
OUTPUT
DISABLE
OUT
V
DD
P
-
CHANNEL
N
-
CHANNEL
Figure 1-6. Pin Circuit Type C
S3C72F5/P72F5
PRODUCT OVERVIEW
V
DD
RESISTOR
ENABLE
N
-
CH
P
-
CH
V
DD
PULL-UP
RESISTOR
DATA
OUTPUT
DISABLE
CIRCUIT TYPE A
I/O
PNE
Figure 1-7. Pin Circuit Type E
V
DD
RESISTOR
ENABLE
N
-
CH
P
-
CH
V
DD
PULL-UP
RESISTOR
DATA
OUTPUT
DISABLE
SCHMITT TRIGGER
I/O
PNE
Figure 1-8. Pin Circuit Type E-1
PRODUCT OVERVIEW
S3C72F5/P72F5
110
V
DD
RESISTOR
ENABLE
N
-
CH
P
-
CH
V
DD
PULL-UP
RESISTOR
DATA
OUTPUT
DISABLE
SCHMITT TRIGGER
I/O
PNE
Figure 1-9. Pin Circuit Type E-2
S3C72F5/P72F5
PRODUCT OVERVIEW
OUT
VLC4
COM DATA
VLC5
VLC1
VDD
Figure 1-10. Pin Circuit Type H-3
OUT
VLC3
SEG DATA
VLC5
VLC2
VDD
Figure 1-11. Pin Circuit Type H-15
PRODUCT OVERVIEW
S3C72F5/P72F5
112
VDD
P-CH
PULL-UP
RESISTOR
RESISTOR
ENABLE
COM/SEG
OUTPUT
DISABLE
TYPE H-3
CIRCUIT TYPE A
DATA
I/O
TYPE C
Figure 1-12. Pin Circuit Type H-13
VDD
P-CH
PULL-UP
RESISTOR
RESISTOR
ENABLE
SEG
OUTPUT
DISABLE
TYPE H-15
SCHMITT TRIGGER
DATA
I/O
TYPE C
Figure 1-13. Pin Circuit Type H-16
S3C72F5/P72F5
ELECTRICAL DATA
141
14
ELECTRICAL DATA
OVERVIEW
In this section, information on S3C72F5 electrical characteristics is presented as tables and graphics. The
information is arranged in the following order:
Standard Electrical Characteristics
-- Absolute maximum ratings
-- D.C. electrical characteristics
-- Main system clock oscillator characteristics
-- Subsystem clock oscillator characteristics
-- I/O capacitance
-- A.C. electrical characteristics
-- Operating voltage range
Miscellaneous Timing Waveforms
-- A.C timing measurement point
-- Clock timing measurement at X
in
-- Clock timing measurement at XT
in
-- TCL timing
-- Input timing for
RESET
-- Input timing for external interrupts
-- Serial data transfer timing
Stop Mode Characteristics and Timing Waveforms
-- RAM data retention supply voltage in stop mode
-- Stop mode release timing when initiated by
RESET
-- Stop mode release timing when initiated by an interrupt request
ELECTRICAL DATA
S3C72F5/P72F5
142
Table 141. Absolute Maximum Ratings
(T
A
= 25
°
C)
Parameter
Symbol
Conditions
Rating
Units
Supply Voltage
V
DD
0.3 to + 6.5
V
Input Voltage
V
I
Ports 09
0.3 to V
DD
+ 0.3
V
Output Voltage
V
O
0.3 to V
DD
+ 0.3
V
Output Current High
I
O H
One I/O pin active
15
mA
All I/O pins active
35
Output Current Low
I
O L
One I/O pin active
+ 30 (Peak value)
mA
+ 15
(note)
Total for ports 0, 29
+ 100 (Peak value)
+ 60
(note)
Operating Temperature
T
A
40 to + 85
°
C
Storage Temperature
T
stg
65 to + 150
°
C
NOTE
:
The values for Output Current Low ( I
OL
) are calculated as Peak Value
×
Duty .
Table 142. D.C. Electrical Characteristics
(T
A
= 40
°
C to + 85
°
C, V
DD
= 1.8 V to 5.5 V)
Parameter
Symbol
Conditions
Min
Typ
Max
Units
Input High
Voltage
V
IH1
All input pins except those
specified below for V
IH2
V
IH3
0.7V
DD
V
DD
V
V
IH2
Ports 0, 1, 6, P3.2, P3.3, and
RESET
0.8V
DD
V
DD
V
IH3
X
in
, X
out
, and XT
in
V
DD
0.1
V
DD
Input Low
Voltage
V
IL1
All input pins except those
specified below for V
IL2
V
IL3
0.3V
DD
V
V
IL2
Ports 0, 1, 6, P3.2, P3.3, and
RESET
0.2V
DD
V
IL3
X
in
, X
out
, and XT
in
0.1
Output High
Voltage
V
OH
V
DD
= 4.5 V to 5.5 V
I
OH
= 1 mA
Ports 0, 29
V
DD
1.0
V
Output Low
Voltage
V
OL
V
DD
= 4.5 V to 5.5 V
I
OL
= 15 mA
Ports 0, 29
2.0
V
S3C72F5/P72F5
ELECTRICAL DATA
143
Table 142. D.C. Electrical Characteristics (Continued)
(T
A
= 40
°
C to + 85
°
C, V
DD
= 1.8 V to 5.5 V)
Parameter
Symbol
Conditions
Min
Typ
Max
Units
Input High
Leakage
Current
I
LIH1
V
I
= V
DD
All input pins except those
specified below for I
LIH2
3
µA
I
LIH2
V
I
= V
DD
X
in,
X
out,
XT
in,
and
RESET
20
Input Low
Leakage
I
LIL1
V
I
= 0 V
X
in,
X
out,
and XT
in
3
µA
Current
I
LIL2
V
I
= 0 V
X
in
, X
out,
and XT
in
20
Output High
Leakage
Current
I
LOH
V
O
= V
DD
All output pins
3
µA
Output Low
Leakage
Current
I
LOL
V
O
= 0 V
All output pins
3
µA
Pull-Up
Resistor
R
LI
V
I
= 0 V; V
DD
= 5 V
Port 09
25
47
100
k
V
DD
= 3 V
50
95
200
R
L2
V
I
= 0 V; V
DD
= 5 V,
RESET
100
220
400
V
DD
= 3 V
200
450
800
LCD Voltage
Dividing
Resistor
R
LCD
Ta = 25
°
C
25
55
80
k
|V
DD
-COM
i
|
Voltage Drop
(i = 015)
V
DC
15 µA per common pin
120
mV
|V
DD
-SEGx|
Voltage Drop
(x = 055)
V
DS
15 µA per segment pin
120
V
LC1
Output
Voltage
V
LC1
LCD clock = 0 Hz, V
LC5
= 0 V
0.8V
DD
-0.2
0.8V
DD
0.8V
DD
+0.2
V
V
LC2
Output
Voltage
V
LC2
0.6V
DD
-0.2
0.6V
DD
0.6V
DD
+0.2
V
LC3
Output
Voltage
V
LC3
0.4V
DD
-0.2
0.4V
DD
0.4V
DD
+0.2
V
LC4
Output
Voltage
V
LC4
0.2V
DD
-0.2
0.2V
DD
0.2V
DD
+0.2
ELECTRICAL DATA
S3C72F5/P72F5
144
Table 142. D.C. Electrical Characteristics (Concluded)
(T
A
= 40
°
C to + 85
°
C, V
DD
= 1.8 V to 5.5 V)
Parameter
Symbol
Conditions
Min
Typ
Max
Units
Supply
Current
I
DD1
(2)
V
DD
= 5 V
±
10%
Crystal oscillator
C1 = C2 = 22 pF
6.0 MHz
4.19 MHz
3.9
2.9
8.0
5.5
mA
V
DD
= 3 V ± 10%
6.0 MHz
4.19 MHz
1.8
1.3
4.0
3.0
I
DD2
(2)
Idle mode;
V
DD
= 5 V
±
10%
Crystal oscillator
C1 = C2 = 22 pF
6.0 MHz
4.19 MHz
1.3
1.2
2.5
1.8
V
DD
= 3 V ± 10%
6.0 MHz
4.19 MHz
0.5
0.44
1.5
1.0
I
DD3
(3)
V
DD
= 3 V ± 10%
32 kHz crystal oscillator
15.3
30
µA
I
DD4
(3)
Idle mode; V
DD
= 3 V ± 10%
32 kHz crystal oscillator
6.4
15
I
DD5
Stop mode;
V
DD
= 5 V ± 10%
SCMOD =
0000B
2.5
5
Stop mode;
V
DD
= 3 V ± 10%
XT = 0V
0.5
3
Stop mode;
V
DD
= 5 V ± 10%
SCMOD =
0100B
0.2
3
Stop mode;
V
DD
= 3 V ± 10%
0.1
2
NOTES:
1.
Data includes power consumption for subsystem clock oscillation.
2.
When the system clock control register, SCMOD, is set to 1001B, main system clock oscillation stops and the
subsystem clock is used.
3.
Currents in the following circuits are not included; on-chip pull-up resistors, internal LCD voltage dividing resistors,
output port drive currents.
S3C72F5/P72F5
ELECTRICAL DATA
145
Table 143. Main System Clock Oscillator Characteristics
(T
A
= 40
°
C + 85
°
C, V
DD
= 1.8 V to 5.5 V)
Oscillator
Clock
Configuration
Parameter
Test Condition
Min
Typ
Max
Units
Ceramic
Oscillator
Xin
Xout
C1
C2
Oscillation frequency
(1)
0.4
6.0
MHz
Stabilization time
(2)
Stabilization occurs
when V
DD
is equal
to the minimum
oscillator voltage
range; V
DD
= 3.0 V.
4
ms
Crystal
Oscillator
Xin
Xout
C1
C2
Oscillation frequency
(1)
0.4
6.0
MHz
Stabilization time
(2)
V
DD
= 3.0 V
10
ms
V
DD
= 2.0 V to 5.5 V
30
External
Clock
Xin
Xout
X
in
input frequency
(1)
0.4
6.0
MHz
X
in
input high and low
level width (t
XH
, t
XL
)
83.3
1250
ns
RC
Oscillator
Xin
Xout
R
Frequency
R = 20 k
,
V
DD
= 5 V
2
MHz
R = 39 k
,
V
DD
= 3 V
1
NOTES:
1.
Oscillation frequency and X
in
input frequency data are for oscillator characteristics only.
2.
Stabilization time is the interval required for oscillator stabilization after a power-on occurs, or when stop mode is
terminated.
ELECTRICAL DATA
S3C72F5/P72F5
146
Table 144. Recommended Oscillator Constants
(T
A
= 40
°
C + 85
°
C, V
DD
= 1.8 V to 5.5 V)
Manufacturer
Series
Number
(1)
Frequency Range
Load Cap (pF)
Oscillator Voltage
Range (V)
Remarks
C1
C2
MIN
MAX
TDK
FCR
M5
3.58 MHz6.0 MHz
33
33
2.0
5.5
Leaded Type
FCR
MC5
3.58 MHz6.0 MHz
(2)
(2)
2.0
5.5
On-chip C
Leaded Type
CCR
MC3
3.58 MHz6.0 MHz
(3)
(3)
2.0
5.5
On-chip C
SMD Type
NOTES:
1.
Please specify normal oscillator frequency.
2.
On-chip C: 30pF built in.
3.
On-chip C: 38pF built in.
S3C72F5/P72F5
ELECTRICAL DATA
147
Table 145. Subsystem Clock Oscillator Characteristics
(T
A
= 40
°
C + 85
°
C, V
DD
= 1.8 V to 5.5 V)
Oscillator
Clock
Configuration
Parameter
Test Condition
Min
Typ
Max
Units
Crystal
Oscillator
XTin
XTout
C1
C2
Oscillation
frequency
(1)
32
32.768
35
kHz
Stabilization time
(2)
V
DD
= 2.7 V to 5.5 V
1.0
2
s
V
DD
= 2.0 V to 5.5 V
10
External
Clock
XTin
XTout
XT
in
input
frequency
(1)
32
100
kHz
XT
in
input high and
low level width (t
XTL
,
t
XTH
)
5
15
µs
NOTES:
1.
Oscillation frequency and XT
in
input frequency data are for oscillator characteristics only.
2.
Stabilization time is the interval required for oscillating stabilization after a power-on occurs.
Table 146. Input/Output Capacitance
(T
A
= 25
°
C, V
DD
=
0 V )
Parameter
Symbol
Condition
Min
Typ
Max
Units
Input
Capacitance
C
IN
f = 1 MHz; Unmeasured pins
are returned to V
SS
15
pF
Output
Capacitance
C
OUT
15
pF
I/O Capacitance
C
IO
15
pF
ELECTRICAL DATA
S3C72F5/P72F5
148
Table 147. A.C. Electrical Characteristics
(T
A
= 40
°
C to + 85
°
C, V
DD
= 1.8 V to 5.5 V)
Parameter
Symbol
Conditions
Min
Typ
Max
Units
Instruction Cycle
Time
(note)
t
CY
V
DD
= 2.7 V to 5.5 V
0.67
64
µs
V
DD
= 2.0 V to 5.5 V
0.95
64
TCL0, TCL1 Input
Frequency
f
TI0
,
f
TI1
V
DD
= 2.7 V to 5.5 V
0
1.5
MHz
V
DD
= 2.0 V to 5.5 V
1
TCL0, TCL1 Input
High, Low Width
t
TIH0
,
t
TIL0
t
TIH1
, t
TIL1
V
DD
= 2.7 V to 5.5 V
0.48
µs
V
DD
= 2.0 V to 5.5 V
1.8
SCK
Cycle Time
t
KCY
V
DD
= 2.7 V to 5.5 V; Input
800
ns
Internal
SCK
source; Output
650
V
DD
= 2.0 V to 5.5 V; Input
3200
Internal
SCK
source; Output
3800
SCK
High, Low
Width
t
KH
, t
KL
V
DD
= 2.7 V to 5.5 V; Input
325
ns
Internal
SCK
source; Output
t
KCY
/2
50
V
DD
= 2.0 V to 5.5 V; Input
1600
Internal
SCK
source; Output
t
KCY
/
2
150
SI Setup Time to
SCK
High
t
SIK
V
DD
= 2.7 V to 5.5 V; Input
100
ns
V
DD
= 2.7 V to 5.5 V; Output
150
V
DD
= 2.0 V to 5.5 V; Input
150
V
DD
= 2.0 V to 5.5 V; Output
500
SI Hold Time to
SCK
High
t
KSI
V
DD
= 2.7 V to 5.5 V; Input
400
ns
V
DD
= 2.7 V to 5.5 V; Output
400
V
DD
= 2.0 V to 5.5 V; Input
600
V
DD
= 2.0 V to 5.5 V; Output
500
NOTE: Unless otherwise specified, Instruction Cycle Time condition values assume a main system clock ( fx ) source.
S3C72F5/P72F5
ELECTRICAL DATA
149
Table 147. A.C. Electrical Characteristics (Continued)
(T
A
= 40
_
C to + 85
_
C, V
DD
= 1.8 V to 5.5 V)
Parameter
Symbol
Conditions
Min
Typ
Max
Units
Output Delay for
SCK
to SO
t
KSO
V
DD
= 2.7 V to 5.5 V; Input
300
ns
V
DD
= 2.7 V to 5.5 V; Output
250
V
DD
= 2.0 V to 5.5 V; Input
1000
V
DD
= 2.0 V to 5.5 V; Output
1000
Interrupt Input
High, Low Width
t
INTH
,
t
INTL
INT0, INT1, INT2, INT4,
K0K7
10
µs
RESET
Input Low
Width
t
RSL
Input
10
µs
NOTE: Minimum value for INT0 is based on a clock of 2t
CY
or 128 / fx as assigned by the IMOD0 register setting.
CPU CLOCK = 1/n x oscillator frequency (n = 4, 8 or 64)
1 2 3 4 5 6 7
SUPPLY VOLTAGE (V)
750 kHz
15.6 kHz
CPU CLOCK
1.5 MHz
4.2 MHz
Main Oscillator Frequency
(Divided by 4)
6 MHz
1.8 V
1.05 MHz
3 MHz
Figure 141. Standard Operating Voltage Range
ELECTRICAL DATA
S3C72F5/P72F5
1410
Table 148. RAM Data Retention Supply Voltage in Stop Mode
(T
A
= 40
°
C to + 85
°
C)
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
Data retention supply voltage
V
DDDR
1.8
5.5
V
Data retention supply current
I
DDDR
V
DDDR
= 1.8 V
0.1
10
µA
Release signal set time
t
SREL
0
µs
Oscillator stabilization wait
time
(1)
t
WAIT
Released by
RESET
2
17
/ fx
ms
Released by interrupt
(2)
NOTES:
1.
During oscillator stabilization wait time, all CPU operations must be stopped to avoid instability during oscillator
start-up.
2.
Use the basic timer mode register (BMOD) interval timer to delay execution of CPU instructions during the wait time.
S3C72F5/P72F5
ELECTRICAL DATA
1411
TIMING WAVEFORMS
t
WAIT
V
DD
RESET
EXECUTION OF
STOP INSTRUCTION
V
DDDR
DATA RETENTION MODE
STOP MODE
INTERNAL
RESET
OPERATION
IDLE MODE
NORMAL MODE
t
SREL
Figure 142. Stop Mode Release Timing When Initiated by
RESET
RESET
V
DD
EXECUTION OF
STOP INSTRUCTION
V
DDDR
DATA RETENTION MODE
STOP MODE
t
WAIT
t
SREL
IDLE MODE
NORMAL MODE
POWER-DOWN MODE TERMINATING SIGNAL
(INTERRUPT REQUEST)
Figure 143. Stop Mode Release Timing When Initiated by Interrupt Request
ELECTRICAL DATA
S3C72F5/P72F5
1412
0.8
V
DD
0.2
V
DD
0.8
V
DD
0.2
V
DD
MEASUREMENT
POINTS
Figure 144. A.C. Timing Measurement Points (Except for X
in
and XT
in
)
Xin
t
XL
t
XH
1 / f
VDD -0.1 V
0.1 V
x
Figure 145. Clock Timing Measurement at X
in
XTin
t
XTL
t
XTH
1 / f
VDD - 0.1 V
0.1 V
xt
Figure 146. Clock Timing Measurement at XT
in
S3C72F5/P72F5
ELECTRICAL DATA
1413
TCL0
t
TIL
t
TIH
1 / f TI
0.2 V
DD
0.8 V
DD
Figure 147. TCL Timing
RESET
tRSL
0.2 VDD
Figure 148. Input Timing for
RESET
RESET
Signal
INT0, 1, 2, 4 K0 to K7
t
INTL
tINTH
0.8 VDD
0.2 VDD
Figure 149. Input Timing for External Interrupts and Quasi-Interrupts
ELECTRICAL DATA
S3C72F5/P72F5
1414
SCK
tKL
tKH
tKCY
0.8 VDD
INPUT DATA
OUTPUT DATA
0.2 VDD
0.8 VDD
0.2 VDD
SI
SO
tKSO
tSIK
tKSI
Figure 1410. Serial Data Transfer Timing
S3C72F5/P72F5
ELECTRICAL DATA
1415
NOTES
ELECTRICAL DATA
S3C72F5/P72F5
1416
CHARACTERISTIC CURVES
NOTE
The characteristic values shown in the following graphs are based on actual test measurements.
They do not, however, represent guaranteed operating values.
5.0
4.5
4.0
3.5
I DD1
, I
DD2
(mA)
(TA = 25
°
C, fx = 4.2 MHz)
3.0
2.5
2.0
1.5
1.0
0.5
2.7
4.0
4.5
6.0
VDD (V)
0
I
DD1
, CPU Clock = fx/4
I
DD1
, CPU Clock = fx/64
I
DD2
Figure 1411. I
DD1
, I
DD2
VS.
V
DD
S3C72F5/P72F5
ELECTRICAL DATA
1417
5
0
I DD3, 4, 5
(µA)
2.5
VDD (V)
3.0
3.5
4.0
(TA = 25
°
C, fx = 32.768 kHz)
10
15
20
25
30
35
40
45
4.5
5.0
5.5
6.0
6.5
IDD3
2.0
50
IDD4
IDD5
Figure 1412. I
DD3
, I
DD4
, I
DD5
VS.
V
DD
ELECTRICAL DATA
S3C72F5/P72F5
1418
0.5
0
I D
D
1
(
m
A
)
0.5
Main System Clock Frequency (MHz)
1.0
1.5
2.0
(TA = 25
°
C, CPU CLOCK = fx/4)
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
2.5
3.0
3.5
4.0
4.5
VDD = 6.0 V
VDD = 4.5 V
Figure 1413. I
DD1
VS.
Main System Clock Frequency
0.2
0
I D
D
2
(
m
A
)
0.5
Main System Clock Frequency (MHz)
1.0
1.5
2.0
(TA = 25
°
C)
0.4
0.6
0.8
1.0
1.2
1.4
1.6
2.5
3.0
3.5
4.0
4.5
VDD = 6.0 V
VDD = 4.5 V
Figure 1414. I
DD2
VS.
Main System Clock Frequency
S3C72F5/P72F5
ELECTRICAL DATA
1419
2.5
0
I OH
(mA)
0.5
VOH (V)
1.0
1.5
2.0
(TA = 25
°
C, Ports 0, 2, 3, 4, 5, 6, 7)
5.0
7.5
10.0
12.5
15.0
17.5
20.0
22.5
25.0
2.5
3.0
3.5
4.0
4.5
5.0
VDD = 4.5 V
5.5
6.0
VDD = 6.0 V
Figure 1415. I
OH
VS.
V
OH
(P0, 2, 3, 4, 5, 6, 7)
ELECTRICAL DATA
S3C72F5/P72F5
1420
2.5
0
I OH
(mA)
0.5
VOH (V)
1.0
1.5
2.0
(TA = 25
°
C, Ports 8, 9)
5.0
7.5
10.0
12.5
15.0
17.5
20.0
22.5
25.0
2.5
3.0
3.5
4.0
4.5
5.0
VDD = 4.5 V
5.5
6.0
VDD = 6.0 V
Figure 1416. I
OH
VS.
V
OH
(P8, 9)
S3C72F5/P72F5
ELECTRICAL DATA
1421
5.0
0
I OL
(mA)
0.5
VOL (V)
1.0
1.5
2.0
(TA = 25
°
C, Ports 0, 2, 3, 4, 5, 6, 7)
10.0
15.0
20.0
25.0
30.0
35.0
40.0
45.0
50.0
2.5
3.0
3.5
4.0
4.5
5.0
55.0
5.5
6.0
VDD = 6.0 V
VDD = 4.5 V
Figure 1417. I
OL
VS.
V
OL
(P0, 2, 3, 4, 5, 6, 7)
ELECTRICAL DATA
S3C72F5/P72F5
1422
5.0
0
I OL
(mA)
0.5
VOL (V)
1.0
1.5
2.0
(TA = 25
°
C, Ports 8, 9)
10.0
15.0
20.0
25.0
30.0
35.0
40.0
45.0
50.0
2.5
3.0
3.5
4.0
4.5
5.0
55.0
5.5
6.0
VDD = 6.0 V
VDD = 4.5 V
Figure 1418. I
OL
VS.
V
OL
(P8, 9)
S3C72F5/P72F5
MECHANICAL DATA
151
15
MECHANICAL DATA
OVERVIEW
This section contains the following information about the device package:
--
Package dimensions in millimetersD
--
Pad diagram
--
Pad/pin coordinate data table
MECHANICAL DATA
S3C72F5/P72F5
15-2
100 QFP
(Top View)
C
0.65 TYP
0.30 ± 0.1
A
20.00 TYP
14.00 TYP
B
E
0.15
+ 0.1
0.05
D
Item
Package
A
B
C
D
E
100-QFP-1420A
100-QFP-1420C
25.00 ± 0.3
23.20 ± 0.3
19.00 ± 0.3
17.20 ± 0.3
2.45 MAX
3.00 MAX
1.20 ± 0.2
0.80 ± 0.2
0.15
+ 0.1
0.05
0.15 ± 0.1
NOTE: Typical dimensions are in millimeters.
Figure 151. 100-QFP Package Dimensions
S3C72F5/P72F5
S3P72F5 OTP
161
16
S3P72F5 OTP
OVERVIEW
The S3P72F5 single-chip CMOS microcontroller is the OTP (One Time Programmable)
version of the S3C72F5
microcontroller. It has an on-chip OTP ROM instead of masked ROM. The EPROM is accessed by serial data
format.
The S3P72F5 is fully compatible with the S3C72F5, both in function and in pin configuration. Because of its
simple programming requirements, the S3P72F5 is ideal for use as an evaluation chip for the S3C72F5.
S3P72F5 OTP
S3C72F5/P72F5
162
SEG25
SEG26
SEG27
SEG28
SEG29
SEG30
SEG31
SEG32
SEG33
SEG34
SEG35
SEG36
SEG37
SEG38
SEG39
P9.3/SEG40
P9.2/SEG41
P9.1/SEG42
P9.0/SEG43
P8.3/SEG44
P8.2/SEG45
P8.1/SEG46
P8.0/SEG47
P7.3/SEG48
P7.2/SEG49
P7.1/SEG50
P7.0/SEG51
P6.3/SEG52/K7
P6.2/SEG53/K6
P6.1/SEG54/K5
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
SEG4
SEG3
SEG2
SEG1
SEG0
VLC5
VLC4
VLC3
VLC2
VLC1
P0.0/
SCK
/K0
P0.1/SO/K1
SDAT/P0.2/SI/K2
SCLK /P0.3/BUZ/K3
VDD /VDD
VSS/VSS
Xout
Xin
VPP/TEST
XTin
XTout
RESET
RESET /RESET
P1.0/INT0
P1.1/INT1
P1.2/INT2
P1.3/INT4
P2.0/CLO
P2.1/LCDCK
P2.2/LCDSY
P3.0/TCLO0
S3P72F5
(100-QFP-1420C)
SEG5
SEG6
SEG7
SEG8
SEG9
SEG10
SEG11
SEG12
SEG13
SEG14
SEG15
SEG16
SEG17
SEG18
SEG19
SEG20
SEG21
SEG22
SEG23
SEG24
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
P3.1/TCLO1
P3.2/TCL0
P3.3/TCL1
COM0
COM1
COM2
COM3
COM4
COM5
COM6
COM7
P4.0/COM8
P4.1/COM9
P4.2/COM10
P4.3/COM11
P5.0/COM12
P5.1/COM13
P5.2/COM14
P5.3/COM15
P6.0/SEG55/K4
NOTE: The bolds indicate an OTP pin name.
Figure 161. S3P72F5 Pin Assignments (100-QFP Package)
S3C72F5/P72F5
S3P72F5 OTP
163
Table 161. Descriptions of Pins Used to Read/Write the EPROM
Main Chip
During Programming
Pin Name
Pin Name
Pin No.
I/O
Function
P0.2
SDAT
13
I/O
Serial data pin. Output port when reading and
input port when writing. Can be assigned as a
Input / push-pull output port.
P0.3
SCLK
14
I/O
Serial clock pin. Input only pin.
TEST
V
PP
(TEST)
19
I
Power supply pin for EPROM cell writing
(indicates that OTP enters into the writing
mode). When 12.5 V is applied, OTP is in
writing mode and when 5 V is applied, OTP is in
reading mode. (Option)
RESET
RESET
22
I
Chip initialization
V
DD
/ V
SS
V
DD
/ V
SS
15/16
I
Logic power supply pin. VDD should be tied to
+5 V during programming.
Table 162. Comparison of S3P72F5 and S3C72F5 Features
Characteristic
S3P72F5
S3C72F5
Program Memory
16 Kbyte EPROM
16 Kbyte mask ROM
Operating Voltage (V
DD
)
1.8 V to 5.5 V
1.8 V to 5.5 V
OTP Programming Mode
V
DD
= 5 V, V
PP
(TEST)=12.5V
Pin Configuration
100 QFP
100 QFP
EPROM Programmability
User Program 1 time
Programmed at the factory
OPERATING MODE CHARACTERISTICS
When 12.5 V is supplied to the VPP(TEST) pin of the S3P72F5, the EPROM programming mode is entered. The
operating mode (read, write, or read protection) is selected according to the input signals to the pins listed in
Table 163 below.
Table 163. Operating Mode Selection Criteria
VDD
Vpp
(TEST)
REG/MEM
Address
(A15-A0)
R/W
Mode
5 V
5 V
0
0000H
1
EPROM read
12.5 V
0
0000H
0
EPROM program
12.5 V
0
0000H
1
EPROM verify
12.5 V
1
0E3FH
0
EPROM read protection
NOTE: "0" means Low level; "1" means High level.
S3P72F5 OTP
S3C72F5/P72F5
164
Table 164. D.C. Electrical Characteristics
(T
A
= 40
°
C to + 85
°
C, V
DD
= 1.8 V to 5.5 V)
Parameter
Symbol
Conditions
Min
Typ
Max
Units
Supply
Current
I
DD1
(2)
V
DD
= 5 V
±
10%
Crystal oscillator
C1 = C2 = 22 pF
6.0 MHz
4.19 MHz
3.9
2.9
8.0
5.5
mA
V
DD
= 3 V ± 10%
6.0 MHz
4.19 MHz
1.8
1.3
4.0
3.0
I
DD2
(2)
Idle mode;
V
DD
= 5 V
±
10%
Crystal oscillator
C1 = C2 = 22 pF
6.0 MHz
4.19 MHz
1.3
1.2
2.5
1.8
V
DD
= 3 V ± 10%
6.0 MHz
4.19 MHz
0.5
0.44
1.5
1.0
I
DD3
(3)
V
DD
= 3 V ± 10%
32 kHz crystal oscillator
15.3
30
µA
I
DD4
(3)
Idle mode; V
DD
= 3 V ± 10%
32 kHz crystal oscillator
6.4
15
I
DD5
Stop mode;
V
DD
= 5 V ± 10%
SCMOD =
0000B
2.5
5
Stop mode;
V
DD
= 3 V ± 10%
XT = 0V
0.5
3
Stop mode;
V
DD
= 5 V ± 10%
SCMOD =
0100B
0.2
3
Stop mode;
V
DD
= 3 V ± 10%
0.1
2
NOTES:
1.
Data includes power consumption for subsystem clock oscillation.
2.
When the system clock control register, SCMOD, is set to 1001B, main system clock oscillation stops and the
subsystem clock is used.
3.
Currents in the following circuits are not included; on-chip pull-up resistors, internal LCD voltage dividing resistors,
output port drive currents.
S3C72F5/P72F5
S3P72F5 OTP
165
CPU CLOCK = 1/n x oscillator frequency (n = 4, 8 or 64)
1 2 3 4 5 6 7
SUPPLY VOLTAGE (V)
750 kHz
15.6 kHz
CPU CLOCK
1.5 MHz
3 MHz
Main Oscillator Frequency
(Divided by 4)
6 MHz
1.8 V
1.05 MHz
4.2 MHz
Figure 162. Standard Operating Voltage Range
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