SGRAM MODULE

M965G5115AP(Q)0 / M966G5115AP(Q)0

The Samsung M965(6)G5115AP(Q)0 is a 512K bit x 64 Syn-

chronous Graphic RAM high density memory module. The

Samsung M965(6)G5115AP(Q)0 consists of two CMOS 512K

x 32 bit Synchronous Graphic RAMs in 100pin QFP packages

mounted on a 144pin glass-epoxy substrate. Five 0.1uF

decoupling capacitors are mounted on the printed circuit board

for each Synchronous GRAM. The M965(6)G5115AP(Q)0 is a

Small Outline Dual In-line Memory Module and is intended for

mounting into 144-pin edge connector sockets.

Synchronous design allows precise cycle control with the use

of system clock. I/O transactions are possible on every clock

cycle. Range of operating frequencies, programmable laten-

cies and burst lengths allows the same device to be useful for a

variety of high bandwidth, high performance memory system

applications.

FEATURE

GENERAL DESCRIPTION

M965G5115AP(Q)0 / M966G5115AP(Q)0 SGRAM SODIMM

512Kx64 SGRAM SODIMM based on 512Kx32, 2K Refresh, 3.3V Synchronous Graphic RAMs

SAMSUNG ELECTRONICS CO. Ltd. reserves the right to change products and specifications without notice.

Performance range

* M965(6)G5115AP0 : based on PQFP Component
M965(6)G5115AQ0 : based on TQFP Component

ˇ Burst Mode Operation
ˇ BLOCK-WRITE and Write-per-bit capability
ˇ Independent byte operation via DQM0 ~ 7
ˇ Auto & Self Refresh Capability (2048 cycles / 32ms)
ˇ LVTTL compatible inputs and outputs
ˇ Single 3.3V

0.3V power supply

ˇ MRS cycle with address key programs.
CAS Latency (2, 3)
Burst Length (1, 2, 4, 8 & Full page)
Data Scramble (Sequential & Interleave)
ˇ Optional Serial PD with EEPROM (M966G5115A)
ˇ Resistor Strapping Options for speed and CAS Latency
ˇ PCB : Height(1000mil), single sided components

Part NO.

Max. Freq. (t

)

M965(6)G5115AP(Q)0-C50

200MHz (5ns)

M965(6)G5115AP(Q)0-C60

166MHz (6ns)

M965(6)G5115AP(Q)0-C70

143MHz (7ns)

M965(6)G5115AP(Q)0-C80

125MHz (8ns)

PIN NAMES

These pins are not used in this module.

These pins should be NC in the system

which does not support SPD.

Pin Name

Function

A0 ~ A9

Address Input(multiplexed)

BA(A10)

Bank Select Address

DQ0 ~ 63

Data Input / Output

CLK0, *CLK1 Clock Input

CKE

Clock Enable Input

CS0, *CS1

Chip Select Input

RAS

Row Address Strobe

CAS

Column Address Strobe

Write Enable

DSF

Define Special Function

DQM0 ~ 7

DQM

Power Supply (3.3V)

Ground

**SDA

Serial Address Data I/O

**SBA

EEPROM Device Address

**SCL

Serial Clock

RSVD

Reserved

RFU

Reserved for future use

No Connection

PIN CONFIGURATIONS (Front Side / Back Side)

Pin

Front

Pin

Back

Pin

Front

Pin

Back

Pin

Front

Pin

Back

1
3
5
7
9

11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49

DQ63
DQ61
DQ59
DQ57

DQ55
DQ53
DQ51
DQ49

DQM7
DQM5

DQ47
DQ45
DQ43
DQ41

DQ39
DQ37
DQ35
DQ33

RSVD

2
4
6
8

10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50

DQ62
DQ60
DQ58
DQ56

DQ54
DQ52
DQ50
DQ48

DQM6
DQM4

DQ46
DQ44
DQ42
DQ40

DQ38
DQ36
DQ34
DQ32

RSVD

Voltage Key

95
97
99

101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143

DQ31
DQ29
DQ27
DQ25

DQ23
DQ21
DQ19
DQ17

DQM3
DQM1

DQ15
DQ13
DQ11

DQ9

DQ7
DQ5
DQ3
DQ1

**SDA

96
98

100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144

DQ30
DQ28
DQ26
DQ24

DQ22
DQ20
DQ18
DQ16

DQM2
DQM0

DQ14
DQ12
DQ10

DQ8

DQ6
DQ4
DQ2
DQ0

**SCL

51
53
55
57
59
61
63
65
67
69
71
73
75
77
79

81
83
85
87
89
91
93

RSVD
RSVD

DSF
RFU
RFU

CS1

RAS

CLK1

RSVD
RSVD

(A11)

BA(A10)

A5
A3
A1

52
54
56
58
60
62
64
66
68
70
72
74
76
78
80

82
84
86
88
90
92
94

RSVD
RSVD

RFU
RFU

**SBA

CS0

CAS
CKE

CLK0

RSVD

A9/AP

A4
A2
A0

SGRAM MODULE

M965G5115AP(Q)0 / M966G5115AP(Q)0

PIN CONFIGURATION DESCRIPTION

Pin

Name

Input Function

CLK

System Clock

Active on the positive going edge to sample all inputs.

Chip Select

Disables or enables device operation by masking or enabling all inputs except
CLK, CKE and DQM

CKE

Clock Enable

Masks system clock to freeze operation from the next clock cycle.
CKE should be enabled at least one clock + t

prior to new command.

Disable input buffers for power down in standby.

A0 ~ A9

Address

Row / column addresses are multiplexed on the same pins.
Row address : RA0 ~ RA9, column address : CA0 ~ CA7

BA(A10)

Bank Select Address

Selects bank to be activated during row address latch time.
Selects bank for read/write during column address latch time.

RAS

Row Address Strobe

Latches row addresses on the positive going edge of the CLK with RAS low.
Enables row access & precharge.

CAS

Column Address Strobe

Latches column addresses on the positive going edge of the CLK with CAS low.
Enables column access.

Write Enable

Enables write operation and row precharge.
Latches data in starting from CAS, WE active.

DQM0 ~ 7

Data Input/Output Mask

Makes data output Hi-Z, t

SHZ

after the clock and masks the output.

Blocks data input when DQM active. (Byte masking)

DQ0 ~ 63

Data Input/Output

Data inputs/outputs are multiplexed on the same pins.

DSF

Define Special Function

Enables write per bit, block write and special mode register set.

Power Supply/Ground

Power and ground for the input buffers and the core logic.

Three resistor straps are used to indicate the synchronous clock frequency (period) and memory timing.Timing information
for each clock frequency is indicated in the section titled AC CHARATERISTICS.

Clock Frequency and Memory Timing

CAS Latency

Cycle Time

DQ30

DQ29

8ns

7ns

6ns

5ns

CAS Latency

DQ31

2 and 3

RESISTOR STRAPPING OPTIONS

SGRAM MODULE

M965G5115AP(Q)0 / M966G5115AP(Q)0

DQ0

DQ7

FUNCTIONAL BLOCK DIAGRAM

Vss

Five 0.1uF Capacitors
per SGRAM device

To all SGRAMs

CKE

DSF

RAS

CAS

U0 to U1

CLK0

CS0

DQ0

DQ7

DQM0

DQ8

DQ15

DQ8

DQ15

DQM1

DQ16

DQ23

DQ16

DQ23

DQM2

DQ24

DQ31

DQ24

DQ31

DQM3

DQ32

DQ39

DQ0

DQ7

DQM0

DQM4

DQ40

DQ47

DQ8

DQ15

DQM1

DQM5

DQ48

DQ55

DQ16

DQ23

DQM2

DQM6

DQ56

DQ63

DQ24

DQ31

DQM3

DQM7

BA(A10)

A(9:0)

U0 to U1

U0, U1

Serial PD

SDA

SCL

SBA

* Serial PD is optional

SGRAM MODULE

M965G5115AP(Q)0 / M966G5115AP(Q)0

ABSOLUTE MAXIMUM RATINGS

(Voltages referenced to

)

Parameter

Symbol

Value

Unit

Voltage on any pin relative to Vss V

, V

OUT

-1.0 ~ 4.6 V

Voltage on V

supply relative to Vss V

-1.0 ~ 4.6 V

Storage temperature T

STG

-55 ~ +150

Power dissipation P

2 W

Short circuit current I

50 mA

Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded.
Functional operation should be restricted to recommended operating condition.
Exposure to higher than recommended voltage for extended periods of time could affect device reliability.

DC OPERATING CONDITIONS

Recommended operating conditions (Voltage referenced to V

= 0V)

Parameter

Symbol

Min

Typ

Max

Unit

Note

Supply voltage V

3.0 3.3 3.6 V 4

Input high voltage V

2.0 3.0 V

+0.3 V

Input low voltage V

-0.3 0 0.8 V Note 1

Output high voltage V

2.4 - - V I

= -2mA

Output low voltage V

- - 0.4 V I

= 2mA

Input leakage current I

-20 - 20 uA Note 2

Output leakage current I

-10 - 10 uA Note 3

Output loading conditon See Figure 1

1. V

(min.) = -1.5V AC (pulse width

5ns)

2. Any input 0V

+ 0.3V, all other pins are not under test = 0V.

3. Dout is disabled, 0V

OUT

4. The VDD condition of M965(6)G5115AP(Q)0-C50/60 is 3.135V~3.6V.

Note :

CAPACITANCE

= 3.3V, T

= 25

C, f = 1MHz)

Parameter

Symbol

Min

Max

Unit

Input capacitance (A0 ~ A9, BA)

Input capacitance (RAS, CAS, WE, CKE, DSF)

Input capacitance (CLK0)

Input capacitance (CS0)

Input capacitance (DQM0 ~ DQM7)

Data input/output capacitance (DQ0 ~ DQ63)

IN1

IN2

IN3

IN4

IN5

OUT

Note :

SGRAM MODULE

M965G5115AP(Q)0 / M966G5115AP(Q)0

DC CHARACTERISTICS

Note : 1. Unless otherwise notes, Input level is CMOS(V

DDQ

SSQ

) in LVTTL.

2. Measured with outputs open. Address are changed only one time during tcc(min).

3. Refresh period is 32ms. Address are changed only one time during tcc(min).

(Recommended operating condition unless otherwise noted, T

= 0 to 70

C, V

IH(min)

IL(max)

=2.0V/0.8V)

Parameter

Symbol

Test Condition

CAS

Latency

Speed

Unit Note

-50

-60

-70

-80

Operating Current
(One Bank Active)

CC1

Burst Length =1
t

(min), t

(min), I

= 0mA

400

360

320

300

Precharge Standby Current
in power-down mode

CC2

CKE

(max), t

= 15ns

CC2

CKE

CLK

(max), t

Precharge Standby Current
in non power-down mode

CC2

CKE

(min), CS

(min), t

= 15ns

Input signals are changed one time during 30ns

CC2

CKE

(min), CLK

(max), t

Input signals are stable

Active Standby Current
in power-down mode

CC3

CKE

(max), t

= 15ns

CC3

CKE

(max), t

Active Standby Current
in non power-down mode
(One Bank Active)

CC3

CKE

(min), CS

(min), t

= 15ns

Input signals are changed one time during 30ns

100

CC3

CKE

(min), CLK

(max), t

Input signals are stable

Operating Current
(Burst Mode)

CC4

= 0 mA, Page Burst

All bank Activated, t

CCD

= t

CCD

(min)

540

520

460

400

320

Refresh Current

CC5

(min)

400

360

320

300

Self Refresh Current

CC6

CKE

0.2V

Operating Current
(One Bank Block Write)

CC7

(min), I

=0mA, t

BWC

(min)

460

400

340

300

Part Number M96xG5115Ax0