DRAM MODULE

M53230810CW0/CB0

M53230800CW0/CB0

M53230800CW0/CB0 & M53230810CW0/CB0 EDO Mode
8M x 32 DRAM SIMM using 4Mx4, 4K/2K Refresh, 5V

The Samsung M5323080(1)0C is a 8Mx32bits Dynamic RAM

high density memory module. The Samsung M5323080(1)0C

consists of sixteen CMOS 4Mx4bits DRAMs in 24-pin SOJ

package mounted on a 72-pin glass-epoxy substrate. A 0.1 or

0.22uF decoupling capacitor is mounted on the printed circuit

board for each DRAM. The M5323080(1)0C is a Single In-line

Memory Module with edge connections and is intended for

mounting into 72 pin edge connector sockets.

ˇ Part Identification

- M53230800CW0-C(4096 cycles/64ms Ref, SOJ, Solder)

- M53230800CB0-C(4096 cycles/64ms Ref, SOJ, Gold)

- M53230810CW0-C(2048 cycles/32ms Ref, SOJ, Solder)

- M53230810CB0-C(2048 cycles/32ms Ref, SOJ, Gold)

ˇ Extended Data Out

ˇ CAS-before-RAS refresh capability

ˇ RAS-only and Hidden refresh capability

ˇ TTL compatible inputs and outputs

ˇ Single +5V

10% power supply

ˇ 1st Gen. JEDEC standard PDPin & pinout

ˇ PCB : Height(1000mil), double sided component

GENERAL DESCRIPTION

FEATURES

PERFORMANCE RANGE

Speed

RAC

CAC

HPC

-50

50ns

13ns

90ns

25ns

-60

60ns

15ns

110ns

30ns

PIN NAMES

Pin Name

Function

A0 - A11

Address Inputs(4K Ref)

A0 - A10

Address Inputs(2K Ref)

DQ0 - DQ31

Data In/Out

Read/Write Enable

RAS0, RAS1

Row Address Strobe

CAS0 - CAS3

Column Address Strobe

PD1 -PD4

Presence Detect

Vcc

Power(+5V)

Vss

Ground

No Connection

PRESENCE DETECT PINS (Optional)

* Pin connection changing available

Pin

50NS

60NS

PD1

PD2

PD3

PD4

Vss

PIN CONFIGURATIONS

Pin

1
2
3
4
5
6
7
8
9

10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36

Symbol

DQ0

DQ16

DQ1

DQ17

DQ2

DQ18

DQ3

DQ19

Vcc

A0
A1
A2
A3
A4
A5
A6

A10

DQ4

DQ20

DQ5

DQ21

DQ6

DQ22

DQ7

DQ23

A11

Vcc

A8
A9

RAS1
RAS0

NC
NC

Pin

37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72

Symbol

NC
NC

Vss

CAS0
CAS2
CAS3
CAS1
RAS0
RAS1

DQ8

DQ24

DQ9

DQ25
DQ10
DQ26
DQ11
DQ27
DQ12
DQ28

Vcc

DQ29
DQ13
DQ30
DQ14
DQ31
DQ15

PD1
PD2
PD3
PD4

Vss

* NOTE : A11 is used for only M53230800CW0/CB0 (4K ref.)

SAMSUNG ELECTRONICS CO., LTD. reserves the right to
change products and specifications without notice.

DRAM MODULE

M53230810CW0/CB0

M53230800CW0/CB0

FUNCTIONAL BLOCK DIAGRAM

DQ1

DQ2
DQ3
DQ4

CAS

RAS

A0-

Vcc

Vss

.1 or .22uF Capacitor
for each DRAM

To all DRAMs

A11(A10)

DQ1
DQ2
DQ3
DQ4

CAS

RAS

A0-

A11(A10)

DQ1

DQ2
DQ3
DQ4

CAS

RAS

A0-

A11(A10)

DQ1
DQ2
DQ3
DQ4

CAS

RAS

A0-

A11(A10)

A0-A11(A10)

DQ1

DQ2
DQ3
DQ4

CAS

RAS

A0-

A11(A10)

DQ1
DQ2
DQ3
DQ4

CAS

RAS

A0-

A11(A10)

DQ1

DQ2
DQ3
DQ4

CAS

RAS

A0-

A11(A10)

DQ1
DQ2
DQ3
DQ4

CAS

RAS

A0-

A11(A10)

DQ1

DQ2
DQ3
DQ4

CAS

RAS

A0-

A11(A10)

DQ1
DQ2
DQ3
DQ4

CAS

RAS

A0-

A11(A10)

DQ1

DQ2
DQ3
DQ4

CAS

RAS

A0-

A11(A10)

DQ1
DQ2
DQ3
DQ4

CAS

RAS

A0-

A11(A10)

DQ1

DQ2
DQ3
DQ4

CAS

RAS

A0-

A11(A10)

DQ1
DQ2
DQ3
DQ4

CAS

RAS

A0-

A11(A10)

DQ1

DQ2
DQ3
DQ4

CAS

RAS

A0-

A11(A10)

DQ1
DQ2
DQ3
DQ4

CAS

RAS

A0-

A11(A10)

DQ0-DQ3

DQ4-DQ7

DQ8-DQ11

DQ12-DQ15

DQ16-DQ19

DQ20-DQ23

DQ24-DQ27

DQ28-DQ31

RAS1

CAS0

RAS0

CAS1

CAS2

CAS3

U10

U11

U12

U13

U14

U15

DRAM MODULE

M53230810CW0/CB0

M53230800CW0/CB0

CC1

, I

CC3

, I

CC4

and I

CC6

are dependent on output loading and cycle rates. Specified values are obtained with the output open.

is specified as an average current. In I

CC1

and I

CC3

, address can be changed maximum once while RAS=V

. In I

CC4

address can be changed maximum once within one EDO mode cycle,

HPC

* NOTE :

ABSOLUTE MAXIMUM RATINGS *

* Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to

the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for intended
periods may affect device reliability.

Item

Symbol

Rating

Unit

Voltage on any pin relative to V

Voltage on V

supply relative to V

Storage Temperature
Power Dissipation
Short Circuit Output Current

, V

OUT

stg

-1 to +7.0
-1 to +7.0

-55 to +150

16
50

V
V

RECOMMENDED OPERATING CONDITIONS

(Voltage referenced to V

, T

= 0 to 70

*1 : V

+2.0V/20ns, Pulse width is measured at V

*2 : -2.0V/20ns, Pulse width is measured at V

Item

Symbol

Min

Typ

Max

Unit

Supply Voltage
Ground
Input High Voltage
Input Low Voltage

4.5

2.4

-1.0

5.0

-
-

5.5

0.8

V
V
V
V

DC AND OPERATING CHARACTERISTICS

(Recommended operating conditions unless otherwise noted)

CC1

CC2

CC3

CC4

CC5

CC6

I(L)

O(L)

Symbol

Speed

M53230800CW0/CB0

M53230810CW0/CB0

Unit

Min

Max

Min

Max

CC1

-50
-60

-
-

736
656

-
-

896
816

mA
mA

CC2

Don

t care

CC3

-50
-60

-
-

736
656

-
-

896
816

mA
mA

CC4

-50
-60

-
-

656
576

-
-

736
656

mA
mA

CC5

Don

t care

CC6

-50
-60

-
-

736
656

-
-

896
816

mA
mA

I(L)

O(L)

Don

t care

-80
-10

80
10

-80
-10

80
10

uA
uA

Don

t care

2.4

0.4

2.4

0.4

V
V

: Operating Current * (RAS, CAS, Address cycling @

=min)

: Standby Current (RAS=CAS=W=V

)

: RAS Only Refresh Current * (CAS=V

, RAS cycling @

=min)

: EDO Mode Current * (RAS=V

, CAS Address cycling :

HPC

=min)

: Standby Current (RAS=CAS=W=Vcc-0.2V)

: CAS-Before-RAS Refresh Current * (RAS and CAS cycling @

=min)

: Input Leakage Current (Any input 0

Vcc+0.5V, all other pins not under test=0 V)

: Output Leakage Current(Data Out is disabled, 0V

OUT

Vcc)

: Output High Voltage Level (I

= -5mA)

: Output Low Voltage Level (I

= 4.2mA)

DRAM MODULE

M53230810CW0/CB0

M53230800CW0/CB0

CAPACITANCE

= 25ĄÉ , V

=5V, f = 1MHz)

Item

Symbol

Min

Max

Unit

Input capacitance[A0-A11(A10)]
Input capacitance[W]
Input capacitance[RAS0, RAS1]
Input capacitance[CAS0 - CAS3]
Input/Output capacitance[DQ0-31]

IN1

IN2

IN3

IN4

100
130

70
30
20

pF
pF
pF
pF
pF

Test condition : V

=2.4/0.8V, V

=2.0/0.8V, Output loading CL=100pF

Parameter

Symbol

-50

-60

Unit

Note

Min

Max

Min

Max

Random read or write cycle time

110

Access time from RAS

RAC

3,4,10

Access time from CAS

CAC

3,4,5

Access time from column address

3,10

CAS to output in Low-Z

CLZ

Output buffer turn-off delay from CAS

CEZ

6,11,12

Transition time(rise and fall)

RAS precharge time

RAS pulse width

RAS

10K

RAS hold time

RSH

CAS hold time

CSH

CAS pulse width

CAS

10K

RAS to CAS delay time

RCD

RAS to column address delay time

RAD

CAS to RAS precharge time

CRP

Row address set-up time

ASR

Row address hold time

RAH

Column address set-up time

ASC

Column address hold time

CAH

Column address to RAS lead time

RAL

Read command set-up time

RCS

Read command hold time referenced to CAS

RCH

Read command hold time referenced to RAS

RRH

Write command hold time

WCH

Write command pulse width

Write command to RAS lead time

RWL

Write command to CAS lead time

CWL

Data-in set-up time

Data-in hold time

Refresh period (4K Ref)

REF

Refresh period (2K Ref)

REF

Write command set-up time

WCS

CAS setup time(CAS-before-RAS refresh)

CSR

CAS hold time(CAS-before-RAS refresh)

CHR

RAS to CAS precharge time

RPC

AC CHARACTERISTICS

C, V

=5.0V

10%. See notes 1,2.)

DRAM MODULE

M53230810CW0/CB0

M53230800CW0/CB0

NOTES

An initial pause of 200us is required after power-up followed
by any 8 RAS-only or CAS-before-RAS refresh cycles before
proper device operation is achieved.

(min) and V

(max) are reference levels for measuring

timing of input signals. Transition times are measured
between V

(min) and V

(max) and are assumed to be 5ns

for all inputs.

Measured with a load equivalent to 2 TTL loads and 100pF.

Operation within the

RCD

(max) limit insures that

RAC

(max)

can be met.

RCD

(max) is specified as a reference point only.

RCD

is greater than the specified

RCD

(max) limit, then

access time is controlled exclusively by

CAC

Assumes that

RCD

(max).

This parameter defines the time at which the output achieves
the open circuit condition and is not referenced to V

WCS

is non-restrictive operating parameter. It is included in

the data sheet as electrical characteristics only. If

WCS

(min), the cycle is an early write cycle and the data

out pin will remain high impedance for the duration of the
cycle.

Either

RCH

RRH

must be satisfied for a read cycle.

These parameter are referenced to the CAS leading edge in
early write cycles and to the W leading edge in read-write
cycles.

Operation within the

RAD

(max) limit insures that

RAC

(max)

can be met.

RAD

(max) is specified as reference point only. If

RAD

is greater than the specified t

RAD

(max) limit, then

access time is controlled by

CEZ

(max),

REZ

(max),

WEZ

(max) and

OEZ

(max) define the

time at which the output achieves the open circuit condition
and are not referenced to output voltage level.

If RAS goes to high before CAS high going, the open circuit
condtion of the output is achieved by CAS high going. If CAS
goes to high before RAS high going, the open circuit cond-
tion of the output is achieved by RAS high going.

ASC

min

10.

Test condition : V

=2.4/0.8V, V

=2.0/0.8V, Output loading CL=100pF

Parameter

Symbol

-50

-60

Unit

Note

Min

Max

Min

Max

CAS precharge time (C-B-R counter test cycle)

CPT

Access time from CAS precharge

CPA

Hyper page mode cycle time

HPC

CAS precharge time(Hyper page cycle)

RAS pulse width(Hyper page cycle)

RASP

200K

RAS hold time from CAS precharge

RHCP

W to RAS precharge time(C-B-R refresh)

WRP

W to RAS hold time(C-B-R refresh)

WRH

Output data hold time

DOH

Output buffer turn off delay from RAS

REZ

7,11,12

Output buffer turn off delay from W

WEZ

7,11

W to data delay

WED

W pulse width (Hyper Page Cycle)

WPE

AC CHARACTERISTICS

C, V

=5.0V

10%. See notes 1,2.)

11.

12.

13.

Part Number M532308x0Cx0