K9D1208V0A-SSB0

SmartMedia

Document Title

64M x 8 Bit SmartMedia

Card

Revision History

The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the

right to change the specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions about device. If you
have any questions, please contact the SAMSUNG branch office near your office.

Revision No

0.0

0.1

Remark

preliminary

Final

History

Initial issue

1. Renamed the 17th pin from Vcc to LVD(Low Voltage Detect)
-The LVD is used to electrically detect the proper supply voltage.
By connecting this pin to Vss through a pull-down resister, it is pos-
sible to distinguish 3.3V product from 5V product. When 3.3V is
applied as Vcc to pins 12 and 22, a 'High' level can be detected
on the system side if the device is a 3.3V product, and 'Low' level
for 5V product.

Draft Date

Nov. 20th 2000

Mar. 2th 2001

Note : For more detailed features and specifications including FAQ, please refer to Samsung's Flash web site.
http://www.intl.samsungsemi.com/Memory/Flash/datasheets.html

K9D1208V0A-SSB0

SmartMedia

64M x 8 Bit SmartMedia

Card

The K9D1208V0A is a 64M(67,108,864)x8bit NAND Flash
Memory with a spare 2,048K(2,097,152)x8bit. Its NAND cell
provides the most cost-effective solution for the solid state
mass storage market. A program operation programs the 528-
byte page in typically 200

s and an erase operation can be per-

formed in typically 2ms on a 16K-byte block. Data in the page
can be read out at 50ns cycle time per byte. The I/O pins serve
as the ports for address and data input/output as well as com-
mand inputs. The on-chip write controller automates all pro-
gram and erase functions including pulse repetition, where
required, and internal verify and margining of data. n, where
required, and internal verify and margining of data. Even the
write-intensive systems can take advantage of the
K9D1208V0A

s extended reliability of 100K program/erase

cycles by providing ECC(Error Correcting Code) with real time
mapping-out algorithm.
The K9D1208V0A is an optimum solution for large nonvolatile
storage applications such as solid state file storage, digital
voice recorder, digital still camera and other portable applica-
tions requiring non-volatility.

GENERAL DESCRIPTION

FEATURES

·Single 2.7V~3.6V Supply
·Organization
- Memory Cell Array : (64M + 2,048K)bit x 8bit
- Data Register : (512 + 16)bit x8bit
·Automatic Program and Erase
- Page Program : (512 + 16)Byte
- Block Erase : (16K + 512)Byte
·528-Byte Page Read Operation
- Random Access : 10

s(Max.)

- Serial Page Access : 50ns(Min.)
·Fast Write Cycle Time
- Program Time : 200

s(Typ.)

- Block Erase Time : 2ms(Typ.)
·Command/Address/Data Multiplexed I/O Port
·Hardware Data Protection
- Program/Erase Lockout During Power Transitions
·Reliable CMOS Floating-Gate Technology
- Endurance : 100K Program/Erase Cycles
- Data Retention : 10 Years
·Command Register Operation
·22pad SmartMedia

(SSFDC)

·ID for Copyright Protection

SmartMedia

CARD(SSFDC)

NOTE : Connect all V

and V

pins of each device to common power supply outputs.

Do not leave V

or V

disconnected.

Pin Name

Pin Function

I/O0 ~ I/O7

Data Input/Outputs

CLE

Command Latch Enable

ALE

Address Latch Enable

Chip Enable

Read Enable

Write Enable

Write Protect

LVD

Low Voltage Detect

GND

Ground

R/B

Ready/Busy output

Power

Ground

N.C

No Connection

PIN DESCRIPTION

I/O

LVD

GND

R/B

I/O

ALE

CLE

22 PAD SmartMedia

ID 64MB

K9D1208V0A-SSB0

SmartMedia

512B Byte

16 Byte

Figure 1. FUNCTIONAL BLOCK DIAGRAM

Figure 2. ARRAY ORGANIZATION

NOTE : Column Address : Starting Address of the Register.

00h Command(Read) : Defines the starting address of the 1st half of the register.
01h Command(Read) : Defines the starting address of the 2nd half of the register.

* A

is set to "Low" or "High" by the 00h or 01h Command.

* L muxt be set to "Low".

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

1st Cycle

2nd Cycle

3rd Cycle

4th Cycle

X-Buffers

Command

I/O Buffers & Latches

Latches

& Decoders

Y-Buffers

Latches

& Decoders

Register

Control Logic

& High Voltage

Generator

Global Buffers

Output

Driver

- A

Command

RE
WE

CLE

I/0 0

I/0 7

1st half Page Register
(=256 Bytes)

2nd half Page Register
(=256 Bytes)

128K Pages
(=4,096 Blocks)

512 Byte

8 bit

16 Byte

1 Block = 32 Pages
(16K + 512) Byte

I/O 0 ~ I/O 7

1 Page = 528 Byte
1 Block = 528 Byte x 32 Pages
= (16K + 512) Byte
1 Device = 528Byte x 32Pages x 4096 Blocks
= 528 Mbits

Column Address
Row Address

(Page Address)

Page Register

ALE

512M + 16M Bit

NAND Flash

ARRAY

(512 + 16)Byte x 131072

Y-Gating

Page Register & S/A

K9D1208V0A-SSB0

SmartMedia

PRODUCT INTRODUCTION

The K9D1208V0A is a 528Mbit(553,648,218 bit) memory organized as 131,072 rows(pages) by 528 columns. Spare sixteen col-
umns are located from column address of 512 to 527. A 528-byte data register is connected to memory cell arrays accommodating
data transfer between the I/O buffers and memory during page read and page program operations. The memory array is made up of
16 cells that are serially connected to form a NAND structure. Each of the 16 cells resides in a different page. A block consists of the
32 pages formed by two NAND structures, totaling 8448 NAND structures of 16 cells. The array organization is shown in Figure 2.
The program and read operations are executed on a page basis, while the erase operation is executed on a block basis. The mem-
ory array consists of 4096 separately erasable 16K-byte blocks. It indicates that the bit by bit erase operation is prohibited on the
K9D1208V0A.

The K9D1208V0A has addresses multiplexed into 8 I/O's. This scheme dramatically reduces pin counts and allows systems
upgrades to future densities by maintaining consistency in system board design. Command, address and data are all written through
I/O's by bringing WE to low while CE is low. Data is latched on the rising edge of WE. Command Latch Enable(CLE) and Address
Latch Enable(ALE) are used to multiplex command and address respectively, via the I/O pins. All commands require one bus cycle
except for Block Erase command which requires two cycles: one cycle for erase-setup and another for erase-execution after block
address loading. The 64M byte physical space requires 26 addresses, thereby requiring four cycles for byte-level addressing: col-
umn address, low row address and high row address, in that order. Page Read and Page Program need the same four address
cycles following the required command input. In Block Erase operation, however, only the three row address cycles are used. Device
operations are selected by writing specific commands into the command register. Table 1 defines the specific commands of the
K9D1208V0A.

Table 1. COMMAND SETS

NOTE : 1. The 00h command defines starting address of the 1st half of registers.

The 01h command defines starting address of the 2nd half of registers.
After data access on the 2nd half of register by the 01h command, the status pointer is
automatically moved to the 1st half register(00h) on the next cycle.

Function

1st. Cycle

2nd. Cycle

Acceptable Command during Busy

00h/01h

(1)

50h

Read ID

90h

Reset

FFh

Page Program

80h

10h

Block Erase

60h

D0h

Read Status

70h

K9D1208V0A-SSB0

SmartMedia

PIN DESCRIPTION

Command Latch Enable(CLE)

The CLE input controls the path activation for commands sent to the command register. When active high, commands are latched
into the command register through the I/O ports on the rising edge of the WE signal.

Address Latch Enable(ALE)

The ALE input controls the activating path for address to the internal address registers. Addresses are latched on the rising edge of
WE with ALE high.

Chip Enable(CE)

The CE input is the device selection control. When CE goes high during a read operation the device is returned to standby mode.
However, when the device is in the busy state during program or erase, CE high is ignored, and does not return the device to
standby mode.

Write Enable(WE)

The WE input controls writes to the I/O port. Commands, address and data are latched on the rising edge of the WE pulse.

Read Enable(RE)

The RE input is the serial data-out control, and when active drives the data onto the I/O bus. Data is valid t

REA

after the falling edge

of RE which also increments the internal column address counter by one.

I/O Port : I/O 0 ~ I/O 7

The I/O pins are used to input command, address and data, and to output data during read operations. The I/O pins float to high-z
when the chip is deselected or when the outputs are disabled.

Write Protect(WP)

The WP pin provides inadvertent write/erase protection during power transitions. The internal high voltage generator is reset when
the WP pin is active low.

Ready/Busy(R/B)

The R/B output indicates the status of the device operation. When low, it indicates that a program, erase or random read operation is
in process and returns to high state upon completion. It is an open drain output and does not float to high-z condition when the chip
is deselected or when outputs are disabled.

Low Voltage Detect(LVD)

The LVD is used to electrically detect the proper supply voltage. By connecting this pin to Vss through a pull-down resister, it is pos-
sible to distinguish 3.3V product from 5V product. When 3.3V is applied as Vcc to pins 12 and 22, a 'High' level can be detected on
the system side if the device is a 3.3V product, and 'Low' level for 5V product.

K9D1208V0A-SSB0

SmartMedia

DC AND OPERATING CHARACTERISTICS

(Recommended operating conditions otherwise noted.)

Parameter

Symbol

Test Conditions

Min

Typ

Max

Unit

Operating

Current

Sequential Read

tRC=50ns, CE=V

, I

OUT

=0mA

Program

Erase

Stand-by Current(TTL)

CE=V

, WP=0V/V

Stand-by Current(CMOS)

CE=V

-0.2, WP=0V/V

Input Leakage Current

=0 to 3.6V

Output Leakage Current

OUT

=0 to 3.6V

Input High Voltage, All inputs

2.0

+0.3

Input Low Voltage, All inputs

-0.3

0.8

Output High Voltage Level

=-400

2.4

Output Low Voltage Level

=2.1mA

0.4

Output Low Current(R/B)

(R/B)

=0.4V

ABSOLUTE MAXIMUM RATINGS

NOTE :

1. Minimum DC voltage is -0.3V on input/output pins. During transitions, this level may undershoot to -2.0V for periods <30ns.
Maximum DC voltage on input/output pins is V

+0.3V which, during transitions, may overshoot to V

+2.0V for periods <20ns.

2. Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to the conditions
as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect reliability.

Parameter

Symbol

Rating

Unit

Voltage on any pin relative to V

-0.6 to + 4.6

Temperature Under Bias

BIAS

-10 to +65

Storage Temperature

STG

-20 to +65

RECOMMENDED OPERATING CONDITIONS

(Voltage reference to GND, T

=0 to 55

Parameter

Symbol

Min

Typ.

Max

Unit

Supply Voltage

2.7

3.3

3.6

Supply Voltage

K9D1208V0A-SSB0

SmartMedia

MODE SELECTION

NOTE : 1. X can be V

or V

IH.

2. WP should be biased to CMOS high or CMOS low for standby.

CLE

ALE

Mode

Read Mode

Command Input

Address Input(4clock)

Write Mode

Command Input

Address Input(4clock)

Data Input

sequential Read & Data Output

During Read(Busy)

During Program(Busy)

During Erase(Busy)

(1)

Write Protect

0V/V

(2)

Stand-by

CAPACITANCE

(

=25

C, V

=3.3V, f=1.0MHz)

NOTE : Capacitance is periodically sampled and not 100% tested.

Item

Symbol

Test Condition

Min

Max

Unit

Input/Output Capacitance

I/O

=0V

Input Capacitance

=0V

VALID BLOCK

NOTE :
1. The

K9D1208V0A

may include invalid blocks when first shipped. Additional invalid blocks may develop while being used. The number of valid

blocks is presented with both cases of invalid blocks considered. Invalid blocks are defined as blocks that contain one or more bad bits

Do not try

to access these invalid blocks for program and erase.

Refer to the attached technical notes for a appropriate management of invalid blocks.

2. Per the specification of the physical format version 1.2 by SSFDC forum, minimum 1,000 vaild blocks are guaranteed for each 16MB memory space.

Parameter

Symbol

Min

Typ.

Max

Unit

Valid Block Number

4026

4096

Blocks

Program/Erase Characteristics

Parameter

Symbol

Min

Typ

Max

Unit

Program Time

PROG

200

500

Number of Partial Program Cycles
in the Same Page

Main Array

Nop

cycle

Spare Array

cycles

Block Erase Time

BERS

AC TEST CONDITION

=0 to 55

C, V

=2.7V~3.6V unless otherwise noted)

Parameter

Value

Input Pulse Levels

0.4V to 2.4V

Input Rise and Fall Times

5ns

Input and Output Timing Levels

1.5V

Output Load (3.0V +/-10%)

1 TTL GATE and CL=50pF

Output Load (3.3V +/-10%)

1 TTL GATE and CL=100pF

K9D1208V0A-SSB0

SmartMedia

AC Characteristics for Operation

NOTE :

1. The time to Ready depends on the value of the pull-up resistor tied R/B pin.
2. To break the sequential read cycle, CE must be held high for longer time than tCEH.
3. If reset command(FFh) is written at Ready state, the device goes into Busy for maximum 5us.

Parameter

Symbol

Min

Max

Unit

Data Transfer from Cell to Register

ALE to RE Delay( ID read )

AR1

100

ALE to RE Delay(Read cycle)

AR2

CE to RE Delay( ID read)

100

Ready to RE Low

RE Pulse Width

WE High to Busy

100

Read Cycle Time

RE Access Time

REA

RE High to Output Hi-Z

RHZ

CE High to Output Hi-Z

CHZ

RE High Hold Time

REH

Output Hi-Z to RE Low

Last RE High to Busy(at sequential read)

100

CE High to Ready(in case of interception by CE at read)

CRY

50 +tr(R/B)

(1)

CE High Hold Time(at the last serial read)

(2)

CEH

100

RE Low to Status Output

RSTO

CE Low to Status Output

CSTO

WE High to RE Low

WHR

RE access time(Read ID)

READID

Device Resetting Time(Read/Program/Erase)

RST

5/10/500

(3)

AC Timing Characteristics for Command / Address / Data Input

Parameter

Symbol

Min

Max

Unit

CLE setup Time

CLS

CLE Hold Time

CLH

CE setup Time

CE Hold Time

WE Pulse Width

(1)

ALE setup Time

ALS

ALE Hold Time

ALH

Data setup Time

Data Hold Time

Write Cycle Time

WE High Hold Time

NOTE : 1. If tCS is set less than 10ns, tWP must be minimum 35ns, otherwise, tWP may be minimum 25ns.

K9D1208V0A-SSB0

SmartMedia

SmartMedia Technical Notes

Identifying Invalid Block(s)

Invalid Block(s)

Invalid blocks are defined as blocks that contain one or more invalid bits whose reliability is not guaranteed by Samsung. The infor-
mation regarding the invalid block(s) is so called as the invalid block information. An invalid block(s) does not affect the performance
of valid block(s) because it is isolated from the bit line and the common source line by a select transistor. The system design must be
able to mask out the invalid block(s) via address mapping.

SSFDC Forum specifies the logical format and physical format to ensure compatibility of SmartMedia. Samsung pre-formats Smart-
Media in the Forum-compliant format prior to shipping.

Physical format standard by SSFDC Forum specifies that for the invalid

blocks the 6th byte in the spare area (column address 517 for 4MB SmartMedia and higher densities, 261 for 2MB SmartMedia,
respectively) contains two or more "0" bits to indicate a invalid block. Other than the blocks with format data and the invalid blocks
are erased(FFh). Since the invalid block information is also erasable in most cases, it is impossible to recover the information once it
has been erased. Therefore, the system must be able to recognize the invalid block(s) based on the original invalid block information
and create the invalid block table via the following suggested flow chart(Figure 3). Any intentional erasure of the original invalid block
information is prohibited.

Check "FFh" at the column address 517

Figure 3. Flow chart to create invalid block table.

Start

Set Block Address = 0

Check "FFh" ?

Increment Block Address

Last Block ?

End

Yes

Create (or update)

Invalid Block(s) Table

(or 261) of the first page in the block

K9D1208V0A-SSB0

SmartMedia

SmartMedia Technical Notes (Continued)

Program Flow Chart

Start

I/O 6 = 1 ?

Write 00h

I/O 0 = 0 ?

If ECC is used, this verification

Write 80h

Write Address

Write Data

Write 10h

Read Status Register

Write Address

Wait for tR Time

Verify Data

Program Completed

or R/B = 1 ?

Program Error

Yes

Program Error

Yes

: If program operation results in an error, map out

the block including the page in error and copy the

target data to another block.

operation is not needed.

Error in write or read operation

Over its life time, the additional invalid blocks may develop with NAND Flash memory. Refer to the qualification report for the actual
data.The following possible failure modes should be considered to implement a highly reliable system. In the case of status read fail-
ure after erase or program, block replacement should be done. To improve the efficiency of memory space, it is recommended that
the read or verification failure due to single bit error be reclaimed by ECC without any block replacement. The said additional block
failure rate does not include those reclaimed blocks.

Failure Mode

Detection and Countermeasure sequence

Write

Erase Failure

Status Read after Erase --> Block Replacement

Program Failure

Status Read after Program --> Block Replacement
Read back ( Verify after Program) --> Block Replacement

or ECC Correction

Read

Single Bit Failure

Verify ECC -> ECC Correction

ECC

: Error Correcting Code --> Hamming Code etc.
Example) 1bit correction & 2bit detection

K9D1208V0A-SSB0

SmartMedia

Erase Flow Chart

Start

I/O 6 = 1 ?

I/O 0 = 0 ?

Write 60h

Write Block Address

Write D0h

Read Status Register

or R/B = 1 ?

Erase Error

Yes

: If erase operation results in an error, map out

the failing block and replace it with another block.

Erase Completed

Yes

Read Flow Chart

Start

Verify ECC

Write 00h

Write Address

Read Data

ECC Generation

Reclaim the Error

Page Read Completed

Yes

Block Replacement

SmartMedia Technical Notes (Continued)

When the error happens with page "a" of Block "A", try
to write the data into another Block "B" from an exter-
nal buffer. Then, prevent further system access to
Block "A" (by creating a "invalid block" table or other
appropriate scheme.)

Buffer
memory

error occurs

Block A

Block B

Page a

K9D1208V0A-SSB0

SmartMedia

Samsung NAND Flash has three address pointer commands as a substitute for the two most significant column addresses. '00h'
command sets the pointer to 'A' area(0~255byte), '01h' command sets the pointer to 'B' area(256~511byte), and '50h' command sets
the pointer to 'C' area(512~527byte). With these commands, the starting column address can be set to any of a whole
page(0~527byte). '00h' or '50h' is sustained until another address pointer command is inputted. '01h' command, however, is effec-
tive only for one operation. After any operation of Read, Program, Erase, Reset, Power_Up is executed once with '01h' command,
the address pointer returns to 'A' area by itself. To program data starting from 'A' or 'C' area, '00h' or '50h' command must be input-
ted before '80h' command is written. A complete read operation prior to '80h' command is not necessary. To program data starting
from 'B' area, '01h' command must be inputted right before '80h' command is written.

00h

(1) Command input sequence for programming 'A' area

Address / Data input

80h

10h

00h

80h

10h

Address / Data input

The address pointer is set to 'A' area(0~255), and sustained

01h

(2) Command input sequence for programming 'B' area

Address / Data input

80h

10h

01h

80h

10h

Address / Data input

'B', 'C' area can be programmed.
It depends on how many data are inputted.

'01h' command must be rewritten before
every program operation

The address pointer is set to 'B' area(256~512), and will be reset to
'A' area after every program operation is executed.

50h

(3) Command input sequence for programming 'C' area

Address / Data input

80h

10h

50h

80h

10h

Address / Data input

Only 'C' area can be programmed.

'50h' command can be omitted.

The address pointer is set to 'C' area(512~527), and sustained

'00h' command can be omitted.

It depends on how many data are inputted.

'A','B','C' area can be programmed.

Pointer Operation of K9D1208V0A

Table 2. Destination of the pointer

Command

Pointer position

Area

00h
01h
50h

0 ~ 255 byte

256 ~ 511 byte
512 ~ 527 byte

1st half array(A)

2nd half array(B)

spare array(C)

"A" area

256 Byte

(00h plane)

"B" area

(01h plane)

"C" area

(50h plane)

256 Byte

16 Byte

"A"

"B"

"C"

Internal

Page Register

Pointer select
commnad

(00h, 01h, 50h)

Pointer

Figure 4. Block Diagram of Pointer Operation

K9D1208V0A-SSB0

SmartMedia

System Interface Using CE don't-care.

Timing requirements : If CE is is exerted high during data-loading,
tCS must be minimum 10ns and tWC must be increased accordingly.

(Min. 10ns)

Start Add.(4Cycle)

80h

Data Input

CLE

ALE

I/O

Data Input

CE don't-care

10h

For an easier system interface, CE may be inactive during the data-loading or sequential data-reading as shown below. The internal
528byte page registers are utilized as seperate buffers for this operation and the system design gets more flexible. In addition, for
voice or audio applications which use slow cycle time on the order of u-seconds, de-activating CE during the data-loading and read-
ing would provide significant savings in power consumption.

Start Add.(4Cycle)

00h

CLE

ALE

I/O

Data Output(sequential)

CE don't-care

R/B

CEA

out

REA

(Max. 45ns)

I/O

Timing requirements : If CE is exerted high during sequential
data-reading, the falling edge of CE to valid data(tCEA) must
be kept greater than 45ns.

Figure 5. Program Operation with CE don't-care.

Figure 6. Read Operation with CE don't-care.

Must be held
low during tR.

K9D1208V0A-SSB0

SmartMedia

* Input Data Latch Cycle

CLE

I/O

DIN 0

DIN 1

DIN 511

ALE

ALS

CLH

* Sequential Out Cycle after Read

(CLE=L, WE=H, ALE=L)

R/B

I/O

Dout

REA

RHZ*

REA

REH

REA

CHZ*

RHZ*

NOTES : Transition is measured

200mV from steady state voltage with load.

This parameter is sampled and not 100% tested.

K9D1208V0A-SSB0

SmartMedia

* Status Read Cycle

CLE

I/O

70h

Status Output

CLS

CLH

RSTO

RHZ*

CHZ*

WHR

CSTO

CLS

READ1 OPERATION

(READ ONE PAGE)

CLE

R/B

I/O

ALE

Busy

00h or 01h A

~ A

Dout N

Dout N+1 Dout N+2

Column
Address

Page(Row)
Address

AR2

RHZ

CHZ

CEH

Dout 527

CRY

K9D1208V0A-SSB0

SmartMedia

READ1 OPERATION

(INTERCEPTED BY CE)

CLE

R/B

I/O

ALE

Busy

00h or 01h

~ A

Dout N

Dout N+1

Dout N+2

Page(Row)
Address

Address

Column

AR2

CHZ

READ2 OPERATION

(READ ONE PAGE)

CLE

R/B

I/O

ALE

50h

~ A

Dout

Dout 527

M Address

511+M

AR2

: Valid Address

: Don

care

Selected
Row

Start
address M

512

K9D1208V0A-SSB0

SmartMedia

PAGE PROGRAM OPERATION

CLE

R/B

I/O

ALE

80h

70h

I/O

Din

10h

527

~ A

Sequential Data

Input Command

Column

Address

Page(Row)

Address

1 up to 528 Byte Data

Serial Input

Program

Command

Read Status

Command

I/O

=0 Successful Program

I/O

=1 Error in Program

PROG

SEQUENTIAL ROW READ OPERATION ( WITHIN A BLOCK )

CLE

R/B

I/O

ALE

00h

~ A

Busy

Output

~ A

Dout

N+1

Dout

527

Dout

527

Busy

M+1

Output

Ready

K9D1208V0A-SSB0

SmartMedia

BLOCK ERASE OPERATION

(ERASE ONE BLOCK)

CLE

R/B

I/O

ALE

60h

~ A

Auto Block Erase Setup Command

Erase Command

Read Status

Command

I/O

=1 Error in Erase

DOh

70h

I/O 0

Busy

BERS

I/O

=0 Successful Erase

Page(Row)

Address

MANUFACTURE & DEVICE ID READ OPERATION

CLE

I/O 0 ~ 7

ALE

90h

Read ID Command

Maker Code

Device Code

00h

ECh

76h

READID

Address. 1cycle

K9D1208V0A-SSB0

SmartMedia

DEVICE OPERATION

PAGE READ

Upon initial device power up, the device defaults to Read1 mode. This operation is also initiated by writing 00h to the command reg-
ister along with four address cycles. Once the command is latched, it does not need to be written for the following page read opera-
tion. Three types of operations are available : random read, serial page read and sequential row read.
The random read mode is enabled when the page address is changed. The 528 bytes of data within the selected page are trans-
ferred to the data registers in less than 10

s(t

). The system controller can detect the completion of this data transfer(tR) by analyz-

ing the output of R/B pin. Once the data in a page is loaded into the registers, they may be read out in 50ns cycle time by sequentially
pulsing RE. High to low transitions of the RE clock output the data stating from the selected column address up to the last column
address.
After the data of last column address is clocked out, the next page is automatically selected for sequential row read.
Waiting 10

s again allows reading the selected page. The sequential row read operation is terminated by bringing CE high. The

way the Read1 and Read2 commands work is like a pointer set to either the main area or the spare area. The spare area of bytes
512 to 527 may be selectively accessed by writing the Read2 command. Addresses A

to A

set the starting address of the spare

area while addresses A

to A

are ignored. Unless the operation is aborted, the page address is automatically incremented for

sequential row read as in Read1 operation and spare sixteen bytes of each page may be sequentially read. The Read1 com-
mand(00h/01h) is needed to move the pointer back to the main area. Figures 7 thru 10 show typical sequence and timings for each
read operation.

Figure 7. Read1 Operation

Start Add.(4Cycle)

00h

~ A

& A

~ A

Data Output(Sequential)

(00h Command)

Data Field

Spare Field

CLE

ALE

R/B

I/O

* After data access on 2nd half array by 01h command, the start pointer is automatically moved to 1st half
array (00h) at next cycle.

(01h Command)*

Data Field

Spare Field

1st half array

2st half array

1st half array

2st half array

K9D1208V0A-SSB0

SmartMedia

Figure 8. Read2 Operation

50h

~ A

& A

~ A

Data Output(Sequential)

Spare Field

CLE

ALE

R/B

Data Field

Spare Field

Start Add.(4Cycle)

~ A

Don

t Care)

I/O

Figure 9. Sequential Row Read1 Operation

00h

01h

~ A

& A

~ A

I/O

R/B

Start Add.(4Cycle)

Data Output

1st

2nd

Nth

(528 Byte)

The Sequential Read 1 and 2 operation is allowed only within a block and after the last page of a block is read-
out, the sequential read operation must be terminated by bringing CE high. When the page address moves onto
the next block, read command and address must be given.

(00h Command)

1st half array 2nd half array

Data Field

Spare Field

1st
2nd

(01h Command)

Data Field

Spare Field

Nth

1st half array 2nd half array

1st
2nd

Nth

Block

1st half array 2nd half array

K9D1208V0A-SSB0

SmartMedia

Figure 10. Sequential Row Read2 Operation

PAGE PROGRAM

The device is programmed basically on a page basis, but it does allow multiple partial page programing of a byte or consecutive
bytes up to 528, in a single page program cycle. The number of consecutive partial page programming operation within the same
page without an intervening erase operation must not exceed 1 for main array and 2 for spare array. The addressing may be done in
any random order in a block. A page program cycle consists of a serial data loading period in which up to 528 bytes of data may be
loaded into the page register, followed by a non-volatile programming period where the loaded data is programmed into the appropri-
ate cell. Serial data loading can be started from 2nd half array by moving pointer. About the pointer operation, please refer to the
attached technical notes.
The serial data loading period begins by inputting the Serial Data Input command(80h), followed by the four cycle address input and
then serial data loading. The bytes other than those to be programmed do not need to be loaded.The Page Program confirm com-
mand(10h) initiates the programming process. Writing 10h alone without previously entering the serial data will not initiate the pro-
gramming process. The internal write controller automatically executes the algorithms and timings necessary for program and verify,
thereby freeing the system controller for other tasks. Once the program process starts, the Read Status Register command may be
entered, with RE and CE low, to read the status register. The system controller can detect the completion of a program cycle by
monitoring the R/B output, or the Status bit(I/O 6) of the Status Register. Only the Read Status command and Reset command are
valid while programming is in progress. When the Page Program is complete, the Write Status Bit(I/O 0) may be checked(Figure 11).
The internal write verify detects only errors for "1"s that are not successfully programmed to "0"s. The command register remains in
Read Status command mode until another valid command is written to the command register.

50h

~ A

& A

~ A

I/O

R/B

Start Add.(4Cycle)

Data Output

2nd

Nth

(16Byte)

1st

Figure 11. Program & Read Status Operation

80h

~ A

& A

~ A

I/O

R/B

Address & Data Input

I/O

Pass

528 Byte Data

10h

70h

Fail

PROG

Data Field

Spare Field

1st
Block

~ A

Don

t Care)

Nth

K9D1208V0A-SSB0

SmartMedia

Figure 12. Block Erase Operation

BLOCK ERASE

The Erase operation is done on a block(16K Byte) basis. Block address loading is accomplished in three cycles initiated by an Erase
Setup command(60h). Only address A

to A

is valid while A

to A

is ignored. The Erase Confirm command(D0h) following the

block address loading initiates the internal erasing process. This two-step sequence of setup followed by execution command
ensures that memory contents are not accidentally erased due to external noise conditions.
At the rising edge of WE after the erase confirm command input, the internal write controller handles erase and erase-verify. When
the erase operation is completed, the Write Status Bit(I/O 0) may be checked. Figure 12 details the sequence.

60h

Block Add. : A

~ A

I/O

R/B

Address Input(3Cycle)

I/O

Pass

D0h

70h

Fail

BERS

READ STATUS

The device contains a Status Register which may be read to find out whether program or erase operation is completed, and whether
the program or erase operation is completed successfully. After writing 70h command to the command register, a read cycle outputs
the content of the Status Register to the I/O pins on the falling edge of CE or RE, whichever occurs last. This two line control allows
the system to poll the progress of each device in multiple memory connections even when R/B pins are common-wired. RE or CE
does not need to be toggled for updated status. Refer to table 3 for specific Status Register definitions. The command register
remains in Status Read mode until further commands are issued to it. Therefore, if the status register is read during a random read
cycle, a read command(00h or 50h) should be given before sequential page read cycle.

I/O #

Status

Definition

I/O 0

Program / Erase

"0" : Successful Program / Erase

"1" : Error in Program / Erase

I/O 1

Reserved for Future

Use

"0"

I/O 2

"0"

I/O 3

"0"

I/O 4

"0"

I/O 5

"0"

I/O 6

Device Operation

"0" : Busy "1" : Ready

I/O 7

Write Protect

"0" : Protected "1" : Not Protected

Table3. Read Staus Register Definition

K9D1208V0A-SSB0

SmartMedia

Figure 13. Read ID Operation

CLE

I/O

ALE

90h

00h

ECh

76h

Address. 1cycle

Maker code

Device code

AR1

READID

Figure 14. RESET Operation

RESET

The device offers a reset feature, executed by writing FFh to the command register. When the device is in Busy state during random
read, program or erase mode, the reset operation will abort these operations. The contents of memory cells being altered are no
longer valid, as the data will be partially programmed or erased. The command register is cleared to wait for the next command, and
the Status Register is cleared to value C0h when WP is high. Refer to table 4 for device status after reset operation. If the device is
already in reset state a new reset command will not be accepted by the command register. The R/B pin transitions to low for tRST
after the Reset command is written. Reset command is not necessary for normal operation. Refer to Figure 14 below.

After Power-up

After Reset

Operation Mode

Waiting for next command

FFh

I/O

R/B

Table4. Device Status

RST

READ ID

The device contains a product identification mode, initiated by writing 90h to the command register, followed by an address input of
00h. Two read cycles sequentially output the manufacture code(ECH), and the device code (76H) respectively. The command regis-
ter remains in Read ID mode until further commands are issued to it. Figure 13 shows the operation sequence.

K9D1208V0A-SSB0

SmartMedia

DATA PROTECTION

The device is designed to offer protection from any involuntary program/erase during power-transitions. An internal voltage detector
disables all functions whenever Vcc is below about 2V. WP pin provides hardware protection and is recommended to be kept at V

during power-up and power-down as shown in Figure 15. The two step command sequence for program/erase provides additional
software protection.

READY/BUSY

The device has a R/B output that provides a hardware method of indicating the completion of a page program, erase and random
read completion. The R/B pin is normally high but transitions to low after program or erase command is written to the command reg-
ister or random read is started after address loading. It returns to high when the internal controller has finished the operation. The pin
is an open-drain driver thereby allowing two or more R/B outputs to be Or-tied. An appropriate pull-up resister is required for proper
operation and the value may be calculated by the following equation.

R/B
open drain output

Device

GND

Rp =

(Max.) - V

(Max.)

3.2V

8mA

where I

is the sum of the input currents of all devices tied to the

R/B pin.

Figure 15. AC Waveforms for Power Transition

High

~ 2.5V

SmartMedia Dimensions

SmartMedia

DIMENSIONS

Unit:mm

0.15

0.05

22 PAD SOLID STATE FLOPPY DISK CARD (3.3V)

2
7

.
5

2
2

.
1
(
M

a
x
)

SOLID STATE PRODUCT OUTLINE

0.76

0.08

1.5

0.1

27.0

0.5mm Chamfer
(3.3V Card)

4.2(Min)

45.0

0.1

.
5
(
M

i
n

)

37.0

0.1

5.0

0.2

Index Label Area

10.0

0.2

Write Protect Area

c
c

/
B

c
c

I
/
O

c
c

I
/
O

1
2
.
7
0

6.500

7.900

8.650

1
0
.
1
6

7
.
6
2

5
.
0
8

2
.
5
4

0
.
0
0

2
.
7
0
0

6.500

7.900

8.650

0
.
1
6
0

.
6
2
0

.
0
8
0

.
5
4
0

.
0
0
0

2.140 TYP

0.400 TYP

0.000

40.0

0.1

5.0

Part Number K9D1208V0A-SSB0