TBB1010

Twin Build in Biasing Circuit MOS FET IC

VHF/VHF RF Amplifier

ADE-208-1607B (Z)

3rd. Edition

Feb. 2003

Features

Small SMD package CMPAK-6 built in twin BBFET; To reduce using parts cost & PC board space.

High |yfs|=29mS ×2

Suitable for World Standard Tuner RF amplifier.

Very useful for total tuner cost reduction.

Withstanding to ESD; Build in ESD absorbing diode. Withstand up to 200 V at C = 200 pF,
Rs = 0 conditions.

Provide mini mold packages; CMPAK-6

Outline

CMPAK-6

1. Drain(1)
2. Source
3. Drain(2)
4. Gate-1(2)
5. Gate-2
6. Gate-1(1)

Notes:

Marking is "KM".

TBB1010 is individual type number of HITACHI TWIN BBFET.

TBB1010

Rev.2, Feb. 2003, page 2 of 10

Absolute Maximum Ratings

(Ta = 25°C)

Item

Symbol

Ratings

Unit

Drain to source voltage

Gate1 to source voltage

G1S

+6
-0

Gate2 to source voltage

G2S

+6
-0

Drain current

Channel power dissipation

Pch

250

Channel temperature

Tch

150

Storage temperature

Tstg

55 to +150

Notes: 3. Value on the glass epoxy board (50mm

40mm

1mm).

TBB1010

Rev.2, Feb. 2003, page 3 of 10

Electrical Characteristics

(Ta = 25°C)

The below specification are applicable for FET1 and FET2 unit

Item

Symbol Min

Typ

Max

Unit

Test Conditions

Drain to source breakdown
voltage

(BR)DSS

= 200

A, V

G1S

= V

G2S

= 0

Gate1 to source breakdown
voltage

(BR)G1SS

= +10

A, V

G2S

= V

= 0

Gate2 to source breakdown
voltage

(BR)G2SS

= +10

A, V

G1S

= V

= 0

Gate1 to source cutoff current

G1SS

+100

G1S

= +5 V, V

G2S

= V

= 0

Gate2 to source cutoff current

G2SS

+100

G2S

= +5 V, V

G1S

= V

= 0

Gate1 to source cutoff voltage

G1S(off)

0.6

1.1

= 5 V, V

G2S

= 4 V,

= 100

Gate2 to source cutoff voltage

G2S(off)

0.6

1.1

= 5 V, V

G1S

= 5 V,

= 100

Drain current

D(op)

= 5 V, V

= 5 V

G2S

= 4 V, R

= 120 k

Forward transfer admittance

= 5 V, V

G2S

=4V

= 120 k

, f = 1 kHz

Input capacitance

Ciss

1.7

2.1

2.5

= 5 V, V

= 5 V

Output capacitance

Coss

1.0

1.4

1.8

G2S

=4 V, R

= 120 k

Reverse transfer capacitance

Crss

0.03

0.05

f = 1 MHz

Power gain

= V

= 5 V, V

G2S

= 4 V

Noise figure

1.1

1.8

= 120 k

, f = 200 MHz

TBB1010

Rev.2, Feb. 2003, page 4 of 10

Test Circuits

DC Biasing Circuit for Operating Characteristic Items (I

D(op)

, |yfs|, Ciss, Coss, Crss, NF, PG)

Measurment of FET1

Gate 1

Source

Open

Drain

Gate 2

Measurment of FET2

Open

Source

Gate 2

Drain

Gate 1

Open

TBB1010

Rev.2, Feb. 2003, page 5 of 10

Equivalent Circuit

BBFET-(1)

BBFET-(2)

No.1

No.2

No.3

No.6

No.5

No.4

Drain(1)

Source

Drain(2)

Gate-1(1)

Gate-2

Gate-1(2)

200 MHz Power Gain, Noise Figure Test Circuit

Input (50

)

1000p

36p

1000p

V = V

D G1

TWINBBFET

RFC

Output (50

)

1000p

10p max

1000p

47k

1SV70

1000p

47k

120k

Unit : Resistance (

)

Capacitance (F)

1SV70

L1 :

1mm Enameled Copper Wire,Inside dia 10mm, 2Turns

L2 :

1mm Enameled Copper Wire,Inside dia 10mm, 2Turns

RFC :

1mm Enameled Copper Wire,Inside dia 5mm, 2Turns

TBB1010

Rev.2, Feb. 2003, page 6 of 10

400

300

200

100

150

200

V = 4 V
V = V

G2S

V = 5 V
R = 120 k

Channel Power Dissipation Pch* (mW)

Ambient Temperature Ta (

Maximum Channel Power

Dissipation Curve

Drain Current I (mA)

Typical Output Characteristics

Drain to Source Voltage V (V)

Drain Current vs. Gate1 Voltage

Gate1 Voltage V (V)

Drain Current I (mA)

R = 82 k

100 k

2 V

V = 1 V

G2S

4 V

3 V

* Value on the glass epoxy board (50mm

× 40

1mm)

120 k

150 k

180 k

Gate1 Voltage V (V)

Forward Transfer Admittance

vs. Gate1 Voltage

Forward Transfer Admittance |y | (mS)

V = 1 V

G2S

4 V

3 V

2 V

V = 5 V
R = 120 k

f = 1 kHz

TBB1010

Rev.2, Feb. 2003, page 7 of 10

Gate2 to Source Voltage V (V)

G2S

Input Capacitance Ciss (pF)

Input Capacitance vs.

Gate2 to Source Voltage

100 200

500 1000

V = 5 V
V = 5 V
V = 4 V

DS
G1
G2S

Drain Current vs. Gate Resistance

Drain Current I (mA)

Gate Resistance R (k

)

100 200

500 1000

V = 5 V
V = 5 V
V = 4 V
f = 200 MHz

DS
G1
G2S

Power Gain vs. Gate Resistance

Gate Resistance R (k

)

Power Gain PG (dB)

100

200

500 1000

Noise Figure vs. Gate Resistance

Noise Figure NF (dB)

Gate Resistance R (k

)

V = 5 V
V = 5 V
V = 4 V
f = 200 MHz

DS
G1
G2S

V = 5 V
V = 5 V
R = 120 k

f = 1 MHz

DS
G1

TBB1010

Rev.2, Feb. 2003, page 8 of 10

DS
G

V = V = 5 V
R = 120 k

Gain Reduction GR (dB)

Gain Reduction vs.

Gate2 to Source Voltage

Gate2 to Source Voltage V (V)

G2S

TBB1010

Rev.2, Feb. 2003, page 9 of 10

Package Dimensions

2.1 ą 0.3

6-0.2

0.9 ą 0.1

(0.2)

2.0 ą 0.2

(0.65)

1.3 ą 0.2

(0.425)

Hitachi Code
JEDEC
JEITA
Mass (reference value)

CMPAK-6
--
Conforms
0.006 g

0.15

0 0.1

+ 0.1
0.05

1.25 ą 0.1

As of July, 2002

Unit: mm

TBB1010

Rev.2, Feb. 2003, page 10 of 10

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Colophon 7.0

Part Number TBB1010