This data sheet contains design specifications for product development. Ramtron International Corporation
These specifications may change in any manner without notice 1850 Ramtron Drive, Colorado Springs, CO 80921
(800) 545-FRAM, (719) 481-7000, Fax (719) 481-7058

www.ramtron.com

11 May 2000 1/14

FM25040

4Kb FRAM Serial Memory

Features

4K bit Ferroelectric Nonvolatile RAM

Organized as 512 x 8 bits

High endurance 10 Billion (10

) read/writes

10 year data retention at 85

NoDelayTM write

Advanced high-reliability ferroelectric process

Fast Serial Peripheral Interface - SPI

Up to 2.1 MHz maximum bus frequency

Direct hardware replacement for EEPROM

Supports SPI Mode 0 (CPOL=0, CPHA=0)

Sophisticated Write Protection Scheme

Hardware protection

Software protection

Low Power Consumption

A standby current

Industry Standard Configuration

Industrial temperature -40

C to +85

8-pin SOP or DIP

Description

The FM25040 is a 4-kilobit nonvolatile memory
employing an advanced ferroelectric process. A
ferroelectric random access memory or FRAM is
nonvolatile but operates in other respects as a RAM.
It provides reliable data retention for 10 years while
eliminating the complexities, overhead, and system
level reliability problems caused by EEPROM and
other nonvolatile memories.

Unlike serial EEPROMs, the FM25040 performs
write operations at bus speed. No write delays are
incurred. Data is written to the memory array mere
hundreds of nanoseconds after it has been
successfully transferred to the device. The next bus
cycle may commence immediately. In addition the
product offers substantial write endurance compared
with other nonvolatile memories. The FM25040 is
capable of supporting up to 1E10 read/write cycles --
far more than most systems will require from a serial
memory.

These capabilities make the FM25040 ideal for
nonvolatile memory applications requiring frequent
or rapid writes. Examples range from data collection,
where the number of write cycles may be critical, to
demanding industrial controls where the long write
time of EEPROM can cause data loss.

The FM25040 provides substantial benefits to users
of serial EEPROM, in a hardware drop-in
replacement. The FM25040 uses the high-speed SPI
bus which enhances the high-speed write capability of
FRAM technology. It is guaranteed over an industrial
temperature range of -40°C to +85°C.

Pin Configuration

VSS

VCC

HOLD

SCK

Pin Names

Function

/CS

Chip Select

Serial Data Output

/WP

Write Protect

VSS

Ground

Serial Data Input

SCK

Serial Clock

/HOLD

Hold

VCC

Supply Voltage 5V

Ordering Information

FM25040-P

8-pin plastic DIP

FM25040-S

8-pin SOP

Ramtron FM25040

11 May 2000 3/14

Pin Description

Pin Name

Pin Number I/O Pin Description

/CS

Chip Select. Activates the device. When high, all outputs are tri-state and
the device ignores other inputs. The part remains in a low power standby
mode. When low, the part recognizes activity on the SCK signal. A
falling edge on /CS must occur prior to every op-code.

Serial Output. SO is the data output pin. It is driven actively during a read
and remains tri-state at all other times including when /HOLD is low.
Data transitions are driven on the falling edge of the serial clock.
* SO can be connected to SI for a single pin data interface since the part
communicates in half-duplex fashion.

/WP

Write Protect. This pin prevents all write operations. If low, the part is
completely write protected. If high, write access is determined by the
other write protection features. A complete explanation of write
protection is provided below. *Note that the function of /WP is different
from the FM25160 where it protects the status register only.

VSS

Ground

Serial Input. All data is input to the device on this pin. The pin is sampled
on the rising edge of SCK and is ignored at other times. It should always
be driven to a valid logic level to meet ICC specifications.
* SI may be connected to SO for a single pin data interface.

SCK

Serial Clock. All I/O activity is synchronized to the serial clock. Inputs
are latched on the rising edge and outputs occur on the falling edge. The
part is static so the clock frequency may be any value between 0 and 2.1
MHz and may be interrupted at any time.

/HOLD

Hold. The /HOLD signal is used when the host CPU must interrupt a
memory operation for another task. Taking the /HOLD signal to a low
state pauses the current operation. The part ignores any transition on SCK
or /CS. All transitions on /HOLD must occur while SCK is low.

VCC

Supply Voltage. 5V

Overview

The FM25040 is a serial FRAM memory. The
memory array is logically organized as 512 x 8 and is
accessed using an industry standard Serial Peripheral
Interface or SPI bus. Functional operation of the
FRAM is similar to serial EEPROMs. The major
difference between the FM25040 and a serial
EEPROM with the same pin-out relates to its superior
write performance.

Memory Architecture

When accessing the FM25040, the user addresses 512
locations each with 8 data bits. These data bits are
shifted serially. The addresses are accessed using the
SPI protocol, which includes a chip select (to permit
multiple devices on the bus), an op-code including the
upper address bit, and a word address. The word
address consists of the lower 8-addres bits. The
complete address of 9-bits specifies each byte address
uniquely.

Most functions of the FM25040 are either controlled
by the SPI interface, or are handled automatically by
on-board circuitry. The access time for memory

operation essentially is zero, beyond the time needed
for the serial protocol. That is, the memory is read or
written at the speed of the SPI bus. Unlike an
EEPROM, it is not necessary to poll the device for a
ready condition since writes occur at bus speed. That
is, by the time a new bus transaction can be shifted
into the part, a write operation will be complete. This
is explained in more detail in the interface section
below.

Users expect several obvious system benefits from
the FM25040 due to its fast write cycle and high
endurance as compared with EEPROM. However
there are less obvious benefits as well. For example in
a high noise environment, the fast-write operation is
less susceptible to corruption than an EEPROM since
it is completed quickly. By contrast, an EEPROM
requiring milliseconds to write is vulnerable to noise
during much of the cycle.

Note that the FM25040 contains no power
management circuits other than a simple internal
power-on reset. It is the user's responsibility to ensure
that VCC is within data sheet tolerances to prevent
incorrect operation.

Ramtron FM25040

11 May 2000 4/14

Serial Peripheral Interface SPI Bus

The FM25040 employs a Serial Peripheral Interface
(SPI) bus. This high-speed serial bus provides high
performance serial communication with a host
microcontroller. Many common microcontrollers
have hardware SPI ports allowing a direct interface. It
is quite simple to emulate the SPI interface using
ordinary port pins for microcontrollers that do not.
Note that the FM25040 operates in SPI Mode 0 only.

The SPI interface uses a total of four pins; clock,
data-in, data-out, and chip select. It is possible to
connect the two data lines together. Figure 2
illustrates a typical system configuration using the
FM25040 with a microcontroller that offers an SPI
port. Figure 3 shows a similar configuration for a
microcontroller that has no hardware support for the
SPI bus.

Protocol Overview

The SPI interface is a synchronous serial interface
using clock and data lines. It is intended to support
multiple devices on the bus. Each device is activated
using a chip select. Once chip select is activated by
the bus master, the FM25040 will begin monitoring
the clock and data lines. The relationship between the
falling edge of /CS, the clock and data is dictated by
the SPI mode. There are four such modes however
the FM25040 supports only mode 0. This mode
dictates that the SCK signal must be low when /CS is
activated.

The SPI protocol is controlled by op-codes. These
op-codes specify the commands to the part. After /CS
is activated, the first byte transferred from the bus
master is the op-code. Following the op-code, any
addresses and data are then transferred. Certain op-
codes are commands with no subsequent data
transfer. The /CS must go inactive after an operation
is complete and before a new op-code can be issued.

Figure 2. System Configuration with SPI port

Figure 3. System Configuration without SPI port

Ramtron FM25040

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Data Transfer

All data transfers to and from the FM25040 occur in
8-bit groups. They are synchronized to the clock
signal (SCK) and occur most significant bit (MSB)
first. Serial inputs are clocked in on the rising edge
of SCK. Outputs are driven on the falling edge of
SCK.

Command Structure

There are six commands called op-codes that can be
issued by the bus master to the FM25040. They are
listed in the table below. These op-codes control the
functions performed by the memory. They can be
divided into three categories. First, are commands
that have no subsequent operands. They perform a
single function such as to enable a write operation.
Second are commands followed by one byte, either in
or out. They operate on the status register Last are
commands for memory transactions followed by
address and one or more bytes of data.

Table 1. Op-code Commands

Name

Description

Op-code value

WREN

Set Write Enable Latch

00000110

WRDI

Write Disable

00000100

RDSR

Read Status Register

00000101

WRSR

Write Status Register

00000001

READ

Read Memory Data

0000A011

WRITE

Write Memory Data

0000A010

WREN - Set Write Enable Latch

The FM25040 will power up with writes disabled.
The WREN command must be issued prior to any
write operation. Sending the WREN op-code will
allow the user to issue subsequent op-codes for write
operations. These include writing the status register
and writing the memory.

Sending the WREN op-code causes the internal Write
Enable Latch to be set. A flag bit in the status
register, called WEL, indicates the state of the latch.
WEL=1 indicates that writes are permitted.
Attempting to write the WEL bit in the status register
has no affect. Completing any write operation (rising
edge of /CS) will automatically clear the Write
Enable Latch and prevent further writes without
another WREN command. Figure 4 below illustrates
the WREN command bus configuration.

WRDI - Write Disable

The WRDI command disables all write activity by
clearing the Write Enable Latch. The user can verify
that writes are disabled by reading the WEL bit in the
status register and verifying that WEL=0. Figure 5
below illustrates the WRDI command bus
configuration.

Figure 4. WREN Bus Configuration

Figure 5. WRDI Bus Configuration

Part Number FM25040