Philips Semiconductors

Product specification

SSTL16877

14-bit SSTL_2 registered driver with
differential clock inputs

2000 Apr 20

853-2198 23523

FEATURES

Stub-series terminated logic for 2.5 V VDDQ (SSTL_2)

Optimized for DDR (Double Data Rate) SDRAM applications

Supports SSTL_2 signal inputs and outputs

Flow-through architecture optimizes PCB layout

Meets SSTL_2 class I and class II specifications

Latch-up protection exceeds 500mA per JEDEC Std 17

ESD protection exceeds 2000 V per MIL STD 833 Method 3015
and 200 V per Machine Model

Full DDR solution provided when used with PCK877 and CBT3867

DESCRIPTION

The SSTL16877 is a 14-bit SSTL_2 registered driver with differential
clock inputs, designed to operate between 2.3 V and 2.7 V. V

DDQ

must not exceed V

. Inputs are SSTL_2 type with V

REF

normally at

0.5*V

DDQ

. The outputs support class I which can be used for

standard stub-series applications or capacitive loads. Master reset
(RESET) asynchronously resets all registers to zero.

The SSTL16877 is intended to be incorporated into standard DIMM
(Dual In-Line Memory Module) designs defined by JEDEC, such as
DDR (Double Data Rate) SDRAM or SDRAM II Memory Modules.
Different from traditional SDRAM, DDR SDRAM transfers data on
both clock edges (rising and falling), thus doubling the peak bus
bandwidth. A DDR DRAM rated at 166 MHz will have a burst rate of
333 MHz. The modules require between 23 and 27 registered
control and address lines, so two 14-bit wide devices will be used on
each module. The SSTL16877 is intended to be used for SSTL_2
input and output signals.

The device data inputs consist of differential receivers. One
differential input is tied to the input pin while the other is tied to a
reference input pad, which is shared by all inputs.

The clock input is fully differential to be compatible with DRAM
devices that are installed on the DIMM. However, since the control
inputs to the SDRAM change at only half the data rate, the device
must only change state on the positive transition of the CLK signal.
In order to be able to provide defined outputs from the device even
before a stable clock has been supplied, the device must support an
asynchronous input pin (reset), which when held to the LOW state
will assume that all registers are reset to the LOW state and all
outputs drive a LOW signal as well.

PIN CONFIGURATION

VDDQ

Q10

D12

D11

D10

RESET

VREF

GND

VCC

CLK+

CLK

VCC

GND

VDDQ

Q14

D14

D13

GND

VCC

GND

VDDQ

GND

VDDQ

GND

Q11

Q12

GND

Q13

SW00311

QUICK REFERENCE DATA

GND = 0 V; T

amb

= 25

C; t

2.5 ns

SYMBOL

PARAMETER

CONDITIONS

TYPICAL

UNIT

PHL

PLH

Propagation delay; CLK to Qn

= 30 pF; V

DDQ

= 2.5 V

2.4

Input capacitance

= 2.5 V

2.9

NOTES:
1. C

is used to determine the dynamic power dissipation (P

W) P

= C

x f

)

) where:

= input frequency in MHz; C

= output load capacity in pF; f

= output frequency in MHz; V

= supply voltage in V;

) = sum of the outputs.

ORDERING INFORMATION

PACKAGES

TEMPERATURE RANGE

ORDER CODE

DWG NUMBER

48-Pin Plastic TSSOP Type I

C to +70

SSTL16877 DGG

SOT362-1

Philips Semiconductors

Product specification

SSTL16877

14-bit SSTL_2 registered driver with
differential clock inputs

2000 Apr 20

PIN DESCRIPTION

PIN NUMBER

SYMBOL

NAME AND FUNCTION

RESET

LVCMOS asynchronous master
reset
(Active LOW)

48, 47, 44, 43,
42, 41, 40, 33,
32, 31, 30, 29,

26, 25

D1 D14

SSTL_2 data inputs

1, 2, 5, 6, 7, 10,

11, 14, 15, 18,

19, 20, 23, 24

Q1 Q14

SSTL_2 data outputs

VREF

SSTL_2 input reference level

3, 8, 13, 17, 22,

27, 36, 46

GND

Ground (0 V)

28, 37, 45

Positive supply voltage

4, 9, 12, 16, 21

DDQ

Output supply voltage

38
39

CLK+
CLK

Differential clock inputs

FUNCTION TABLE

INPUTS

OUTPUT

RESET

CLK

L or H

H = High voltage level
L = High voltage level

= High-to-Low transition

= Low-to-High transition

X = Don't care

LOGIC DIAGRAM

SW00312

RESET

VREF

D10

D11

D12

D13

D14

CLK+

CLK

Q10

Q11

Q12

Q13

Q14

ABSOLUTE MAXIMUM RATINGS

1, 2

SYMBOL

PARAMETER

CONDITION

LIMITS

UNIT

SYMBOL

PARAMETER

CONDITION

MIN

MAX

UNIT

DC supply voltage

0.5

+4.6

DC input diode current

< 0

DC input voltage

0.5

DDQ

+ 0.5

DC output diode current

< 0

OUT

DC output voltage

Note 3

0.5

DDQ

+ 0.5

DC output current

= 0 to V

DDQ

OUT

Continuous current

, V

DDQ

, or GND

100

STG

Storage temperature range

+150

NOTES:
1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the

device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to
absolute-maximum-rated conditions for extended periods may affect device reliability.

2. The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction

temperatures which are detrimental to reliability. The maximum junction temperature of this integrated circuit should not exceed 150

3. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
4. The continuous current at V

, V

DDQ

, or GND should not exceed

100 mA.

Philips Semiconductors

Product specification

SSTL16877

14-bit SSTL_2 registered driver with
differential clock inputs

2000 Apr 20

RECOMMENDED OPERATING CONDITIONS

SYMBOL

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Supply voltage

2.3

2.5

2.7

DDQ

Output supply voltage

2.3

2.5

2.7

REF

Reference voltage

REF

= 0.5 x V

DDQ

)

1.15

1.25

1.35

Termination voltage

REF

40 mV

REF

+ 40 mV

Input voltage

AC HIGH-level input voltage

All inputs

REF

+ 350 mV

AC LOW-level input voltage

All inputs

REF

350 mV

DC HIGH-level input voltage

All inputs

REF

+ 180 mV

DDQ

+ 0.5 V

DC LOW-level input voltage

All inputs

0.5 V

REF

180 mV

HIGH-level output current

LOW-level output current

Tamb

Operating free-air temperature range

NOTE:
1. Unused control inputs must be held HIGH or LOW to prevent them from floating.

DC ELECTRICAL CHARACTERISTICS

Over recommended operating conditions. Voltages are referenced to GND (ground = 0 V).

LIMITS

SYMBOL

PARAMETER

TEST CONDITIONS

Temp = 0

C to +70

UNIT

MIN

TYP

MAX

I/O supply voltage

= 2.3 V; I

= 18 mA

1.2

= 2.3 V to 2.7 V; I

= 100

0.2

2.3

HIGH level output voltage

= 2.3 V; I

= 8 mA

1.95

2.2

= 2.3 V; I

= 16 mA

1.95

2.1

= 2.3 V to 2.7 V; I

= 100

0.002

0.2

LOW level output voltage

= 2.3 V; I

= 8 mA

0.14

0.35

= 2.3 V; I

= 16 mA

0.30

0.35

CMR

CLK, CLK

Common mode range for reliable performance

0.97

1.53

CLK, CLK

Minimum peak-to-peak input to ensure logic state

360

Data inputs RESET

= 2.7 V ; V

= 1.7 V or 0.8 V

= 1 15V or 1 35V

0.01

Data inputs, RESET

= 2.7 V ; V

= 2.7 V or 0 V

REF

= 1.15V or 1.35V

0.01

CLK CLK

= 2.7 V ; V

= 1.7 V or 0.8 V

= 1 15V or 1 35V

0.05

CLK, CLK

= 2.7 V ; V

= 2.7 V or 0 V

REF

= 1.15V or 1.35V

0.05

REF

= 2.7 V

REF

= 1.15V or 1.35V

0.05

Quiescent supply current
CLK and CLK in opposite

= 2.7 V ; V

= 1.7 V or 0.8 V

CLK and CLK in o

osite

state

= 2.7 V ; V

= 2.7 V or 0 V

NOTES:
1. When CLK and CLK are HIGH, typical I

= 25 mA.

2. All typical values are at V

= 3.3 V and T

amb

= 25

C (unless otherwise specified).

Philips Semiconductors

Product specification

SSTL16877

14-bit SSTL_2 registered driver with
differential clock inputs

2000 Apr 20

TIMING REQUIREMENTS

Over recommended operating conditions; T

amb

= 0

C to +70

C (unless otherwise noted) (see Figure 1)

LIMITS

SYMBOL

PARAMETER

TEST CONDITIONS

= 2.5 V

0.2 V

UNIT

MIN

MAX

clock

Clock frequency

200

MHz

Pulse duration, CLK, CLK HIGH or LOW

1.0

Setup time

Data before CLK

, CLK

0.2

Setup time

RESET HIGH before CLK

, CLK

0.8

Hold time

1.2

SWITCHING CHARACTERISTICS

Over recommended operating conditions; T

amb

= 0

C to +70

C; V

DDQ

= 2.3 2.7 V and V

DDQ

does not exceed V

CC.

Class I, V

REF

= V

DDQ

x 0.5 and C

= 10 pF (unless otherwise noted) (see Figure 1)

LIMITS

SYMBOL

FROM

(INPUT)

(OUTPUT)

= 2.5 V

0.2 V

UNIT

(INPUT)

(OUTPUT)

MIN

MAX

max

Maximum clock frequency

200

MHz

PLH

PHL

CLK and CLK

1.0

3.5

PHL

RESET

2.0

4.0

184/200-pin DDR SDRAM DIMM

SDRAM

The PLL clock distribution device and SSTL registered drivers reduce
signal loads on the memory controller and prevent timing delays and
waveform distortions that would cause unreliable operation

SW00502

CBT3867 (9)

CBT

SDRAM

SSTL16877

PCK877

SSTL16877

BACK SIDE

FRONT SIDE

Philips Semiconductors

Product specification

SSTL16877

14-bit SSTL_2 registered driver with
differential clock inputs

2000 Apr 20

PARAMETER MEASUREMENT INFORMATION

AC WAVEFORMS

PLH

PHL

OUTPUT

REF

CLK

REF

SW00338

Waveform 1. Propagation delay times inverting and

non-inverting outputs

REF

OUTPUT

PHL

SW00402

RESET

Waveform 2. Propagation delay RESET to output.

REF

INPUT

SW00339

Waveform 3. Pulse duration

REF

TIMING INPUT

SW00340

REF

DATA INPUT

Waveform 4. Setup and hold times

TEST CIRCUIT

TEST
POINT

= 10pF or 30pF

= SSTL_2 Class II

= SSTL_2 Class I

NOTES:
C

includes probe and jig capacitance

All input pulses are supplied by generators having the following characteristics:
PRR

10MHz, Z

= 50

, t

1.25ns/V, t

1.25ns/V.

The outputs are measured one at a time with one transition per measurement.
V

= V

REF

= V

DDQ

x 0.5

SW00337

Figure 1. Load circuitry

50pF

500

SW00336

Figure 2.

SW00335

50pF

Figure 3.

Philips Semiconductors

Product specification

SSTL16877

14-bit SSTL_2 registered driver with
differential clock inputs

2000 Apr 20

Definitions

Short-form specification -- The data in a short-form specification is extracted from a full data sheet with the same type number and title. For
detailed information see the relevant data sheet or data handbook.

Limiting values definition -- Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one
or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or
at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended
periods may affect device reliability.

Application information -- Applications that are described herein for any of these products are for illustrative purposes only. Philips
Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or
modification.

Disclaimers

Life support -- These products are not designed for use in life support appliances, devices or systems where malfunction of these products can
reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications
do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application.

Right to make changes -- Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard
cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no
responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these
products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless
otherwise specified.

Philips Semiconductors
811 East Arques Avenue
P.O. Box 3409
Sunnyvale, California 940883409
Telephone 800-234-7381

Date of release: 04-00

Document order number:

9397 750 07086

Philips

Semiconductors

Data sheet
status

Objective
specification

Preliminary
specification

Product
specification

Product
status

Development

Qualification

Production

Definition

[1]

This data sheet contains the design target or goal specifications for product development.
Specification may change in any manner without notice.

This data sheet contains preliminary data, and supplementary data will be published at a later date.
Philips Semiconductors reserves the right to make changes at any time without notice in order to
improve design and supply the best possible product.

This data sheet contains final specifications. Philips Semiconductors reserves the right to make
changes at any time without notice in order to improve design and supply the best possible product.

Data sheet status

[1]

Please consult the most recently issued datasheet before initiating or completing a design.

Part Number SSTL16877