1996 Nov 07
2
Philips Semiconductors
Preliminary specification
Digital Video Encoder (ECO-DENC)
SAA7124; SAA7125
FEATURES
·
Monolithic CMOS 5 V device
·
Digital PAL/NTSC encoder
·
System pixel frequency 13.5 MHz
·
Accepts MPEG decoded data on 8-bit wide input port.
Input data format Cb, Y, Cr etc.
"(CCIR 656)"
·
Four DACs for CVBS (10-bit resolution), RGB (9-bit
resolution) operating at 27 MHz; RGB sync on CVBS
·
Optionally 2 times CVBS and Y, C (all 10-bit resolution)
available simultaneously
·
Closed captioning encoding
·
On-chip YUV to RGB dematrix optionally to be
by-passed for Cr, Y, Cb output on RGB DACs
·
Fast I
2
C-bus control port (400 kHz)
·
Encoder can be master or slave
·
Programmable horizontal and vertical input
synchronization phase, via input pins or auxiliary codes
at MP data port
·
Programmable horizontal sync output phase
·
Internal 100/75 Colour Bar Generator (CBG)
·
Macrovision Pay-per-View copy protection system as
option, also partly used for RGB output.
This applies to SAA7124 only. The device is protected
by USA patent numbers 4631603, 4577216 and
4819098 and other intellectual property rights. Use of
the Macrovision anti-copy process in the device is
licensed for non-commercial home use only.
Reverse engineering or disassembly is prohibited.
Please contact your nearest Philips Semiconductor
sales office for more information
·
Controlled rise and fall times of output syncs and
blanking
·
Down-mode of DACs
·
LQFP64 (V1 devices only), QFP80 or PLCC84
package.
GENERAL DESCRIPTION
The SAA7124; SAA7125 encodes digital YUV video data
to an NTSC or PAL CVBS plus RGB or alternatively to
S-Video and CVBS output.
Optionally, the YUV to RGB dematrix can be by-passed
providing the digital-to-analog converted Cb, Y, Cr signals
instead of RGB.
The circuit accepts CCIR compatible YUV data with
720 active pixels per line in 4 : 2 : 2 multiplexed formats,
for example MPEG decoded data.
It includes a sync/clock generator and on-chip
Digital-to-Analog Converters (DACs).
ORDERING INFORMATION
Note
1. LQFP64 package for V1 devices only.
TYPE
NUMBER
PACKAGE
(1)
NAME
DESCRIPTION
VERSION
SAA7124WP;
SAA7125WP
PLCC84
plastic leaded chip carrier; 84 leads
SOT189-2
SAA7124HZ;
SAA7125HZ
LQFP64
plastic low profile quad flat package; 64 leads; body 10
×
10
×
1.4 mm
SOT314-2
SAA7124H;
SAA7125H
QFP80
plastic quad flat package; 80 leads (lead length 2.35 mm);
body 14
×
20
×
2.8 mm
SOT318-3
1996 Nov 07
3
Philips Semiconductors
Preliminary specification
Digital Video Encoder (ECO-DENC)
SAA7124; SAA7125
QUICK REFERENCE DATA
SYMBOL
PARAMETER
MIN.
TYP.
MAX.
UNIT
V
DDA
analog supply voltage
4.75
5.0
5.25
V
V
DDD
digital supply voltage
4.75
5.0
5.25
V
I
DDA
analog supply current
-
tbf
60
mA
I
DDD
digital supply current
-
tbf
100
mA
V
i
input signal voltage levels
TTL compatible
V
o(p-p)
analog output signal voltages Y, C, CVBS and RGB without load
(peak-to-peak value)
-
2.0
-
V
R
L
load resistance
80
-
-
ILE
LF integral linearity error
-
-
±
4
LSB
DLE
LF differential linearity error
-
-
±
1
LSB
T
amb
operating ambient temperature
0
-
+70
°
C
1996 Nov 07
4
Philips Semiconductors
Preliminary specification
Digital Video Encoder (ECO-DENC)
SAA7124; SAA7125
BLOCK DIAGRAM
full pagewidth
MGG550
8
2
8
I
2
C-BUS
INTERFACE
I
2
C-bus
control
8
I
2
C-bus
control
8
I
2
C-bus
control
8
2
2
I
2
C-bus
control
I
2
C-bus
control
I
2
C-bus
control
8
I
2
C-bus
control
DATA
MANAGER
ENCODER
SYNC CLOCK
OUTPUT
INTERFACE
MODE
RGB
PROCESSOR
internal
control bus
CbCr
Y
C
clock
and timing
D
A
1
84
83
4
37
50
35
36
46
45
44
48
54, 57, 60,
64, 74
53, 75
73
67
62
59
56
65
61
58
55
63, 68
52, 76
77
78
3, 15, 24,
30, 39, 42,
51, 79, 81
5, 14, 22,
29, 38, 41,
49, 80, 82
2, 16 to 21, 23,
40, 43, 47, 66,
70, 72
Y
CbCr
25 to 28,
31 to 34
MP7
to
MP0
RESET
SDA
SCL
SA
RTCI
CDIR
RCV1
RCV2
V
DDDO
(5)
XTALO
XTALI
LLC
V
DDA1
to V
DDA5
V
refH1
V
refH2
CVBS
(1)
V
SSA1
res
res
res
res
RED
(2)
GREEN
(3)
BLUE
(4)
CUR1
CUR2
V
refL1
V
refL2
AP
69, 71
res
SP
n.c.
V
DDD1
to
V
DDD9
V
SSD1
to
V
SSD9
Y
SAA7124
SAA7125
Fig.1 Block diagram; PLCC84.
(1)
Alternatively Y or CVBS.
(2)
Alternatively CHROMA or Cr.
(3)
Alternatively CVBS or Yin.
(4)
Alternatively CVBS or Cb.
(5)
V1 devices only.
1996 Nov 07
5
Philips Semiconductors
Preliminary specification
Digital Video Encoder (ECO-DENC)
SAA7124; SAA7125
full pagewidth
MGG551
8
2
8
I
2
C-BUS
INTERFACE
I
2
C-bus
control
8
I
2
C-bus
control
8
I
2
C-bus
control
8
2
2
I
2
C-bus
control
I
2
C-bus
control
I
2
C-bus
control
8
I
2
C-bus
control
DATA
MANAGER
ENCODER
SYNC CLOCK
OUTPUT
INTERFACE
MODE
RGB
PROCESSOR
internal
control bus
CbCr
Y
C
clock
and timing
D
A
57
56
55
59
21
31
19
20
28
27
26
29
34, 36, 38,
41, 46
33, 47
45
42,
43
39
37
35
40, 44
32, 48
49
50
6, 8, 14,
23, 25, 51,
53, 58
5, 7, 13,
22, 24, 30,
52, 54, 60
Y
CbCr
9 to 12,
15 to 18
MP7
to
MP0
RESET
SDA
SCL
SA
RTCI
CDIR
RCV1
RCV2
V
DDDO
XTALO
XTALI
LLC
V
DDA1
to V
DDA5
V
refH1
V
refH2
CVBS
(1)
V
SSA2
RED
(2)
GREEN
(3)
BLUE
(4)
CUR1
CUR2
V
refL1
V
refL2
AP
SP
V
DDD1
to
V
DDD9
V
SSD1
to
V
SSD8
Y
SAA7124
SAA7125
2
Fig.2 Block diagram; TQFP64, V1
devices only.
(1)
Alternatively Y or CVBS.
(2)
Alternatively CHROMA or Cr.
(3)
Alternatively CVBS or Yin.
(4)
Alternatively CVBS or Cb.
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