Philips Semiconductors

Product specification

SA1620

Low voltage GSM front-end transceiver

1997 May 22

853-1784 18066

DESCRIPTION

The SA1620 is a combined receive (Rx) and transmit (Tx) front-end
for GSM cellular telephones. The receive path contains two low
noise amplifiers (LNA1 and LNA2) with four switchable attenuation
steps. A Gilbert Cell mixer in the receive path down-converts the
RF signal to a first IF of 70 to 500 MHz. A second Gilbert Cell in the
transmit path transposes a GMSK or phase modulated IF to RF by
image reject mixing and has a fixed IF of 400 MHz. A buffered LO
signal is fed to Rx and Tx mixers. Rx or Tx path or the entire circuit
may be powered-down.

FEATURES

Excellent noise figure: <2dB for the LNAs at 950MHz

LNAs matched to 50

with external matching components

LNAs with gain control, 59dB dynamic range in four discrete steps

LNA gain stability

0.5dB within -40 to 85

Feedthrough attenuation LNA1 to Rx mixer

35dB

Tx power adjustable from -3 to +12dBm by external resistor

Direct supply: 2.7V to 5.5V

Battery supply voltage V

BATT

= 3.3V to 7.5V or direct supply

Two DC regulators programmable for 3.0V, 3.4V, 3.7V or 5.1V

Low current consumption: 28mA for Rx or 59mA for Tx

Fully compatible with SA1638 GSM IF Digital I/Q circuit

APPLICATIONS

900MHz front end for GSM hand-held units

Portable radio, TDMA systems

PIN CONFIGURATION

LQFP Package

VBATT

PON

GNDREG1

VREG1

VREGF2

VREG2

GNDREG2

CON1

LO INX

LO IN

VCCL2

IN2

GNDL2

GNDL2A

OUT2

INM

INMX

COMP2

48PIN LQFP

13 14

15 16 17 18 19

21 22 23 24

COMP1

VCCBM

CON2

GNDTx2

VccL1

OUT1

GNDL1A

GNDL1

IN1

RETx

GNDTx3

TxO

Tx0X

GNDTx4

PDTx

PONBUF

GNDBM

PONRx

GND1

RxIF

GND2

TxIF

TxIFX

GND3

VccTx1

GNDTx1

VccTx2

RxIFX

SR00127

Figure 1.

Pin Configuration

ORDERING INFORMATION

DESCRIPTION

TEMPERATURE RANGE

ORDER CODE

DWG #

48-Pin Thin Quad Flat Pack (TQFP)

-40 to +85

SA1620BE

SOT313-2

RECOMMENDED OPERATING CONDITIONS

SYMBOL

PARAMETER

RATING

UNITS

CCXX

Supply voltages

2.7 to 5.5

BATT

Battery voltage

3.3 to 7.5

Operating ambient temperature range

-40 to +85

Philips Semiconductors

Product specification

SA1620

Low voltage GSM front-end transceiver

1997 May 22

PIN DESCRIPTIONS

Pin No.

Pin Name

Description

DC Regulators

GND1

Ground of regulator supply

GND2

Ground of regulator supply

GND3

Ground of regulator supply

CON2

Control 2, voltage select for regulator 1
and 2

CON1

Control 1, voltage select for regulator 1
and 2

GNDREG2

Ground of regulator 2

VREG2

Output of regulator 2

VREG2F2

Feedback of regulator 2

VREG1

Output of regulator 1

GNDREG1

Ground of regulator 1

PON

Power-on input of regulators

BATT

Input of regulator 1 and 2

Rx Path

Positive supply for LNA2

IN2

Input LNA2

GNDL2

Ground L2 for LNA2

GNDL2A

Ground L2A for LNA2

OUT2

Output LNA2

Attenuation select B for LNA1 and LNA2

Attenuation select A for LNA1 and LNA2

INM

RF input for Rx mixer, open emitter

INMX

Inverse RF input for Rx mixer, open
emitter

COMP2

Capacitor for bias stabilization

COMP1

Capacitor for bias stabilization

for Rx Bias and Rx mixer

Pin No.

Pin Name

Description

GNDBM

Ground for Rx Bias and Rx mixer

PONRx

Power on input for Rx bias supply

RxIF

IF output, open collector

RxIFX

Inverse IF output, open collector

IN1

Input to LNA1

GNDL1

Ground L1 for LNA1

GNDL1A

Ground L1A for LNA1

OUT1

Output LNA1

Positive supply for LNA1

Tx Path

TxIF

IF input for Tx

TxIFX

Inverse IF input for Tx

Tx1

Positive supply for Tx input

GNDTx1

Ground for Tx input

Tx2

Positive supply for LO and Tx input

GNDTx2

Ground for LO and Tx input

PDTx

Power down Tx input

GNDTx4

Ground for Tx output

TxOX

Inverse Tx output, open collector

TxO

Tx output, open collector

GNDTx3

Ground 1 for Tx output side

RETx

Reference resistor for Tx output current

Elements for Tx and Rx Path

LO IN

Input for Local Oscillator signal

LO INX

Inverse input for LO or AC ground

PONBUF

Power on first stage LO input buffer and
bias

NOTES:
1. Device is ESD sensitive. There are no ESD protection diodes at Pins 16, 17, 40 and 41. Thus, open-collector outputs may have increased

DC voltage or higher AC peak voltage.

2. Pins 15, 18 and 21 are connected to each other and to a separate ground in REG1 and REG2.
3. Pins 23, 25, 42 and 39 are connected to each other and to the Tx path, LO buffer and associated bias supplies.
4. Pins 22 and 24 are connected to each other providing a sense input. They are also connected to the Tx path, LO buffer and associated bias

supplies.

5. Pins 30 and 34 are not internally connected. They must be connected to external grounds.
6. Pins 48, 1, and 12 are not internally connected and have no ESD protection diodes between them. Power may be saved by connecting

L1 and IN1 or V

L2 and IN2 to ground if LNA1 or LNA2 is not needed.

Philips Semiconductors

Product specification

SA1620

Low voltage GSM front-end transceiver

1997 May 22

ABSOLUTE MAXIMUM RATINGS

SYMBOL

PARAMETER

RATING

UNITS

CCXX

Supply voltages

-0.3 to +6.0

BATT

Battery voltage

-0.3 to +8.0

Voltage applied to any other pin

-0.3 to (V

CCXX

+0.3)

Tx1,2 pins to V

-0.3 to +1

Any GND pin to any other GND pin

Power dissipation, T

= 25

C (still air)

800

JMAX

Maximum operating junction temperature

150

MAX

Maximum power input/output

+20

dBm

STG

Storage temperature range

65 to +150

TXO

, V

TXOX

Positive RF peak voltage at Tx outputs

RXIF

, V

RXIFX

Positive IF peak voltage at Rx mixer outputs

NOTE:
1. Maximum junction temperature is determined by the power dissipation is determined by the operating ambient temperature and the thermal

resistance,

. 48-pin TQFP:

= 67

C/W.

DC REGULATORS

Two low drop regulators (REG1 and REG2) are included on the chip
and may be used to deliver the supply voltage of the main circuitry
(e.g., 3V) out of the battery (at V

BATT

= 3.3 to 7.5V) as shown in

Figure 4 and in Table 1.

REG1 is intended to supply, at least, the internal functions of the
SA1620. Both regulators may also be used for external circuitry.
For this application, different voltages may be programmed as
shown in Table 1.

The transmitter supply pins (V

Tx1,2) also operate as a sensor

connection in the feedback loop of REG1 and must be externally
connected to pin VREG1. For REG2, the sensor pin VREGF2 must
be connected to VREG2.

All ground pins are internally bonded to the header except for pins
GNDL1, GNDREG1 and GNDREG2.

When both regulators are not used, connect pins V

BATT

, PON,

CON1, CON2, VREG1, VREG2 and VREG2F2 to ground.

Table 1.

DC Reg Output Voltage Control Pins

CON1

CON2

VREG1

VREG2

UNITS

3.4

3.7

5.1

10%

NOTES:
1. Logic levels at CON1 and CON2:

H Open circuit. Pin must not be connected externally.
Logic high level supplied on chip.
L Connected to ground.

2. Currents at CON1 and CON2:

H 0

L (PON = H) 50

L (PON = L) <1

Philips Semiconductors

Product specification

SA1620

Low voltage GSM front-end transceiver

1997 May 22

Table 2.

DC Regulators

SYMBOL

PARAMETER

TEST

LIMITS

UNITS

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

BATT

Common positive input voltage at both regulators

VREG1+0.3

VREG1,

VREG2

Output voltages of regulators 1 and 2

BATT

= 3.3V

2.85

3.15

INT1

Internal current of REG1 in power-on mode

4 + I

VREG1

/10

INT2

Internal current of REG2 in power-on mode

2.5 + I

VREG2

/10

INT01

, I

INT02

Internal current in power-down mode

<15

VREG1MAX

Max output current at VREG1

100

VREG2MAX

Max output current at VREG2

BATT

= 3.3V, I

REG1

= 0.1mA

0.03

BATT

= 3.3V, I

REG1

= 100mA

kHz

BATT

= 7.5V, I

REG1

= 100mA

100kHz

10MHz

REG

100MHz

400MHz

NOTES:
1. Power-on pin of Regulator 1 and 2: PON
2. Input currents at PON: <1

A. There are no pull-up or pull-down resistors.

3. Feedthrough attenuation from the logic input PON to the outputs VREG1 and VREG2:

40dB.

4. Recommended load capacitors: C529 = C530 = 1

F to ground with series resistance

0.1

See Figure 4. Additional optional capacitor

1000

F with series resistance

5. At T

150

C a thermal switch reduces the output current.

6. Typical open loop bandwidths of regulator 1 at V

REG1

= 3V and C529 = 1

7. Feedthrough attenuation (at the indicated frequency f) from the input V

BATT

to the outputs V

REG1

and V

REG2

at V

BATT

= 3.3V,

(CON1=CON2=L)

Philips Semiconductors

Product specification

SA1620

Low voltage GSM front-end transceiver

1997 May 22

DC ELECTRICAL CHARACTERISTICS

CCxxx

= +3V, T

= 25

C; unless otherwise stated.

SYMBOL

PARAMETER

TEST CONDITIONS

LIMITS

UNITS

SYMBOL

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNITS

Transmitter

VCC

Total supply current

Transmit mode

546

= 240

External resistor

240

Internal supply at pin RETx

Tx1,2 = 2.7V

0.43

Internal supply at pin RETx

Tx1,2 = 5.5V

0.45

Current at pin RETx

R546 = 240

, V

Tx1,2 = 2.7V

1.7

Current at pin RETx

R546 = 240

, V

Tx1,2 = 5.5V

1.8

Low noise amplifiers

VCC

Current at pin V

G1hi mode

2.5

3.5

VCC

Current at pin V

G2hi mode

2.5

3.5

Receiver

VCC

Total supply current

Receive mode

546

= 240

Regulators

Vreg1

Voltage @ 100mA load

Con1 Con2

L L

2.85

3.0

3.15

L H

3.23

3.4

3.57

H L

3.515

3.7

3.885

H H

4.61

5.1

5.61

Vreg2

Voltage @ 30mA load

Con1 Con2

L L

2.85

3.0

3.15

L H

3.23

3.4

3.57

H L

3.515

3.7

3.885

H H

4.61

5.1

5.61

Logic levels

Logic 1 level

BUF, PDTx, P

Rx, A, B

2.0

CCBM

Logic 1 level

2.0

BATT

Logic 0 level

0.8

Input logic current

Input logic capacitance

1.7

NOTES:
1. The output current I

TXO

+ I

TXOX

is adjustable by the external resistor R546. I

TXO

+ I

TXOX

= 10 * I

R546

, I

R546

= V

/R546,

2. Thresholds are independent of supply voltages. Thus the SA1620 is compatible with SA1638 and with the power down inputs of usual

external voltage regulators.

3. P

logic 1 max is V

BATT

Philips Semiconductors

Product specification

SA1620

Low voltage GSM front-end transceiver

1997 May 22

AC ELECTRICAL CHARACTERISTICS

CCXX

= +3V, T

= 25

C; RF = 940MHZ; IF=400MHz, f

=RF + IF; LO = 15dBm; unless otherwise stated.

SYMBOL

PARAMETER

TEST CONDITIONS

LIMITS

UNITS

SYMBOL

PARAMETER

TEST CONDITIONS

MIN

-3

TYP

MAX

UNITS

Low Noise Amplifier LNA1

G1hi mode

9.4

10.6

Gain

G1hi mode, RF = 1800MHz

2.5

G1lo mode

IP3

G1lo mode

S /

Gain temperature sensitivity

G1hi mode

0.003

dB/

Gain temperature sensitivity

G1lo mode

0.0140

dB/

CCL1

Gain/voltage sensitivity

0.1

dB/V

Gain frequency variation

0.01

dB/MHz

Reverse isolation

G1hi mode

Input match

Output match

-1dB

Input 1dB gain compression

G1hi mode

15.5

12.5

dBm

IIP3

Input third order intercept

5.5

2.5

dBm

IIP3/

Input third order intercept

0.011

dB/

Noise figure

1.9

Turn-on time

OFF

Turn-off time

0.5

Low Noise Amplifier LNA2

G2hi mode

G2hi mode, RF = 1800MHz

1.5

Gain

G2lo1 mode

8.5

7.5

6.5

G2lo2 mode

22.5

21.5

20.5

G2lo3 mode

28.5

G2lo1 mode

IP3

G2lo2 mode

G2lo3 mode

S /

Gain temperature sensitivity

G2hi mode

0.003

dB/

Gain temperature sensitivity

G2lo1,2,3 modes

0.014

dB/

CCL2

Gain/voltage sensitivity

0.1

dB/V

Gain frequency variation

0.01

dB/MHz

Reverse isolation

G2hi mode

Input match

Output match

-1dB

Input 1dB gain compression

G2hi mode

dBm

IIP3

Input third order intercept

dBm

IIP3/

Input third order intercept

0.019

dB/

Noise figure

Turn-on time

OFF

Turn-off time

0.5

Philips Semiconductors

Product specification

SA1620

Low voltage GSM front-end transceiver

1997 May 22

AC ELECTRICAL CHARACTERISTICS (continued)

SYMBOL

PARAMETER

TEST CONDITIONS

LIMITS

UNITS

SYMBOL

PARAMETER

TEST CONDITIONS

MIN

-3

TYP

MAX

UNITS

Rx Mixer

Power conversion gain

7.5

+8.5

9.5

Power conversion gain

RF = 1800MHz

Mixer input match at ports INM
and INMX

SSB combined noise figure

-1dB

Input 1dB compression

7.3

dBm

IIP3

Input third order intercept

dBm

IIP3/

Input third order intercept

0.005

dB/

IIP2

Input second order intercept

dBm

RFM-IF

RF feedthrough

400MHz

LOfloor

LO floor feedthrough

400MHz

LO-IF

LO feedthrough to IF

1.3GHz

LO-RFM

LO to mixer input feedthrough

1.3GHz

dBm

LO-RF1

LO to RF LNA1 input
feedthrough

1.3GHz

dBm

LNA1-2

LNA1 output to LNA2 input
feedthrough

400MHz

1290-1760MHz

41
26

LNA2-M

LNA2 output to mixer input
feedthrough

1290-1760MHz

LNA1-M

LNA1 output to mixer input
feedthrough

400MHz

1290-1760MHz

50
35

Receiver

Cascaded gain

A,B Logic Level

H,H

23.5

26.5

28.5

30.5

33.5

H,L

L,H

L,L

+28

Input IP3 @ RFin=40dBm

H,H

dBm

LO input

Input impedance
(each single-ended input)

1.3GHz

35-j97

Input power

dBm

SAT

Transistor saturation limit,
max input amplitude

500

Tx IF input

Input impedance

400MHz

Input power

dBm

Tx RF output

OUT

R546 = 240

Tx1,2 = 3V

7.5

8.5

9.5

dBm

NOTES:
1. Due to our automatic test equipment accuracy and repeatability test limits may not reflect the ultimate device performance. Standard

deviations are calculated from characterization data.

2. If the LNA1 is not needed, connect pin V

L1 and IN1 to GND. If the LNA2 is not needed, connect pin V

L2 and IN2 to GND.

3. Simple L/C elements are needed to achieve specified return loss.
4. The mixer RF inputs (emitters of a Gilbert Cell) may be driven by a symmetrical matching network.
5. Input symmetry suppression is such that the product 6*RF4*LO is to be suppressed by at least 66dB relative to the wanted IF output when

the input to the mixer is at 32dBm.

6. LNA1, LNA2, and the mixer are cascaded. 0 db insertion loss between LNA1 out to LNA2 in and LNA2 out to mixer in.
7. Lowering the LO input power (P

) from TYP to MIN will lower the mixer gain (PG

) by 1 dB.

Philips Semiconductors

Product specification

SA1620

Low voltage GSM front-end transceiver

1997 May 22

Table 3.

Power-Down and Tx/Rx Control Logic

No.

PONBUF

PDTX

PONRX

MODE

RESULT

Standby

LO buffer active, Tx and Rx path inactive

Transmit

LO buffer active, Tx path active, Rx path inactive (LNAs + mixer)

Receive

Tx path inactive, LO buffer and Rx path active (LNAs + mixer)

Calibrate

Tx path and Rx LNAs inactive, LO buffer and Rx mixer active

Power-Down

Tx- and Rx-path, LO buffers and Bias inactive

NOTES:
1. Logic levels of PONBUF, PDTx and PONRx: TTL, see DC Electrical Characteristics.
2. Logic levels / polarities are compatible with Philips Semiconductors Power Amp Controller PCA5075 and synthesizers UMA1019 or SA8025.
3. First stage of LO buffer and parts of bias supply are powered on by PONBUF.
4. Tx- or Rx-paths may be activated for special timeslots. Lines 1 and 4 show options to support DC offset calibrations at baseband mixers,

following in the receiver chain (SA1638).

Table 4.

Gain Control Logic for LNA1 and LNA2

INPUT

ATTENUATION

GAIN

POWER CONSUMPTION

STEP

LNA1

LNA2

LNA1

LNA2

G1hi

G2hi

G1hi

G2lo1

off

G1hi

G2lo2

off

G1lo

G2lo3

off

NOTES:
1. Logic levels of a and b: TTL
2. For values of G1hi and G1lo, G2hi, G2lo1, G2lo2 and G2lo3 see LNA1 and LNA2 AC Electrical Characteristics.

Philips Semiconductors

Product specification

SA1620

Low voltage GSM front-end transceiver

1997 May 22

Overview of Dual GSM/PCN Architecture

The SA1620 RF front-end and SA1638 IF transceivers form a dual
conversion architecture which uses a common IF and standard I/Q
baseband interface for both transmit and receive paths. This
approach avoids the screening difficulties of direct modulation in the
transmit direction and the mass production and practical
performance issues related to direct conversion in the receive
direction. The time division multiplex nature of the GSM system
permits integration of the transmit and receive functions together on
the one RF and one IF chips. This simplifies the distribution of local
oscillator signals, maximizes circuitry commonality, and reduces
power consumption.

The SA1620 and SA1638 allow considerable flexibility to optimize
the transceiver design for particular price/size/performance
requirements, through choice of appropriate RF and IF filters. The
receive IF may be chosen freely in the range 70500MHz, while the
transmit IF is fixed to 400 MHz. The comparison frequency of the
SA1638 PLL is high in order to provide fast switching time.

With suitable choice of the IF, an identical SA1638 IF receiver
design can be used for both 900MHz GSM and 1800MHz PCN
(DCS1800) equipment.

General Benefits/Advantages

2.7V operation. Compatible with 3V digital technology and
portable applications. (Higher voltage operation also possible, if
desired.)

Excellent dynamic range. The availability of two LNAs allows
flexibility in receiver dynamic design for portable and mobile GSM
spec. applications with appropriate filters. If for a particular
application a GaAs or discrete front-end is desired, one of the
LNAs can be left unpowered. The placing of the AGC gains
switches at the front means that for most of the time some
attenuation will be inserted, further increasing typical dynamic
performance beyond that specified by GSM.

High power transmit output driver, delivering +8.5dBm output.
This is sufficient to drive a filter and power amplifier input, without
a driver amplifier. To avoid unnecessary current consumption the
output power can be reduced, if not required, by appropriate
choice of an external resistor.

DC offsets generated in the receive channel are independent of
the AGC setting, and correctable by software to prevent erosion of
signal handling dynamic range by DC offsets. Independence of
DC from AGC setting is achieved by putting the gain switches in
the RF front-end.

Minimal high-quality filter requirements. As a result of the
integration in the SA1638 of high quality channel selectivity filters,
only sufficient filtering is needed in the receive path to provide
blocking protection for the second mixers. This reduces receiver
cost and size.

Operation at a high IF allows RF image reject filters to be relaxed.
For example, at a 400MHz IF, the natural gain roll-off in the LNAs
and mixer suppresses the image signal in the 1800MHz band by
typically 28dB below the desired 900MHz band signal.

Receive Path

Multiple LNAs allow the flexibility to exploit the best choice of
currently available filters (on performance, size, or cost grounds).
This approach is preferable to a single high-gain stage as the stray
cross-coupling effects between pins remain manageable. In a single
stage amplifier this would limit the amount of rejection of out-of-band
signals that could be achieved, and would also limit the amount of
AGC attenuation that could be practically implemented.

The LNAs are powered up only when PONBUF, PDTx and PONRx
are high, to allow a high degree of battery economy. If greater
sensitivity is required for an application, an external preamplifier
circuit can be used instead of LNA1, and LNA1 left unconnected.

A special mode is provided with just the IF output related circuitry
active in order to allow calibration of the DC offset at the SA1638
baseband receive outputs. This offset contains a contribution due to
coupling effects between the second local oscillator and the IF
circuitry, and therefore the receiver is set up in the receive state (but
with incoming signals excluded) to allow accurate offset calibration.

Gain Control

Gain control is implemented in the SA1620 RF front-end. This
avoids the disruption of the DC offset at the baseband IQ outputs
that is typically caused by changes in the AGC. The SA1620 and
SA1638 are designed so that the GSM dynamic range requirements
can be met with the AGC remaining on the maximum gain setting.

These gain steps scale the dynamic range of the received signal
(e.g., 90dB for GSM) into the dynamic range of the baseband
processing device.

The absolute gain tolerances may be measured together with the
attenuation tolerances of external filters during production of the
receiver equipment. After software calibration switching from one
dynamic range to another will cause only minor errors.

Tx Path

TXIF and TXIFX are differential IF inputs for phase modulated
signals (e.g., GMSK). There is an IF level control loop which
provides a constant amplitude to an image reject up mixer. Thus,
this mixer operates linearly in the IF path, independent of IF level
tolerances.

The single sideband up mixer is sufficient in quadrature to achieve
the typical performance indicated in Table 6 over an IF range of 250
to 500MHz. The mixer is operating in switching mode by well
matched 0

and 90

LO signals, optimized for 1.1 to 1.5GHz.

The Tx output stage operates in switching mode. Thus, parasitic
AM at the IF is not transferred. The outputs TXO and TXOX may be
used symmetrically or single-ended. Some spurious emissions will
be very low when a symmetrical output signal is used.

OUT

= R

6.25V

Pin 40

)

Pin 41

)

R546

)

according to Figure 4 and I

R546

546

according to DC Electrical

Characteristics. P

OUT

is adjustable with R546 and is accurate to

within

1dB over the full voltage range 2.7 to 5.5V, and

0.5dB from

a given supply voltage. The absolute limit of the negative peak
voltage swing at pins TxO and TxOX is V

SAT

= V

Tx1,2 1V. The

absolute limit of the positive peak voltage is +6V.

Philips Semiconductors

Product specification

SA1620

Low voltage GSM front-end transceiver

1997 May 22

420

VCCL2

IN2

GNDL2

GNDL2A

OUT2

INM

INMX

COMP2

COMP1

VCCBM

GNDBM

PONRx

GND1

RxIF

RxIFX

GND2

TxIF

TxIFX

GDN3

VccTx1

GNDTx1

VccTx2

GNDL1A

GNDL1

IN1

RETx

GNDTx3

TxO

TxOX

GNDTx4

OUT1

VccL1

VBA

GNDREG1

VREG1

VREGF2

GNDREG2

CON1

LOINX

LOIN

CON2

GNDTx2

LNA1_Out

LNA_In

c=33p

C574

C575

c=33p

C573

r=100

R651

605

C650 c=33p

940

C610

c=3.9p

I=56n

L612

TMXR_Out

C613 c=33p

r=240

R546

690

Vcc/Gnd

C61

c=33p

V503

vdc=7.5

Vbatt

C635

c100n

C609 c=3.9p

335

c=33p

C533

C534

c=33p

C339 c=1n

LNA2_In

L648

I=56n

C336

c=33p

Vcc/Gnd

C644

c=33p

C631

c=4.7p

180

R641

r=100

C643

c=33p

c=10n

C380

c=10n

C645

C535

c=100n

RMXR+Out

C626

c=3.3p

340

C619

c=33p

C628

c=100n

Vcc/Gnd

C622

c=10p

350

C618

c=8.2p

C623

c=10p

L624

I=22n

L627

I=56n

350

TMXR_In

gnd

C539

c=33p

C615

c=10p

L617 I=22n

C620 c=3.3p

C527

c=100n

c=10u

C636

C528

c=100n

Vbatt/Gnd

Vcc

VRegF2

C=1u

C529

(ceramic!!!)

C530

c=1u

(ceramic!!!)

Open/Gnd

LO_In

C565

c=33p

C564

C=33p

Open/Gnd

Vcc/Gnd

LNA2_Out

RMXR_In

890

PDTx

PONBUF

VREG2

10 mils wide, xxx mils long on 31 mils

thick FR4 substrate.

1620

8/12/96

xxx

SR01332

PON

c:1p

650

340

Figure 4.

Application Circuit

Philips Semiconductors

Product specification

SA1620

Low voltage GSM front-end transceiver

1997 May 22

APPLICATION CIRCUIT

LNA

Impedance Match: Intrinsic return losses at the input and output
ports are 7dB and 11dB, respectively. However, since long and
narrow traces are always needed to fan out the pins, the user can
adjust the traces' dimensions so that only one shunt capacitor at the
input is required to achieve excellent impedance match for both
ports. If the user wants to skip the input matching network for
simplicity, then roughly 0.7dB gain would be lost, although it benefits
the system IP3.

Noise Match: The LNA1 and LNA2 can achieve 1.9dB and 2.0dB
noise figure, respectively, when S11 = 11dB. Further improvement
in S

will slightly decrease NF and increase S

Gain Control: The LNA1 can be switched to the attenuation mode,
while LNA2 has three attenuation modes to choose from. When
gain and loss modes from two LNAs are combined, there will be a
total dynamic range of 59dB in the RF block; 3.0V operation is
preferred to achieve better IP3 for both LNA1 and LNA2.

Temperature Compensation: Both LNAs have a builtin temperature
compensation scheme to reduce the gain drift rate to 0.003dB/

from 40

C to +85

Supply Voltage Compensation: Unique circuitry provides gain
stabilization over wide supply voltage range. The gain changes no
more than 0.5dB when V

increases from 2.7V to 5.5V.

Mixer

Mixer Input Match: The mixer is configured for best gain, noise
figure and spurious response. The user must supply an external,
patented resonant balun to provide the differential drive as well as
the impedance match (embedded in). Because the mixer consists
of two singlebalance mixers, whose inputs are connected in
parallel instead of in series, the differential and commonmode
impedances are equal.

Output Match: The mixer output circuit also features an external,
patented resonant balun to optimize the conversion gain and noise
figure. The principal IF operating frequency is 400 MHz.

LO Drive: The internal buffer only requires 15dBm from an external
source. Furthermore, the transmitter incorporates an integrated
SSB upconverter that consists of narrowband phase shifters at
1300MHz (LO side) and 400MHz (IF side), so the LO frequency is

recommended to be the receiver band plus 400MHz. Additionally,
the LO leakage at the input of LNA1 is extremely low, which can
greatly alleviate the LO reradiation problem.

Outband Blocking: For optimum performance, passive R/C network
is added at each input of the mixer. The resistors degenerate the
noise conversion gain, while the capacitors preserve the gain and
noise figure at RF frequencies.

Noise Figure and IP3: The resonant balun is superior to the
conventional balun in terms of insertion loss, size and cost. As a
result, the user can expect excellent SSB noise figure and gain
which is 10dB and 8.5dB, respectively, at 400MHz IF. And the
associated input IP3 is 2dBm typically. In the meantime, due to the
internal LO buffer, the noise figure and IP3 are not sensitive to the
LO levels. As discussed in the LNA Impedance Match session, a
better system IP3 can be achieved (if necessary) through LNAs'
gain reduction.

Transmitter

The resonant balun is applied again to maximize the gain and output
power, for a given bias current. Typical output power is 8.5dBm
when the input level exceeds 25dBm.

LO Input

The LO input is used in Tx- and in Rx-mode.

Only one synthesizer PLL is necessary to supply the LO input with
different frequencies in Tx and Rx timeslots.

The LO input buffer should only be set in power-down mode
together with the PLL. As further buffering is included on chip there
will be no influence on the PLL in active mode when the SA1620 Rx-
or Tx-path is power On or Off. Current consumption can thus be
saved by powering on the Rx- and Tx-circuitry just before it is
required, without disruption of the LO circuitry. LO input pins LO IN
and LO INX may be used single-ended or symmetrically.

Table 5.

GSM/DSC1800 Frequency Specification

(GSM 05.05, Version 4.2.0, April 1992) Mobile Stations Frequency
Bands

GSM

EGSM

DCS1800

Unit

890 to 915

880.2 to 915

1710 to 1785

MHz

935 to 960

925.2 to 960

1805 to 1880

MHz

Philips Semiconductors

Product specification

SA1620

Low voltage GSM front-end transceiver

1997 May 22

Table 6.

Measured Tx Output Frequency and Tx Mixer Products

IF=400MHz, symmetrical load at pins TxO, TxOX.

SPECTRAL LINE f=n*IF+m*LO MHz

RELATIVE POWER OF SPECTRAL

No.

LO =

Order

LINE

REMARKS

1280MHz

1300MHz

1315MHz

min dBc

typ dBc

max dBc

100

115

160

200

230

320

300

285

400

480

500

515

560

600

630

720

700

685

800

Note 2

880

900

915

Note 1

960

1000

1030

Note 3

1020

1100

1185

1200

1280

1300

1315

1360

1400

1430

1440

1500

1545

1600

1680

1700

1715

Notes 4 and 5

1760

1800

1830

Note 3

1840

1900

1945

Note 3

2000

2080

2100

2115

2160

2200

2230

2240

2300

2345

2400

2480

2500

2515

2560

2600

2630

2LO

NOTES:
1. Desired Tx output frequency LOIF corresponding to EGSM Tx band in Table 5.
2. (LO+IF)(LOIF) = 2 * IF
3. See Rx bands in Table 5.
4. LO+IF = mixer image frequency
5. See Tx bands in Table 5.

Philips Semiconductors

Product specification

SA1620

Low voltage GSM front-end transceiver

1997 May 22

Philips Semiconductors and Philips Electronics North America Corporation reserve the right to make changes, without notice, in the products,
including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips
Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright,
or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask
work right infringement, unless otherwise specified. Applications that are described herein for any of these products are for illustrative purposes
only. Philips Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing
or modification.

LIFE SUPPORT APPLICATIONS
Philips Semiconductors and Philips Electronics North America Corporation Products are not designed for use in life support appliances, devices,
or systems where malfunction of a Philips Semiconductors and Philips Electronics North America Corporation Product can reasonably be expected
to result in a personal injury. Philips Semiconductors and Philips Electronics North America Corporation customers using or selling Philips
Semiconductors and Philips Electronics North America Corporation Products for use in such applications do so at their own risk and agree to fully
indemnify Philips Semiconductors and Philips Electronics North America Corporation for any damages resulting from such improper use or sale.

This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips
Semiconductors reserves the right to make changes at any time without notice in order to improve design
and supply the best possible product.

Philips Semiconductors
811 East Arques Avenue
P.O. Box 3409
Sunnyvale, California 940883409
Telephone 800-234-7381

DEFINITIONS

Data Sheet Identification

Product Status

Definition

Objective Specification

Preliminary Specification

Product Specification

Formative or in Design

Preproduction Product

Full Production

This data sheet contains the design target or goal specifications for product development. Specifications
may change in any manner without notice.

This data sheet contains Final Specifications. Philips Semiconductors reserves the right to make changes
at any time without notice, in order to improve design and supply the best possible product.

Philips

Semiconductors

Part Number SA1620