General description

The PCK9448 is a 3.3 V or 2.5 V compatible, 1 : 12 clock fan-out buffer targeted for high
performance clock tree applications. With output frequencies up to 350 MHz and output
skews less than 150 ps, the device meets the needs of most demanding clock
applications.

The PCK9448 is specifically designed to distribute LVCMOS compatible clock signals up
to a frequency of 350 MHz. Each output provides a precise copy of the input signal with
near zero skew. The output buffers support driving of 50

terminated transmission lines

on the incident edge: each is capable of driving either one parallel terminated or two
series terminated transmission lines.

Two selectable independent clock inputs are available, providing support of LVCMOS and
differential LVPECL clock distribution systems. The PCK9448 CLK_STOP control is
synchronous to the falling edge of the input clock. It allows the start and stop of the output
clock signal only in a logic LOW state, thus eliminating potential output runt pulses.
Applying the OE control will force the outputs into high-impedance mode.

All inputs have an internal pull-up or pull-down resistor preventing unused and open inputs
from floating. The device supports a 2.5 V or 3.3 V power supply and an ambient
temperature range of

C to +85

Features

12 LVCMOS compatible clock outputs

Selectable LVCMOS and differential LVPECL compatible clock inputs

Maximum clock frequency of 350 MHz

Maximum clock skew of 150 ps

Synchronous output stop in logic LOW state eliminates output runt pulses

High-impedance output control

3.3 V or 2.5 V power supply

Drives up to 24 series terminated clock lines

amb

C to +85

Available in LQFP32 package

Supports clock distribution in networking, telecommunications, and computer
applications

PCK9448

3.3 V/2.5 V LVCMOS 1 : 12 clock fan-out buffer

Rev. 01 -- 29 November 2005

Product data sheet

9397 750 12534

Product data sheet

Rev. 01 -- 29 November 2005

3 of 20

Philips Semiconductors

PCK9448

3.3 V/2.5 V LVCMOS 1 : 12 clock fan-out buffer

Pinning information

5.1 Pinning

5.2 Pin description

Fig 2.

Pin configuration for LQFP32

PCK9448BD

CLK_SEL

GND

CCLK

PCLK

CLK_STOP

GND

Q11

GND

Q10

GND

002aaa721

Table 2:

Pin description

Symbol

Pin

Type

Description

CLK_SEL

clock input select

CCLK

alternative clock signal input

PCLK

clock signal input

PCLK

clock signal input, active LOW

CLK_STOP

clock output enable/disable, active LOW

output enable/disable (high-impedance, 3-state)

Q0 to Q11

31, 29, 27,
25, 23, 21,
19, 17, 15,
13, 11, 9

clock outputs

GND

8, 12, 16,
20, 24, 28,
32

ground

negative power supply (GND)

7, 10, 14,
18, 22, 26,
30

power

Positive power supply for I/O and core. All V

pins must be

connected to the positive power supply for correct operation.

9397 750 12534

Product data sheet

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4 of 20

Philips Semiconductors

PCK9448

3.3 V/2.5 V LVCMOS 1 : 12 clock fan-out buffer

Functional description

Refer to

Figure 1 "Functional diagram of PCK9448"

6.1 Function table

[1]

OE = 0 will high-impedance 3-state all outputs independent of CLK_STOP.

Limiting values

Characteristics

8.1 General characteristics

[1]

200 pF capacitor discharged via a 10

resistor and a 0.75

H inductor.

[2]

100 pF capacitor discharged via a 1.5 k

resistor.

Table 3:

Function table

Control

Default

Logic 0

Logic 1

CLK_SEL

PECL differential input selected CCLK input selected

outputs disabled
(high-impedance state)

[1]

outputs enabled

CLK_STOP

outputs synchronously stopped
in logic LOW state

outputs active

Table 4:

Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134).

Symbol

Parameter

Conditions

Min

Max

Unit

supply voltage

0.3

+3.9

input voltage

0.3

+ 0.3

output voltage

0.3

+ 0.3

input current

output current

stg

storage temperature

+125

Table 5:

General characteristics

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

termination voltage
(output)

0.5V

esd

electrostatic discharge
voltage

Machine Model

[1]

200

Human Body Model

[2]

2000

latch(prot)

latch-up protection
current

200

power dissipation
capacitance

per output

input capacitance

inputs

4.0

9397 750 12534

Product data sheet

Rev. 01 -- 29 November 2005

5 of 20

Philips Semiconductors

PCK9448

3.3 V/2.5 V LVCMOS 1 : 12 clock fan-out buffer

8.2 Static characteristics

[1]

ICR

(DC) is the cross point of the differential input signal. Functional operation is obtained when the cross point is within the V

ICR

range

and the input swing lies within the V

i(p-p)

(DC) specification.

[2]

The PCK9448 is capable of driving 50

transmission lines on the incident edge. Each output drives one 50

parallel terminated

transmission line to a termination voltage of V

. Alternatively, the device drives up to two 50

series terminated transmission lines

= 3.3 V) or one 50

series terminated transmission line (for V

= 2.5 V).

[3]

Inputs have pull-down or pull-up resistors affecting the input current.

[4]

q(max)

is the DC current consumption of the device with all outputs open and the input in its default state or open.

[1]

ICR

(DC) is the cross point of the differential input signal. Functional operation is obtained when the cross point is within the V

ICR

range

and the input swing lies within the V

i(p-p)

(DC) specification.

[2]

The PCK9448 is capable of driving 50

transmission lines on the incident edge. Each output drives one 50

parallel terminated

transmission line to a termination voltage of V

. Alternatively, the device drives one 50

series terminated transmission line per output

at V

= 2.5 V.

[3]

Inputs have pull-down or pull-up resistors affecting the input current.

[4]

q(max)

is the DC current consumption of the device with all outputs open and the input in its default state or open.

Table 6:

Static characteristics (3.3 V)

amb

C to +85

C; V

= 3.3 V

5 %; unless otherwise specified.

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

HIGH-state input voltage

LVCMOS

2.0

+ 0.3

LOW-state input voltage

LVCMOS

0.3

+0.8

HIGH-state output voltage

24 mA

[2]

2.4

LOW-state output voltage

= 24 mA

[2]

0.55

= 12 mA

0.30

i(p-p)

peak-to-peak input voltage (PCLK)

LVPECL

250

ICR

[1]

common-mode input voltage range
(PCLK)

LVPECL

1.1

0.6

output impedance

input current

= V

or GND

[3]

300

q(max)

maximum quiescent current

all V

pins

[4]

2.0

Table 7:

Static characteristics (2.5 V)

amb

C to +85

C; V

= 2.5 V

5 %; unless otherwise specified.

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

HIGH-state input voltage

LVCMOS

1.7

+ 0.3

LOW-state input voltage

LVCMOS

0.3

+0.7

HIGH-state output voltage

15 mA

[2]

1.8

LOW-state output voltage

= 15 mA

0.6

i(p-p)

peak-to-peak input voltage (PCLK)

LVPECL

250

ICR

[1]

common-mode input voltage range
(PCLK)

LVPECL

1.0

0.7

output impedance

input current

= V

or GND

[3]

300

q(max)

maximum quiescent current

all V

pins

[4]

2.0

9397 750 12534

Product data sheet

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6 of 20

Philips Semiconductors

PCK9448

3.3 V/2.5 V LVCMOS 1 : 12 clock fan-out buffer

8.3 Dynamic characteristics

[1]

Dynamic characteristics apply for parallel output termination of 50

to V

[2]

ICR

(AC) is the cross-point of the differential input signal. Normal AC operation is obtained when the cross-point is within the V

ICR

range

and the input swing lies within the V

i(p-p)

(AC) specification. Violation of V

ICR

or V

i(p-p)

impacts static phase offset.

[3]

Setup and hold times are referenced to the falling edge of the selected clock signal input.

[4]

Violation of the 1.0 ns maximum input rise and fall time limit will affect the device propagation delay, device-to-device skew, reference
input pulse width, output duty cycle, and maximum frequency specifications.

Table 8:

Dynamic characteristics (3.3 V)

amb

C to +85

C; V

= 3.3 V

5 %; unless otherwise specified.

[1]

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

i(p-p)

input voltage (peak-to-peak value)
(PCLK, PCLK)

LVPECL

400

1000

ICR

[2]

common-mode input voltage range
(PCLK, PCLK)

LVPECL

1.3

0.8 V

output frequency

350

MHz

input frequency

350

MHz

sk(o)

output skew time

150

sk(pr)

process skew time

part-to-part

2.0

output duty cycle

< 170 MHz;

ref

= 50 %

PLH

LOW-to-HIGH propagation delay

PCLK to any Q

1.6

3.6

CCLK to any Q

1.3

3.3

PHL

HIGH-to-LOW propagation delay

PCLK to any Q

1.6

3.6

CCLK to any Q

1.3

3.3

PLZ

LOW to OFF-state propagation delay

OE to any Q

PHZ

HIGH to OFF-state propagation delay

OE to any Q

PZL

OFF-state to LOW propagation delay

OE to any Q

PZH

OFF-state to HIGH propagation delay

OE to any Q

setup time

CCLK to CLK_STOP

[3]

0.0

PCLK to CLK_STOP

[3]

0.0

hold time

CCLK to CLK_STOP

[3]

1.0

PCLK to CLK_STOP

[3]

1.5

rise time

output; 0.55 V to 2.4 V

0.1

1.0

CCLK input; 0.8 V to 2.0 V

1.0

[4]

fall time

output; 2.4 V to 0.55 V

0.1

1.0

CCLK input; 2.0 V to 0.8 V

1.0

[4]

9397 750 12534

Product data sheet

Rev. 01 -- 29 November 2005

7 of 20

Philips Semiconductors

PCK9448

3.3 V/2.5 V LVCMOS 1 : 12 clock fan-out buffer

[1]

Dynamic characteristics apply for parallel output termination of 50

to V

[2]

ICR

(AC) is the cross-point of the differential input signal. Normal AC operation is obtained when the cross-point is within the V

ICR

range

and the input swing lies within the V

i(p-p)

(AC) specification. Violation of V

ICR

or V

i(p-p)

impacts static phase offset.

[3]

See

Section 9 "Application information"

for part-to-part skew calculation.

[4]

Setup and hold times are referenced to the falling edge of the selected clock signal input.

Table 9:

Dynamic characteristics (2.5 V)

amb

C to +85

C; V

= 2.5 V

5 %; unless otherwise specified.

[1]

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

i(p-p)

input voltage (peak-to-peak value)
(PCLK, PCLK)

LVPECL

400

1000

ICR

[2]

common-mode input voltage range
(PCLK, PCLK)

LVPECL

1.2

0.8 V

input frequency

350

MHz

output frequency

350

MHz

sk(o)

output skew time

output-to-output

[3]

150

sk(pr)

process skew time

part-to-part; PCLK or
CCLK to any Q

2.7

output duty cycle

ref

= 50 %

PLH

LOW-to-HIGH propagation delay

PCLK to any Q

1.5

4.2

CCLK to any Q

1.7

4.4

PHL

HIGH-to-LOW propagation delay

PCLK to any Q

1.5

4.2

CCLK to any Q

1.7

4.4

PLZ

LOW to OFF-state propagation delay

OE to any Q

PHZ

HIGH to OFF-state propagation delay

OE to any Q

PZL

OFF-state to LOW propagation delay

OE to any Q

PZH

OFF-state to HIGH propagation delay

OE to any Q

setup time

CCLK to CLK_STOP

[4]

0.0

PCLK to CLK_STOP

[4]

0.0

hold time

CCLK to CLK_STOP

[4]

1.0

PCLK to CLK_STOP

[4]

1.5

rise time

input CCLK; 0.8 V to 2.0 V

1.0

output; 0.6 V to 1.8 V

0.1

1.0

fall time

input CCLK; 2.0 V to 0.8 V

1.0

output; 1.8 V to 0.6 V

0.1

1.0

9397 750 12534

Product data sheet

Rev. 01 -- 29 November 2005

9 of 20

Philips Semiconductors

PCK9448

3.3 V/2.5 V LVCMOS 1 : 12 clock fan-out buffer

Fig 5.

Propagation delay test reference
(PCLK/PCLK to Qn)

Fig 6.

Propagation delay test reference (CCLK to Qn)

Fig 7.

Pulse skew time (t

sk(p)

) test reference

The pin-to-pin skew is defined as the worst-case
difference in propagation delay between any similar
delay path within a single device.

The time from the output controlled edge to the
non-controlled edge, divided by the time between
output controlled edges, expressed as a percentage.

Fig 8.

Output skew time (t

sk(o)

)

Fig 9.

Output duty cycle (

)

(1) 2.4 V (V

= 3.3 V)

1.8 V (V

= 2.5 V)

(2) 0.55 V (V

= 3.3 V)

0.6 V (V

= 2.5 V)

Fig 10. Output transition time test reference

Fig 11. Setup and hold time (t

, t

)

002aaa729

PLH

PCLK

ICR

0.5V

GND

PCLK

PHL

002aab829

PLH

0.5V

GND

CCLK

PHL

0.5V

GND

002aab290

PLH

CCLK

0.5V

GND

0.5V

GND

PHL

sk(p)

PLH

PHL

002aab289

sk(o)

0.5V

GND

0.5V

GND

sk(o)

002aab291

0.5V

GND

= (t

100 %)

-----

002aab292

(1)

(2)

002aaa727

CCLK

PCLK

CLK_STOP

0.5V

GND

0.5V

GND

9397 750 12534

Product data sheet

Rev. 01 -- 29 November 2005

10 of 20

Philips Semiconductors

PCK9448

3.3 V/2.5 V LVCMOS 1 : 12 clock fan-out buffer

Application information

9.1 Driving transmission lines

The PCK9448 clock driver was designed to drive high speed signals in a terminated
transmission line environment. To provide the optimum flexibility to the user, the output
drivers were designed to exhibit the lowest impedance possible. With an output
impedance of 17

= 3.3 V), the outputs can drive either parallel or series

terminated transmission lines.

In most high performance clock networks, point-to-point distribution of signals is the
method of choice. In a point-to-point scheme, either series terminated or parallel
terminated transmission lines can be used. The parallel technique terminates the signal at
the end of the line with a 50

resistance to 0.5V

. This technique draws a fairly high

level of DC current, and thus only a single terminated line can be driven by each output of
the PCK9448 clock driver. For the series terminated case, however, there is no DC current
draw, thus the outputs can drive multiple series terminated lines.

Figure 12

, illustrates an

output driving a single series terminated line versus two series terminated lines in parallel.
When taken to its extreme, the fan-out of the PCK9448 clock driver is effectively doubled
due to its capability to drive multiple lines.

Fig 12. Single versus dual transmission lines

Zo = 50

002aaa722

Rs = 33

Zo = 50

Rs = 33

PCK9448

OUTPUT

BUFFER

OutB1

OutB0

Zo = 50

Rs = 33

PCK9448

OUTPUT

BUFFER

OutA

9397 750 12534

Product data sheet

Rev. 01 -- 29 November 2005

11 of 20

Philips Semiconductors

PCK9448

3.3 V/2.5 V LVCMOS 1 : 12 clock fan-out buffer

The waveform plots of

Figure 13

show simulation results of an output driving a single line

versus two lines. In both cases the drive capability of the PCK9448 output buffer is more
than sufficient to drive 50

transmission lines on the incident edge. Note from the delay

measurement in the simulations a delta of only 43 ps exists between the two differently
loaded outputs. This suggests that the dual line driving need not be used exclusively to
maintain the tight output-to-output skew of the PCK9448. The output waveform in

Figure 13

shows a step in the waveform; this step is caused by the impedance mismatch

seen looking into the driver. The parallel combination of the 33

series resistor plus the

output impedance does not match the parallel combination of the line impedances. The
voltage wave launched down the two lines will equal:

At the load end the voltage will double, due to the near unity reflection coefficient, to 2.5 V.
It will then increment towards the quiescent 3.0 V in steps separated by one round trip
delay (in this case 4.0 ns).

Since this step is well above the threshold region it will not cause any false clock
triggering, however designers may be uncomfortable with unwanted reflections on the
line. To better match the impedances when driving multiple lines, the situation in

Figure 14

should be used. In this case the series terminating resistors are reduced such that when
the parallel combination is added to the output buffer impedance the line impedance is
perfectly matched.

Fig 13. Single versus dual line termination waveforms

------------------------------

3.0

16.5

-----------------------------------

1.28 V

time (ns)

002aaa679

3.0

voltage

(V)

0.5

1.0

2.0

OutA
t

= 3.8956 ns

OutB
t

= 3.9386 ns

9397 750 12534

Product data sheet

Rev. 01 -- 29 November 2005

12 of 20

Philips Semiconductors

PCK9448

3.3 V/2.5 V LVCMOS 1 : 12 clock fan-out buffer

9.2 Power consumption of the PCK9448 and thermal management

The PCK9448 dynamic electrical (AC) specification is guaranteed for the entire operating
frequency range up to 350 MHz. The PCK9448 power consumption and the associated
long-term reliability may decrease the maximum frequency limit, depending on operating
condition such as clock frequency, supply voltage, output loading, ambient temperature,
vertical convection and thermal conductivity of package and board. This section describes
the impact of these parameters on the junction temperature and gives a guideline to
estimate the PCK9448 die junction temperature and the associated device reliability. The
long-term device reliability is a function of the die temperature; refer to

Table 10

Increased power consumption will increase the die junctIon temperature and impact the
device reliability (MTBF). According to the system-defined tolerable MTBF, the die junction
temperature of the PCK9448 needs to be controlled and the thermal impedance of the
board/package should be optimized. The power dissipated in the PCK9448 is represented
in

Equation 1

(1)

Where I

q(max)

is the static current consumption of the PCK9448, C

is the power

dissipation capacitance per output, (M)

represents the external capacitive output load,

N is the number of active outputs (N is always 12 in the case of the PCK9448). The
PCK9448 supports driving transmission lines to maintain high signal integrity and tight
timing parameters. Any transmission line will hide the limped capacitive load at the end of
the board trace, therefore,

is zero for controlled transmission line systems and can be

eliminated from

Equation 1

. Using parallel termination output termination results in

Equation 2

for power dissipation.

Fig 14. Optimized dual line termination

Zo = 50

002aaa723

Rs = 16

Zo = 50

Rs = 16

PCK9448

OUTPUT

BUFFER

Zo = 50

Table 10:

Die junction temperature and MTBF

Junction temperature (

MTBF (years)

100

20.4

110

9.1

120

4.2

130

2.0

tot

q max

(

)

clk

9397 750 12534

Product data sheet

Rev. 01 -- 29 November 2005

13 of 20

Philips Semiconductors

PCK9448

3.3 V/2.5 V LVCMOS 1 : 12 clock fan-out buffer

(2)

Equation 2

, P stands for the number of outputs with a parallel or Thevenin termination;

, I

, V

and I

are a function of the output termination technique;

is the clock

signal duty cycle. If transmission lines are used,

is zero in

Equation 2

and can be

eliminated. In general, the use of controlled transmission line techniques eliminates the
impact of the lumped capacitive loads at the end lines and greatly reduces the power
dissipation of the device.

Equation 3

describes the die junction temperature T

as a

function of the power consumption.

(3)

Where R

th(j-a)

is the thermal impedance of the package (junction-to-ambient) and T

amb

the ambient temperature. According to

Table 10

, the junction temperature can be used to

estimate the long-term device reliability. Further, combining

Equation 1

and

Equation 2

results in a maximum operating frequency for the PCK9448 in a series terminated
transmission line system,

Equation 4

(4)

j(max)

should be selected according to the MTBF system requirements and

Table 10

th(j-a)

can be derived from

Table 11

. The R

th(j-a)

represent data based on 1S2P boards;

using 2S2P boards will result in a lower thermal impedance than indicated below.

If the calculated maximum frequency is below 350 MHz, it becomes the upper clock speed
limit for the given application conditions. The following four derating charts describe the
safe frequency operation range for the PCK9448. The charts were calculated for a
maximum tolerable die junction temperature of 110

C (120

C), corresponding to an

estimated MTBF of 9.1 years (4 years), a supply voltage of 3.3 V and series terminated
transmission line or capacitive loading. Depending on a given set of these operating
conditions and the available device convection, a decision on the maximum operating
frequency can be made.

Table 11:

Thermal package impedance of the LQFP32

Convection (LFPM)

th(j-a)

(

C/W) (1P2S board)

th(j-a)

(

C/W) (2P2S board)

still air

100

200

300

400

500

tot

q max

(

)

clk

(

)

(

)

[

]

amb

tot

th j-a

(

)

clk max

(

)

-----------------------------------------

j max

(

)

amb

th j-a

(

)

------------------------------------

q max

(

)

(

)

9397 750 12534

Product data sheet

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Philips Semiconductors

PCK9448

3.3 V/2.5 V LVCMOS 1 : 12 clock fan-out buffer

11. Package outline

Fig 17. Package outline SOT358-1 (LQFP32)

UNIT

max.

(1)

REFERENCES

OUTLINE

VERSION

EUROPEAN

PROJECTION

ISSUE DATE

IEC

JEDEC

JEITA

1.6

0.20
0.05

1.45
1.35

0.25

0.4
0.3

0.18
0.12

7.1
6.9

0.8

9.15
8.85

0.9
0.5

7
0

0.25

0.1

0.2

DIMENSIONS (mm are the original dimensions)

Note

1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.

0.75
0.45

SOT358 -1

136E03

MS-026

03-02-25
05-11-09

(1)

7.1
6.9

9.15
8.85

0.9
0.5

detail X

(A )

Z D

Z E

pin 1 index

2.5

5 mm

scale

LQFP32: plastic low profile quad flat package; 32 leads; body 7 x 7 x 1.4 mm

SOT358-1

9397 750 12534

Product data sheet

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16 of 20

Philips Semiconductors

PCK9448

3.3 V/2.5 V LVCMOS 1 : 12 clock fan-out buffer

12. Soldering

12.1 Introduction to soldering surface mount packages

This text gives a very brief insight to a complex technology. A more in-depth account of
soldering ICs can be found in our

Data Handbook IC26; Integrated Circuit Packages

(document order number 9398 652 90011).

There is no soldering method that is ideal for all surface mount IC packages. Wave
soldering can still be used for certain surface mount ICs, but it is not suitable for fine pitch
SMDs. In these situations reflow soldering is recommended.

12.2 Reflow soldering

Reflow soldering requires solder paste (a suspension of fine solder particles, flux and
binding agent) to be applied to the printed-circuit board by screen printing, stencilling or
pressure-syringe dispensing before package placement. Driven by legislation and
environmental forces the worldwide use of lead-free solder pastes is increasing.

Several methods exist for reflowing; for example, convection or convection/infrared
heating in a conveyor type oven. Throughput times (preheating, soldering and cooling)
vary between 100 seconds and 200 seconds depending on heating method.

Typical reflow peak temperatures range from 215

C to 270

C depending on solder paste

material. The top-surface temperature of the packages should preferably be kept:

below 225

C (SnPb process) or below 245

C (Pb-free process)

for all BGA, HTSSON..T and SSOP..T packages

for packages with a thickness

2.5 mm

for packages with a thickness < 2.5 mm and a volume

350 mm

so called

thick/large packages.

below 240

C (SnPb process) or below 260

C (Pb-free process) for packages with a

thickness < 2.5 mm and a volume < 350 mm

so called small/thin packages.

Moisture sensitivity precautions, as indicated on packing, must be respected at all times.

12.3 Wave soldering

Conventional single wave soldering is not recommended for surface mount devices
(SMDs) or printed-circuit boards with a high component density, as solder bridging and
non-wetting can present major problems.

To overcome these problems the double-wave soldering method was specifically
developed.

If wave soldering is used the following conditions must be observed for optimal results:

Use a double-wave soldering method comprising a turbulent wave with high upward
pressure followed by a smooth laminar wave.

For packages with leads on two sides and a pitch (e):

larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be

parallel to the transport direction of the printed-circuit board;

9397 750 12534

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3.3 V/2.5 V LVCMOS 1 : 12 clock fan-out buffer

smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the

transport direction of the printed-circuit board.

The footprint must incorporate solder thieves at the downstream end.

For packages with leads on four sides, the footprint must be placed at a 45

angle to

the transport direction of the printed-circuit board. The footprint must incorporate
solder thieves downstream and at the side corners.

During placement and before soldering, the package must be fixed with a droplet of
adhesive. The adhesive can be applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the adhesive is cured.

Typical dwell time of the leads in the wave ranges from 3 seconds to 4 seconds at 250

or 265

C, depending on solder material applied, SnPb or Pb-free respectively.

A mildly-activated flux will eliminate the need for removal of corrosive residues in most
applications.

12.4 Manual soldering

Fix the component by first soldering two diagonally-opposite end leads. Use a low voltage
(24 V or less) soldering iron applied to the flat part of the lead. Contact time must be
limited to 10 seconds at up to 300

When using a dedicated tool, all other leads can be soldered in one operation within
2 seconds to 5 seconds between 270

C and 320

12.5 Package related soldering information

[1]

For more detailed information on the BGA packages refer to the

(LF)BGA Application Note (AN01026);

order a copy from your Philips Semiconductors sales office.

[2]

All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the
maximum temperature (with respect to time) and body size of the package, there is a risk that internal or
external package cracks may occur due to vaporization of the moisture in them (the so called popcorn
effect). For details, refer to the Drypack information in the

Data Handbook IC26; Integrated Circuit

Packages; Section: Packing Methods.

[3]

These transparent plastic packages are extremely sensitive to reflow soldering conditions and must on no
account be processed through more than one soldering cycle or subjected to infrared reflow soldering with
peak temperature exceeding 217

C measured in the atmosphere of the reflow oven. The package

body peak temperature must be kept as low as possible.

Table 12:

Suitability of surface mount IC packages for wave and reflow soldering methods

Package

[1]

Soldering method

Wave

Reflow

[2]

BGA, HTSSON..T

[3]

, LBGA, LFBGA, SQFP,

SSOP..T

[3]

, TFBGA, VFBGA, XSON

not suitable

suitable

DHVQFN, HBCC, HBGA, HLQFP, HSO, HSOP,
HSQFP, HSSON, HTQFP, HTSSOP, HVQFN,
HVSON, SMS

not suitable

[4]

suitable

PLCC

[5]

, SO, SOJ

suitable

LQFP, QFP, TQFP

not recommended

[5] [6]

suitable

SSOP, TSSOP, VSO, VSSOP

not recommended

[7]

suitable

CWQCCN..L

[8]

, PMFP

[9]

, WQCCN..L

[8]

not suitable

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Philips Semiconductors

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3.3 V/2.5 V LVCMOS 1 : 12 clock fan-out buffer

[4]

These packages are not suitable for wave soldering. On versions with the heatsink on the bottom side, the
solder cannot penetrate between the printed-circuit board and the heatsink. On versions with the heatsink
on the top side, the solder might be deposited on the heatsink surface.

[5]

If wave soldering is considered, then the package must be placed at a 45

angle to the solder wave

direction. The package footprint must incorporate solder thieves downstream and at the side corners.

[6]

Wave soldering is suitable for LQFP, QFP and TQFP packages with a pitch (e) larger than 0.8 mm; it is
definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm.

[7]

Wave soldering is suitable for SSOP, TSSOP, VSO and VSSOP packages with a pitch (e) equal to or larger
than 0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm.

[8]

Image sensor packages in principle should not be soldered. They are mounted in sockets or delivered
pre-mounted on flex foil. However, the image sensor package can be mounted by the client on a flex foil by
using a hot bar soldering process. The appropriate soldering profile can be provided on request.

[9]

Hot bar soldering or manual soldering is suitable for PMFP packages.

13. Abbreviations

14. Revision history

Table 13:

Abbreviations

Acronym

Description

ESD

ElectroStatic Discharge

HBM

Human Body Model

Machine Model

MTBF

Mean Time Between Failures

LFPM

Linear Feet Per Minute

LVPECL

Low Voltage Positive Emitter Coupled Logic

LVCMOS

Low Voltage Complementary Metal Oxide Silicon

Table 14:

Revision history

Document ID

Release date

Data sheet status

Change notice

Doc. number

Supersedes

PCK9448_1

20051129

Product data sheet

9397 750 12534

Philips Semiconductors

PCK9448

3.3 V/2.5 V LVCMOS 1 : 12 clock fan-out buffer

9397 750 12534

Product data sheet

Rev. 01 -- 29 November 2005

19 of 20

15. Data sheet status

[1]

Please consult the most recently issued data sheet before initiating or completing a design.

[2]

The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at
URL http://www.semiconductors.philips.com.

[3]

For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status.

16. Definitions

Short-form specification -- The data in a short-form specification is
extracted from a full data sheet with the same type number and title. For
detailed information see the relevant data sheet or data handbook.

Limiting values definition -- Limiting values given are in accordance with
the Absolute Maximum Rating System (IEC 60134). Stress above one or
more of the limiting values may cause permanent damage to the device.
These are stress ratings only and operation of the device at these or at any
other conditions above those given in the Characteristics sections of the
specification is not implied. Exposure to limiting values for extended periods
may affect device reliability.

Application information -- Applications that are described herein for any
of these products are for illustrative purposes only. Philips Semiconductors
make no representation or warranty that such applications will be suitable for
the specified use without further testing or modification.

17. Disclaimers

Life support -- These products are not designed for use in life support
appliances, devices, or systems where malfunction of these products can
reasonably be expected to result in personal injury. Philips Semiconductors

customers using or selling these products for use in such applications do so
at their own risk and agree to fully indemnify Philips Semiconductors for any
damages resulting from such application.

Right to make changes -- Philips Semiconductors reserves the right to
make changes in the products - including circuits, standard cells, and/or
software - described or contained herein in order to improve design and/or
performance. When the product is in full production (status `Production'),
relevant changes will be communicated via a Customer Product/Process
Change Notification (CPCN). Philips Semiconductors assumes no
responsibility or liability for the use of any of these products, conveys no
license or title under any patent, copyright, or mask work right to these
products, and makes no representations or warranties that these products are
free from patent, copyright, or mask work right infringement, unless otherwise
specified.

18. Trademarks

Notice -- All referenced brands, product names, service names and
trademarks are the property of their respective owners.

19. Contact information

For additional information, please visit: http://www.semiconductors.philips.com

For sales office addresses, send an email to: sales.addresses@www.semiconductors.philips.com

Level

Data sheet status

[1]

Product status

[2] [3]

Definition

Objective data

Development

This data sheet contains data from the objective specification for product development. Philips
Semiconductors reserves the right to change the specification in any manner without notice.

Preliminary data

Qualification

This data sheet contains data from the preliminary specification. Supplementary data will be published
at a later date. Philips Semiconductors reserves the right to change the specification without notice, in
order to improve the design and supply the best possible product.

III

Product data

Production

This data sheet contains data from the product specification. Philips Semiconductors reserves the
right to make changes at any time in order to improve the design, manufacturing and supply. Relevant
changes will be communicated via a Customer Product/Process Change Notification (CPCN).

All rights are reserved. Reproduction in whole or in part is prohibited without the prior
written consent of the copyright owner. The information presented in this document does
not form part of any quotation or contract, is believed to be accurate and reliable and may
be changed without notice. No liability will be accepted by the publisher for any
consequence of its use. Publication thereof does not convey nor imply any license under
patent- or other industrial or intellectual property rights.

Date of release: 29 November 2005

Document number: 9397 750 12534

Published in The Netherlands

Philips Semiconductors

PCK9448

3.3 V/2.5 V LVCMOS 1 : 12 clock fan-out buffer

20. Contents

General description . . . . . . . . . . . . . . . . . . . . . . 1

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Ordering information . . . . . . . . . . . . . . . . . . . . . 2

Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2

Pinning information . . . . . . . . . . . . . . . . . . . . . . 3

5.1

Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

5.2

Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3

Functional description . . . . . . . . . . . . . . . . . . . 4

6.1

Function table . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 4

Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 4

8.1

General characteristics . . . . . . . . . . . . . . . . . . . 4

8.2

Static characteristics. . . . . . . . . . . . . . . . . . . . . 5

8.3

Dynamic characteristics . . . . . . . . . . . . . . . . . . 6

Application information. . . . . . . . . . . . . . . . . . 10

9.1

Driving transmission lines . . . . . . . . . . . . . . . . 10

9.2

Power consumption of the PCK9448 and
thermal management . . . . . . . . . . . . . . . . . . . 12

Test information . . . . . . . . . . . . . . . . . . . . . . . . 14

Package outline . . . . . . . . . . . . . . . . . . . . . . . . 15

Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

12.1

Introduction to soldering surface mount
packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

12.2

Reflow soldering . . . . . . . . . . . . . . . . . . . . . . . 16

12.3

Wave soldering . . . . . . . . . . . . . . . . . . . . . . . . 16

12.4

Manual soldering . . . . . . . . . . . . . . . . . . . . . . 17

12.5

Package related soldering information . . . . . . 17

Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Revision history . . . . . . . . . . . . . . . . . . . . . . . . 18

Data sheet status . . . . . . . . . . . . . . . . . . . . . . . 19

Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Contact information . . . . . . . . . . . . . . . . . . . . 19

Part Number PCK9448

Document Outline