Document Outline
- FEATURES
- DESCRIPTION
- ORDERING INFORMATION
- PIN CONFIGURATION
- PIN DESCRIPTIONS
- FUNCTION TABLE
- FUNCTIONAL BLOCK DIAGRAM
- ABSOLUTE MAXIMUM RATINGS
- RECOMMENDED OPERATING CONDITIONS
- ELECTRICAL CHARACTERISTICS
- TIMING REQUIREMENTS
- SWITCHING CHARACTERISTICS
- CHARACTERISTIC CURVES
- PARAMETER MEASUREMENT INFORMATION
- PACKAGE
- Data sheet status
- Definitions
- Disclaimers
Philips
Semiconductors
PCK2509SA
50150 MHz 1:9 SDRAM clock driver
Product specification
ICL03 -- PC Motherboard ICs; Logic Products Group
2000 Dec 01
INTEGRATED CIRCUITS
Philips Semiconductors
Product specification
PCK2509SA
50150 MHz 1:9 SDRAM clock driver
2
2000 Dec 01
8532228 25137
FEATURES
·
Phase-Locked Loop Clock distribution for
PC100/PC133 SDRAM applications
·
JEDEC compliant operation--PLL reamins locked when outputs
are disabled.
·
See PCK2509SL for low power version where PLL goes into
standby when outputs are disabled..
·
Spread Spectrum clock compatible
·
Operating frequency 50 to 150 MHz
·
(t
phase
error
jitter) at 100 to133 MHz =
±
50 ps
·
Jitter (peak-peak) at 100 to 133 MHz =
±
80 ps
·
Jitter (cycle-cycle) at 100 to 133 MHz = 65 ps
·
Pin-to-pin skew
<
200 ps
·
Available in plastic 24-Pin TSSOP
·
Distributes one clock input to one bank of five outputs and
one bank of four outputs
·
External Feedback (FBIN) terminal Is used to synchronize the
outputs to the clock input
·
On-Chip series damping resistors
·
No external RC network required
·
Operates at 3.3 V
·
Inputs compatible with 2.5 V and 3.3 V ranges
·
See page 7 for Characteristic curves
DESCRIPTION
The PCK2509SA is a high-performance, low-skew, low-jitter,
phase-locked loop (PLL) clock driver. It uses a PLL to precisely
align, in both frequency and phase, the feedback (FBOUT) output to
the clock (CLK) input signal. It is specifically designed for use with
synchronous DRAMs. The PCK2509SA operates at 3.3 V V
CC
and
is input compatible with both 2.5 V and 3.3 V input voltage ranges. It
also provides integrated series-damping resistors that make it ideal
for driving point-to-point loads.
One bank of five outputs and one bank of four outputs provide nine
low-skew, low-jitter copies of CLK. Output signal duty cycles are
adjusted to 50 percent, independent of the duty cycle at CLK. Each
bank of outputs can be enabled or disabled separately via the
control (1G and 2G) inputs. When the G inputs are high, the outputs
switch in phase and frequency with CLK; when the G inputs are low,
the outputs are disabled to the logiclow state.
Unlike many products containing PLLs, the PCK2509SA does not
require external RC networks. The loop filter for the PLL is included
on-chip, minimizing component count, board space, and cost.
Because it is based on PLL circuitry, the PCK2509SA requires a
stabilization time to achieve phase lock of the feedback signal to the
reference signal. This stabilization time is required, following power up
and application of a fixed-frequency, fixed-phase signal at CLK, and
following any changes to the PLL reference or feedback signals. The
PLL can be bypassed for test purposes by strapping AV
CC
to ground.
The PCK2509SA is characterized for operation from 0
°
C to +70
°
C.
PIN CONFIGURATION
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
AGND
CLK
AV
CC
V
CC
V
CC
2Y0
1Y0
2Y1
GND
1Y1
GND
2Y3
1Y2
2Y2
GND
V
CC
FBIN
GND
1Y3
1Y4
V
CC
1G
FBOUT
SW00389
2G
ORDERING INFORMATION
PACKAGES
TEMPERATURE RANGE
ORDER CODE
DRAWING NUMBER
24-Pin Plastic TSSOP
0
°
C to +70
°
C
PCK2509SADH
SOT355-1
Philips Semiconductors
Product specification
PCK2509SA
50150 MHz 1:9 SDRAM clock driver
2000 Dec 01
3
PIN DESCRIPTIONS
PIN NUMBER
SYMBOL
TYPE
NAME, FUNCTION, and DIRECTION
1
AGND
GND
Analog ground. AGND provides the ground reference for the analog circuitry.
2, 10, 15, 22
V
CC
PWR
Power supply
3, 4, 5, 8, 9
1Y (04)
OUT
Clock outputs. These outputs provide low-skew copies of CLK. Output bank 1Y(04) is enabled
via the1G input. These outputs can be disabled to a logic LOW state by de-asserting the 1G control
input. Each output has an integrated 25
series-damping resistor.
6, 7, 18, 19
GND
GND
Ground
11
1G
IN
Output bank enable. 1G is the output enable for outputs 1Y(04). When 1G is LOW, outputs
1Y(04) are disabled to a logic LOW state. When 1G is HIGH, all outputs 1Y(04) are enabled and
switch at the same frequency as CLK.
12
FBOUT
OUT
Feedback output. FBOUT is dedicated for external feedback. It switches at the same frequency as
CLK. When externally wired to FBIN, FBOUT completes the feedback loop of the PLL. FBOUT has
an integrated 25
series-damping resistor.
13
FBIN
IN
Feedback input. FBIN provides the feedback signal to the internal PLL. FBIN must be hard-wired
to FBOUT to complete the PLL. The integrated PLL synchronizes CLK and FBIN so that there is
nominally zero phase error between CLK and FBIN.
14
2G
IN
Output bank enable. 2G is the output enable for outputs 2Y(03). When 2G is LOW, outputs
2Y(03) are disabled to a logic LOW state. When 2G is HIGH, all outputs 2Y(03) are enabled and
switch at the same frequency as CLK.
16, 17, 20, 21
2Y (03)
OUT
Clock outputs. These outputs provide low-skew copies of CLK. Output bank 2Y(03) is enabled
via the 2G input. These outputs can be disabled to a logic LOW state by de-asserting the 2G
control input. Each output has an integrated 25
series-damping resistor.
23
AV
CC
PWR
Analog power supply. AV
CC
provides the power reference for the analog circuitry. In addition,
AV
CC
can be used to bypass the PLL for test purposes. When AV
CC
is strapped to ground, PLL is
bypassed and CLK is buffered directly to the device outputs.
24
CLK
IN
Clock input. CLK provides the clock signal to be distributed by the PCK2509SA clock driver. CLK
is used to provide the reference signal to the integrated PLL that generates the clock output
signals. CLK must have a fixed frequency and fixed phase for the PLL to obtain phase lock. Once
the circuit is powered up and a valid CLK signal is applied, a stabilization time is required for the
PLL to phase lock the feedback signal to its reference signal.
FUNCTION TABLE
INPUTS
OUTPUTS
1G
2G
CLK
1Y (04)
2Y (03)
FBOUT
X
X
L
L
L
L
L
L
H
L
L
H
L
H
H
L
H
H
H
L
H
H
L
H
H
H
H
H
H
H
Philips Semiconductors
Product specification
PCK2509SA
50150 MHz 1:9 SDRAM clock driver
2000 Dec 01
4
FUNCTIONAL BLOCK DIAGRAM
FBOUT
AV
CC
FBIN
CLK
1G
11
24
13
23
PLL
2Y3
2Y2
2Y1
2Y0
1Y4
1Y3
1Y2
1Y1
1Y0
3
4
5
8
9
21
20
17
16
12
SW00388
2G
14
The PLL clock distribution device and A[L]VC registered drivers reduce
signal loads on the memory controller and prevent timing delays and
waveform distortions that would cause unreliable operation
SDRAM
SDRAM
SDRAM
SDRAM
SDRAM
SDRAM
SDRAM
SDRAM
SDRAM
A[L]VC
PCK2509SA
A[L]VC
FRONT SIDE
A[L]VC
SW00431
Philips Semiconductors
Product specification
PCK2509SA
50150 MHz 1:9 SDRAM clock driver
2000 Dec 01
5
ABSOLUTE MAXIMUM RATINGS
1
In accordance with the Absolute Maximum Rating System (IEC 134)
SYMBOL
PARAMETER
CONDITION
LIMITS
UNIT
SYMBOL
PARAMETER
CONDITION
MIN
MAX
UNIT
AV
CC
Supply voltage range
Note 2
< V
CC
+ 0.7
V
V
CC
Supply voltage range
0.5
+4.6
V
I
IK
Input clamp current
V
I
< 0
50
mA
V
I
Input voltage range
Note 3
0.5
6.5
V
I
OK
Output clamp current
V
O
> V
CC
or V
O
< 0
±
50
mA
V
O
Output voltage range
Notes 3, 4
0.5
V
CC
+ 0.5
V
I
O
DC output source or sink current
V
O
= 0 to V
CC
±
50
mA
T
STG
Storage temperature range
65
+150
°
C
P
TOT
Power dissipation per package
700
mW
NOTES:
1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the
device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to
absolute-maximum-rated conditions for extended periods may affect device reliability.
2. AV
CC
must not exceed V
CC
3. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
4. This value is limited to 4.6 V maximum.
RECOMMENDED OPERATING CONDITIONS
1
SYMBOL
PARAMETER
CONDITIONS
LIMITS
UNIT
SYMBOL
PARAMETER
CONDITIONS
MIN
MAX
UNIT
V
CC
, AV
CC
Supply voltage
3
3.6
V
V
IH
HIGH level input voltage
2
V
V
IL
LOW level input voltage
0.8
V
V
I
Input voltage
0
V
CC
V
T
amb
Operating ambient temperature range in free air
0
+70
°
C
NOTE:
1. Unused inputs must be held high or low to prevent them from floating.
ELECTRICAL CHARACTERISTICS
Over recommended operating free-air temperature range (unless otherwise specified)
SYMBOL
PARAMETER
TEST CONDITIONS
LIMITS
UNIT
SYMBOL
PARAMETER
AV
CC
, V
CC
(V)
OTHER
MIN
TYP
MAX
UNIT
V
IK
Input clamp voltage
3
I
I
= 18mA
1.2
V
MIN to MAX
I
OH
= 100
µ
A
V
CC
0.2
V
OH
HIGH level output voltage
3
I
OH
= 12mA
2.1
V
3
I
OH
= 6mA
2.4
MIN to MAX
I
OL
= 100
µ
A
0.2
V
OL
LOW level output voltage
3
I
OL
= 12mA
0.8
V
3
I
OL
= 6mA
0.55
I
I
Input current
3.6
V
I
= V
CC
or GND
±
5
µ
A
I
CC
1
Quiescent supply current
3.6
V
I
= V
CC
or GND;
I
O
= 0, outputs: LOW or HIGH
10
µ
A
I
CC
Additional supply current per
input pin
3.3 to 3.6
One input at V
CC
0.6V;
other inputs at V
CC
or GND
500
µ
A
C
I
Input capacitance
3.3
V
I
= V
CC
or GND
2.8
pF
C
O
Output capacitance
3.3
V
O
= V
CC
or GND
5.4
pF
NOTE:
1. For I
CCA
and I
CC
vs. Frequency, see Figures 1 and 2.
Philips Semiconductors
Product specification
PCK2509SA
50150 MHz 1:9 SDRAM clock driver
2000 Dec 01
6
TIMING REQUIREMENTS
Over recommended ranges of supply voltage and operating free-air temperature.
SYMBOL
PARAMETER
MIN
MAX
UNIT
f
CLK
Clock frequency
50
150
MHz
Input clock duty cycle
40
60
%
Stabilization time
1
1
ms
NOTE:
1. Time required for the integrated PLL circuit to obtain phase lock of its feedback signal to its reference signal. For phase lock to be obtained,
a fixed-frequency, fixed-phase reference signal must be present at CLK. Until phase lock is obtained, the specifications for propagation
delay, skew, and jitter parameters given in the switching characteristics table are not applicable.
SWITCHING CHARACTERISTICS
Over recommended ranges of supply voltage and operating free-air temperature, C
L
= 30 pF
PARAMETER
FROM
TO
V
CC
, AV
CC
= 3.3 V
±
0.3 V
UNIT
PARAMETER
(INPUT)/CONDITION
(OUTPUT)
MIN
TYP
MAX
UNIT
t
2
CLKIN
= 100 MHz to 133 MHz
FBIN
100
100
ps
t
phase error
2
CLKIN
= 66 MHz
FBIN
125
125
ps
t
phase error
, jitter
1,
3
CLKIN
= 100 MHz to 133 MHz
FBIN
50
50
ps
t
SK(0)
4
Any Y or FBOUT
Any Y or FBOUT
200
ps
jitter
(peak-peak)
CLKIN = 66 MHz to 133 MHz
Any Y or FBOUT
80
80
ps
jitter
(cycle-cycle)
1
CLKIN = 66 MHz to 133 MHz
Any Y or FBOUT
|65|
ps
Duty cycle reference
1
F(CLKIN
>
60 MHz)
Any Y or FBOUT
47
53
%
t
r
1
V
O
= 0.4 to 2 V
Any Y or FBOUT
2.5
1
V/ns
t
f
1
V
O
= 0.4 to 2 V
Any Y or FBOUT
2.5
1
V/ns
NOTES:
1. These parameters are not production tested.
2. This is considered as static phase offset.
3. Phase error does not include jitter. (t
phase error
= static t
phase error
jitter
(cycle-cycle)
).
4. The t
SK(0)
specification is only valid for outputs with equal loading.
Philips Semiconductors
Product specification
PCK2509SA
50150 MHz 1:9 SDRAM clock driver
2000 Dec 01
7
CHARACTERISTIC CURVES
ANALOG SUPPL
Y
CURRENT
(mA)
CLOCK FREQUENCY (MHz)
SW00435
AV
CC
= V
CC
= 3.3 V
T
amb
= 25
°
C
0
1
2
3
4
5
6
7
8
30
40
50
60
70
80
90
100
11
0
120
130
140
150
Figure 1. Analog supply current vs. clock frequency
SUPPL
Y
CURRENT
(mA)
CLOCK FREQUENCY (MHz)
SW00434
AV
CC
= V
CC
= 3.3 V
T
amb
= 25
°
C
0
10
20
30
40
50
60
70
80
90
100
30
40
50
60
70
80
90
100
11
0
120
130
140
150
Figure 2. Supply current vs. clock frequency
0
50
100
150
200
PEAK-TO-PEAK JITTER (ps)
CLOCK FREQUENCY (MHz)
SW00433
AV
CC
= V
CC
= 3.3 V
C
(LF)
= 12 pF; T
amb
= 25
°
C
50
100
133
150
Figure 3. Peak-to-peak jitter vs. clock frequency
0
50
100
150
200
50
60
70
80
90
100
110
120
130
140
CYCLE-TO-CYCLE JITTER (ps)
CLOCK FREQUENCY (MHz)
SW00432
AV
CC
= V
CC
= 3.3 V
C
(LF)
= 12 pF; T
amb
= 25
°
C
Figure 4. Cycle-to-cycle jitter vs. clock frequency
PHASE OFFSET
(ps)
DELAY LENGTH (ns)
SW00439
40
20
0
20
40
60
80
100
0
2
4
6
8
10
V
CC
= 3.3 V; C
(LF)
= 30 pF; f = 100 MHz
Figure 5. Phase offset vs. delay length
Philips Semiconductors
Product specification
PCK2509SA
50150 MHz 1:9 SDRAM clock driver
2000 Dec 01
8
PARAMETER MEASUREMENT INFORMATION
SW00384
3V
0V
V
OH
V
OL
OUTPUT
INPUT
50% V
CC
50% V
CC
t
f
t
r
2 V
0.4 V
2 V
0.4 V
FROM OUTPUT
UNDER TEST
30 pF
500
LOAD CIRCUIT FOR OUTPUTS
VOLTAGE WAVEFORMS & PHASE ERROR TIMES
NOTES:
1. C
L
includes probe and jig capacitance.
2. All input pulses are supplied by generators having the following characteristics: PRR
100 MHz, Z
O
= 50
, t
r
1.2 ns, t
f
1.2 ns.
3. The outputs are measured one at a time with one transition per measurement.
t
pe
Figure 6. Load Circuit and Voltage Waveforms
FBIN
CLKIN
t
phase error
FBOUT
ANY Y
t
SK(0)
ANY Y
ANY Y
t
SK(0)
SW00385
Figure 7. Phase Error and Skew Calculations
Philips Semiconductors
Product specification
PCK2509SA
50150 MHz 1:9 SDRAM clock driver
2000 Dec 01
9
TSSOP24:
plastic thin shrink small outline package; 24 leads; body width 4.4 mm
SOT355-1
Philips Semiconductors
Product specification
PCK2509SA
50150 MHz 1:9 SDRAM clock driver
2000 Dec 01
10
Definitions
Short-form specification -- The data in a short-form specification is extracted from a full data sheet with the same type number and title. For
detailed information see the relevant data sheet or data handbook.
Limiting values definition -- Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one
or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or
at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended
periods may affect device reliability.
Application information -- Applications that are described herein for any of these products are for illustrative purposes only. Philips
Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or
modification.
Disclaimers
Life support -- These products are not designed for use in life support appliances, devices or systems where malfunction of these products can
reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications
do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application.
Right to make changes -- Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard
cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no
responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these
products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless
otherwise specified.
Philips Semiconductors
811 East Arques Avenue
P.O. Box 3409
Sunnyvale, California 940883409
Telephone 800-234-7381
©
Copyright Philips Electronics North America Corporation 2000
All rights reserved. Printed in U.S.A.
Date of release: 12-00
Document order number:
9397 750 07845
Philips
Semiconductors
Data sheet
status
Objective
specification
Preliminary
specification
Product
specification
Product
status
Development
Qualification
Production
Definition
[1]
This data sheet contains the design target or goal specifications for product development.
Specification may change in any manner without notice.
This data sheet contains preliminary data, and supplementary data will be published at a later date.
Philips Semiconductors reserves the right to make changes at any time without notice in order to
improve design and supply the best possible product.
This data sheet contains final specifications. Philips Semiconductors reserves the right to make
changes at any time without notice in order to improve design and supply the best possible product.
Data sheet status
[1]
Please consult the most recently issued datasheet before initiating or completing a design.
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